US20080121417A1 - Package substrate having embedded capacitor - Google Patents
Package substrate having embedded capacitor Download PDFInfo
- Publication number
- US20080121417A1 US20080121417A1 US11/623,553 US62355307A US2008121417A1 US 20080121417 A1 US20080121417 A1 US 20080121417A1 US 62355307 A US62355307 A US 62355307A US 2008121417 A1 US2008121417 A1 US 2008121417A1
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- Prior art keywords
- layer
- package substrate
- circuit board
- metal layer
- embedded
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Definitions
- the present invention relates to a package substrate, and more particularly to a package substrate having embedded capacitor.
- Embedded capacitor can be integrated into a package substrate in the same fabrication process to enhance the efficiency of the active components inside an electronic package, improve electrical performance and lower assembling cost. Therefore, it has become the mainstream method for fabricating electronic carrier.
- the development of embedded capacitor is mainly aiming toward small size ceramic capacitors.
- ceramic capacitors can be classified into single layer ceramic capacitors (SLCC) and multi-layer ceramic capacitors (MLCC), also known as discrete capacitors.
- SLCC single layer ceramic capacitors
- MLCC multi-layer ceramic capacitors
- the capacitance of the conventional discrete capacitor is low and has a low dielectric constant, they could hardly enhance the performance of a conventional circuit substrate.
- FIG. 1 is a schematic diagram of a conventional package substrate having embedded capacitor.
- the internal structure of the package substrate 100 and its fabrication process are roughly as follows. First, a core board 110 , a plurality of dielectric materials 121 ⁇ 124 and two copper foils 142 and 144 soldered with a plurality of discrete capacitors 130 are provided. Then, the dielectric materials 121 ⁇ 124 and the two copper foils 142 and 144 having the discrete capacitors 130 are aligned and compressed to the core board 110 . Thus, the two copper foils 142 and 144 and the discrete capacitors 130 are located between the upper dielectric materials 121 , 122 and the lower dielectric materials 123 , 124 respectively to form a core laminated board 160 .
- a mechanical drilling process is performed to form a plurality of conductive through holes 150 inside the core laminated board 160 that averts the discrete capacitors 130 and connects the upper and lower copper foils 142 and 144 .
- a surface circuit 162 of the core laminated board 160 can connect with the discrete capacitors 130 through the via hole 164 .
- the discrete capacitors 130 have to avert the conductive through hole 150 , the usable area and location for disposing the capacitors 130 are constrained by the number and locations of the conductive through holes 150 and the degree of freedom of disposing the capacitors 130 is lowered. In the meantime, the discrete capacitors 130 are easily damaged or broken in the process of compressing the substrate. As a result, the reliability of the capacitors 130 is lowered.
- the present invention directs to a package substrate having embedded capacitor for enhancing the space and degree of freedom of disposing the embedded capacitor.
- the present invention also directs to a package substrate having embedded capacitor such that the performance of the package substrate is enhanced by using a dielectric material with high dielectric constant and low dielectric loss.
- the present invention directs to a package substrate having embedded capacitor such that the embedded capacitor is protected from damage by covering it with a passivation layer.
- the present invention provides a package substrate having embedded capacitor.
- the package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor and at least one metal layer. At least one wiring layer is disposed on a surface of the core circuit board and a conductive through hole of the core circuit board is connected to the wiring layer.
- the dielectric layer covers the wiring layer and has at least one via hole.
- the embedded capacitor is connected to the metal layer and is embedded within the dielectric layer.
- the metal layer covers the dielectric layer and connects to the wiring layer through the via hole.
- the present invention also provides a package substrate having embedded capacitor.
- the package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer.
- the embedded capacitor is embedded within the first core circuit board and connected to the metal layer.
- a wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer.
- the dielectric layer is laminated between the first core circuit board and the second core circuit board.
- the present invention also provides a package substrate having embedded capacitor.
- the package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. At least one metal layer is disposed on a surface of the core circuit board and at least one conductive through hole of the core circuit board is connected to the metal layer.
- the embedded capacitor is embedded within the core circuit board and connected to the metal layer.
- the dielectric layer covers the wiring layer and has an embedded hole. Furthermore, the wiring layer covers the dielectric layer and is electrically connected to the embedded hole.
- the package substrate further includes a first passivation layer covering the embedded capacitor.
- the metal layer has an opening and the opening exposes a surface of the embedded capacitor.
- the package substrate further includes a second passivation layer covering the surface of the embedded capacitor.
- the first passivation layer is fabricated using epoxy resin or polyimide, and the second passivation layer can be fabricated using epoxy resin or polyimide too.
- the package substrate further includes at least one surface wiring layer disposed on a surface of the package substrate.
- the surface wiring layer has at least one contact electrically connected to the metal layer or the wiring layer.
- the package substrate further includes a solder mask layer covering the surface wiring layer. The solder mask layer has at least one opening that exposes the contact.
- the present invention also provides a package substrate having embedded capacitor.
- the package substrate includes a core board, an embedded capacitor, a first passivation layer and a metal layer.
- the embedded capacitor is embedded within the core board and the first passivation layer covers the embedded capacitor.
- the metal layer covers the core board and is connected to the embedded capacitor.
- the metal layer has an opening and the opening exposes a surface of the embedded capacitor.
- the package substrate further includes a second passivation layer covering the surface of the embedded capacitor.
- the first passivation layer is fabricated using epoxy resin or polyimide, and the second passivation layer can be fabricated using epoxy resin or polyimide too.
- the embedded capacitor in the present invention can be disposed in a suitable location without having to avert the conductive through hole. Therefore, the space and degree of freedom for disposing the embedded capacitors is enhanced.
- capacitors fabricated using high dielectric constant and low dielectric loss material such as polymer-ceramic composite can be used instead of the conventional discrete capacitors so as to enhance the performance of the package substrate.
- the embedded capacitors of the present invention is covered with at least one passivation layer to prevent the embedded capacitors from receiving possible damage in the process of compressing the substrate. Hence, overall reliability of the package substrate is improved.
- FIG. 1 is a schematic diagram of a conventional package substrate having embedded capacitor.
- FIG. 2 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a first embodiment of the present invention.
- FIG. 3 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a second embodiment of the present invention.
- FIG. 4 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a third embodiment of the present invention.
- FIG. 5 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a fourth embodiment of the present invention.
- FIG. 6 is a schematic diagram of a portion of a package substrate using the substrate having embedded capacitor in FIG. 3 as the core layer.
- FIG. 2 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a first embodiment of the present invention.
- the package substrate 200 mainly includes a core circuit board 210 , a dielectric layer 220 , at least one embedded capacitor 230 and a metal layer 240 .
- the core circuit board 210 is, for example, a copper foil substrate with glass fiber and epoxy resin serving as insulating material so as to enhance the strength and support of the package substrate 200 .
- the core circuit board 210 has at least one conductive through hole 216 .
- the method of forming the conductive through hole 216 includes, for example, performing a mechanical drilling to form a through hole and then performing an electrochemical plating to form a layer of conductive material on the inner sidewall of the through hole. As a result, the upper and lower copper foils are connected through the conductive through hole 216 . After an etching operation is performed to pattern the copper foils, a wiring layer for transmitting signals is formed.
- the embedded capacitor 230 of the present invention is disposed in the dielectric layer 220 .
- the dielectric layer 220 may include a first dielectric layer 222 and a second dielectric layer 224 that covers a first wiring layer 212 and a second wiring layer 214 of the core circuit board 210 respectively.
- the conductive through hole 216 has already formed in the core circuit board 210 earlier on, there is no need to perform the process in a subsequent process. Therefore, the location of the conductive through hole 216 will not affect the space for disposing the embedded capacitor.
- the embedded capacitor 230 can be disposed in the first dielectric layer 222 underneath the conductive through hole 216 . Since the disposition of embedded capacitor 230 is unaffected by the conductive through hole 216 , the space and degree of freedom of disposing the embedded capacitor 230 are enhanced.
- the embedded capacitors 230 can be discrete capacitors.
- the capacitors are pre-soldered to a metal layer 240 (for example, a copper foil) and then the dielectric layer 220 and the metal layer 240 are compressed to the core circuit board 210 so that the embedded capacitor 230 is embedded in the dielectric layer 220 .
- epoxy-ceramic composite with high dielectric constant can be used as the embedded capacitor 230 to increase the capacitance.
- the metal layer 240 may include a first metal layer 242 and a second metal layer 244 .
- the first metal layer 242 covers the first dielectric layer 222 , and the first metal layer 242 can be connected to the first wiring layer 212 through a conductive via 226 in the first dielectric layer 222 .
- the second metal layer 244 covers the second dielectric layer 224 , and the second metal layer 244 can be connected to the second wiring layer 214 through a conductive via 228 in the second dielectric layer 224 .
- the conventional discrete capacitor has a relatively low capacitance.
- epoxy resin-ceramic composite capacitor or other ceramic/polymer composite capacitor with high dielectric constant is used so that the capacitance is increased and the dielectric loss is reduced. Hence, the performance of the package substrate 200 is enhanced.
- a build-up method can be used to sequentially fabricate multiple layers of interconnect structures 250 after the process for assembling the embedded capacitor is completed so that the original four circuit layer substrate is increased to six, eight, ten or twelve circuit layer substrate.
- a solder mask layer 260 covers a surface wiring layer 256 in the outermost layer of the package substrate 200 .
- the solder mask layer 260 has at least one opening 262 that exposes a contact of the surface wiring layer 256 .
- a top contact 258 a is used for electrically connecting to at least one chip or passive element (not shown), and a bottom contact 258 b is used for electrically connecting to a printed circuit board (not shown).
- the package substrate 200 serves as a signal transmission medium between the top and bottom elements.
- FIG. 3 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a second embodiment of the present invention.
- the package substrate 300 mainly includes a core board 310 , at least one embedded capacitor 330 , a first passivation layer 338 and a metal layer 340 .
- the core board 310 is a substrate fabricated using glass fibers and epoxy resin as its insulating material so as to enhance the strength and support of the package substrate 300 .
- the embedded capacitor 330 is embedded in the core board 310 and electrically connected to the metal layer 340 .
- the embedded capacitor 330 can be an epoxy resin-ceramic composite capacitor or other ceramic/polymer composite capacitor with high dielectric constant formed on the metal layer 340 after performing a high-temperature sintering process. Afterwards, electrode material covers the dielectric material 332 to form an electrode 334 connected to the metal layer 340 .
- the first passivation layer 338 is formed to cover the embedded capacitors 330 before compressing the substrate.
- the first passivation layer 338 is fabricated from polymer material such as epoxy resin or polyimide.
- the first passivation layer 338 not only has higher pressure resistant strength, but also has the characteristics of preventing the reactants of etching process, plating process and surface treatment process performed prior to the compression process from affecting the embedded capacitors 330 and their electrodes.
- the interior of an opening 342 on another side of the metal layer 340 can be selectively filled with a second passivation layer 336 to cover a surface of the embedded capacitor 330 .
- the material and function of the second passivation layer 336 are identical to the first passivation layer 338 and similarly prevent the embedded capacitors 330 from possible damage.
- FIG. 4 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a third embodiment of the present invention.
- the package substrate 400 mainly includes a first core circuit board 410 , a dielectric layer 420 , at least one embedded capacitor 430 and a second core circuit board 440 .
- the first and second core circuit boards 410 and 440 are, for example, copper foil substrates using glass fiber or epoxy resin as the insulating material so as to enhance the strength and support of the package substrate 400 .
- the dielectric layer 420 can be cured or semi-cured glass fiber epoxy resin laminated between the first and the second core circuit board 410 and 440 .
- the two opposing surfaces of the first core circuit board 410 have a metal layer 412 and at least one first conductive through hole 414 of the first core circuit board 410 is connected to the metal layer 412 .
- the embedded capacitor 430 is embedded in the first core circuit board 410 and connected to the metal layer 412 .
- the two opposing surfaces of the second core circuit board 440 have a wiring layer 442 and at least one second conductive through hole 444 of the second core circuit board 440 is connected to the wiring layer 442 .
- the embedded capacitors 430 in the present embodiment can be epoxy resin-ceramic composite capacitors or other ceramic/polymer composite capacitors with high dielectric constant so as to enhance the performance of the package substrate 400 .
- the first passivation layer 338 in FIG. 3 can be used to cover the embedded capacitors 430 in FIG. 4 .
- the second passivation layer 336 can be used to fill the opening 416 on the other side of the metal layer 412 to protect the embedded capacitors 430 and their electrodes.
- a conductive through hole 450 connecting the metal layer 412 and the wiring layer 442 can be formed in the package substrate 400 of the present invention by mechanically drilling to form a through hole and performing an electrochemical plating process to form a conductive layer on the inner sidewall of the through hole.
- the conductive through hole 450 can be filled with insulating or conductive filling material 452 according to the thickness of the package substrate 400 whose details are omitted.
- a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures (not shown) according to the circuit requirements after the process for forming the embedded capacitors 430 is completed.
- a solder mask layer covers the outermost surface wiring layer like the one in FIG. 1 .
- the solder mask layer has at least one opening exposing a contact on the surface wiring layer so that the package substrate 400 serves as a signal transmission medium between the top and bottom elements.
- FIG. 5 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a fourth embodiment of the present invention.
- the package substrate 500 mainly includes a core circuit board 510 , at least one dielectric layer 520 , at least one embedded capacitor 530 and at least one wiring layer 540 .
- the core circuit board 510 is, for example, a copper foil substrate fabricated using glass fibers and epoxy resin so as to enhance the strength and support of the package substrate 500 .
- the dielectric layer 520 can be cured or semi-cured epoxy resin or polyimide covering the core circuit board 510 using a build-up method.
- the two opposing surfaces of the core circuit board 510 have a metal layer 512 and at least one conductive through hole 514 of the core circuit layer 510 connected to the metal layers 512 .
- the embedded capacitors 530 are embedded in the core circuit board 510 and connected to the metal layers 512 .
- the dielectric layer 520 can be a single layer or multiple layers and the wiring layer 540 can be a single layer or multiple layers.
- the dielectric layer 520 has a plurality of laser-drilled and conductive material filled via holes 522 for electrically connecting neighboring upper and lower wiring layers 540 .
- the wiring layer 540 can be connected to one of the metal layers 512 through the via hole 524 .
- the metal layers 512 are connected to the wiring layer 540 through a through hole 550 passing through the core circuit board 510 , the dielectric layer 520 and the wiring layer 540 of the package substrate 500 .
- the embedded capacitors 530 in the present embodiment can be epoxy resin-ceramic composite capacitors or other ceramic/polymer composite capacitors with high dielectric constant so as to enhance the performance of the package substrate 400 .
- the first passivation layer 338 in FIG. 3 can be used to cover the embedded capacitors 530 in FIG. 5 (not shown)
- the second passivation layer 336 can be used to fill the opening 516 on the other side of the metal layer 512 to protect the embedded capacitors 530 and their electrodes.
- a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures (not shown) according to the circuit requirements after the process for forming the embedded capacitors 530 is completed.
- a solder mask layer covers the outermost surface wiring layer like the one in FIG. 1 .
- the solder mask layer has at least one opening exposing a contact on the surface wiring layer so that the package substrate 500 serves as a signal transmission medium between the top and bottom elements.
- FIG. 6 is a schematic diagram of a portion of a package substrate using the substrate having embedded capacitor in FIG. 3 as the core layer.
- a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures 602 on the package substrate 600 according to the circuit requirements.
- the interconnect structure 602 includes at least one dielectric layer 610 and at least one wiring layer 620 .
- the dielectric layer 610 includes a plurality of first dielectric layers 612 and a second dielectric layer 614 .
- the first dielectric layer 612 covers the first metal layer 340
- the second dielectric layer 614 covers the core board 310 or second metal layer 344 .
- the wiring layer 620 includes a plurality of first wiring layers 622 , 624 and a second wiring layer 626 .
- the first wiring layers 622 , 624 are connected to each other through a via hole 616 in the first dielectric layer 612 .
- the second wiring layer 626 is connected to the second metal layer 344 through a via hole 618 in the second dielectric layer 614 .
- at least one conductive through hole 628 can be used to connect between the first wiring layers 622 , 624 and the second wiring layer 626 .
- the embedded capacitor in the present invention can be disposed in a suitable location without having to avert the conductive through holes due to an improvement of the substrate structure. Therefore, the space and degree of freedom for disposing the embedded capacitors are enhanced.
- capacitors fabricated using high dielectric constant and low dielectric loss material such as polymer-ceramic composite instead of the conventional discrete capacitors can be used so as to enhance the performance of the package substrate.
- the embedded capacitors of the present invention are covered with at least one passivation layer to prevent the embedded capacitors from receiving possible damage in the process of compressing the substrate. Hence, overall reliability of the package substrate is improved.
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Abstract
A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. The embedded capacitor is embedded in the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. The dielectric layer is laminated between the first and the second core circuit boards.
Description
- This application claims the priority benefit of Taiwan application serial no. 95141129, filed Nov. 7, 2006. All disclosure of the Taiwan application is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a package substrate, and more particularly to a package substrate having embedded capacitor.
- 2. Description of Related Art
- Embedded capacitor can be integrated into a package substrate in the same fabrication process to enhance the efficiency of the active components inside an electronic package, improve electrical performance and lower assembling cost. Therefore, it has become the mainstream method for fabricating electronic carrier. At present, the development of embedded capacitor is mainly aiming toward small size ceramic capacitors. In general, ceramic capacitors can be classified into single layer ceramic capacitors (SLCC) and multi-layer ceramic capacitors (MLCC), also known as discrete capacitors. However, because the capacitance of the conventional discrete capacitor is low and has a low dielectric constant, they could hardly enhance the performance of a conventional circuit substrate.
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FIG. 1 is a schematic diagram of a conventional package substrate having embedded capacitor. The internal structure of thepackage substrate 100 and its fabrication process are roughly as follows. First, acore board 110, a plurality ofdielectric materials 121˜124 and twocopper foils discrete capacitors 130 are provided. Then, thedielectric materials 121˜124 and the twocopper foils discrete capacitors 130 are aligned and compressed to thecore board 110. Thus, the twocopper foils discrete capacitors 130 are located between the upperdielectric materials dielectric materials board 160. Thereafter, a mechanical drilling process is performed to form a plurality of conductive throughholes 150 inside the core laminatedboard 160 that averts thediscrete capacitors 130 and connects the upper andlower copper foils surface circuit 162 of the core laminatedboard 160 can connect with thediscrete capacitors 130 through thevia hole 164. - Because the
discrete capacitors 130 have to avert the conductive throughhole 150, the usable area and location for disposing thecapacitors 130 are constrained by the number and locations of the conductive throughholes 150 and the degree of freedom of disposing thecapacitors 130 is lowered. In the meantime, thediscrete capacitors 130 are easily damaged or broken in the process of compressing the substrate. As a result, the reliability of thecapacitors 130 is lowered. - Accordingly, the present invention directs to a package substrate having embedded capacitor for enhancing the space and degree of freedom of disposing the embedded capacitor.
- The present invention also directs to a package substrate having embedded capacitor such that the performance of the package substrate is enhanced by using a dielectric material with high dielectric constant and low dielectric loss.
- The present invention directs to a package substrate having embedded capacitor such that the embedded capacitor is protected from damage by covering it with a passivation layer.
- The present invention provides a package substrate having embedded capacitor. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor and at least one metal layer. At least one wiring layer is disposed on a surface of the core circuit board and a conductive through hole of the core circuit board is connected to the wiring layer. In addition, the dielectric layer covers the wiring layer and has at least one via hole. Furthermore, the embedded capacitor is connected to the metal layer and is embedded within the dielectric layer. The metal layer covers the dielectric layer and connects to the wiring layer through the via hole.
- The present invention also provides a package substrate having embedded capacitor. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. In addition, the embedded capacitor is embedded within the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. Furthermore, the dielectric layer is laminated between the first core circuit board and the second core circuit board.
- The present invention also provides a package substrate having embedded capacitor. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. At least one metal layer is disposed on a surface of the core circuit board and at least one conductive through hole of the core circuit board is connected to the metal layer. In addition, the embedded capacitor is embedded within the core circuit board and connected to the metal layer. The dielectric layer covers the wiring layer and has an embedded hole. Furthermore, the wiring layer covers the dielectric layer and is electrically connected to the embedded hole.
- According to an embodiment of the present invention, the package substrate further includes a first passivation layer covering the embedded capacitor. In addition, the metal layer has an opening and the opening exposes a surface of the embedded capacitor. The package substrate further includes a second passivation layer covering the surface of the embedded capacitor. The first passivation layer is fabricated using epoxy resin or polyimide, and the second passivation layer can be fabricated using epoxy resin or polyimide too.
- According to an embodiment of the present invention, the package substrate further includes at least one surface wiring layer disposed on a surface of the package substrate. The surface wiring layer has at least one contact electrically connected to the metal layer or the wiring layer. In addition, the package substrate further includes a solder mask layer covering the surface wiring layer. The solder mask layer has at least one opening that exposes the contact.
- The present invention also provides a package substrate having embedded capacitor. The package substrate includes a core board, an embedded capacitor, a first passivation layer and a metal layer. The embedded capacitor is embedded within the core board and the first passivation layer covers the embedded capacitor. In addition, the metal layer covers the core board and is connected to the embedded capacitor.
- According to an embodiment of the present invention, the metal layer has an opening and the opening exposes a surface of the embedded capacitor. The package substrate further includes a second passivation layer covering the surface of the embedded capacitor. The first passivation layer is fabricated using epoxy resin or polyimide, and the second passivation layer can be fabricated using epoxy resin or polyimide too.
- Due to the improvement in the substrate structure, the embedded capacitor in the present invention can be disposed in a suitable location without having to avert the conductive through hole. Therefore, the space and degree of freedom for disposing the embedded capacitors is enhanced. In addition, capacitors fabricated using high dielectric constant and low dielectric loss material such as polymer-ceramic composite can be used instead of the conventional discrete capacitors so as to enhance the performance of the package substrate. Furthermore, the embedded capacitors of the present invention is covered with at least one passivation layer to prevent the embedded capacitors from receiving possible damage in the process of compressing the substrate. Hence, overall reliability of the package substrate is improved.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 is a schematic diagram of a conventional package substrate having embedded capacitor. -
FIG. 2 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a first embodiment of the present invention. -
FIG. 3 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a second embodiment of the present invention. -
FIG. 4 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a third embodiment of the present invention. -
FIG. 5 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a fourth embodiment of the present invention. -
FIG. 6 is a schematic diagram of a portion of a package substrate using the substrate having embedded capacitor inFIG. 3 as the core layer. - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 2 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a first embodiment of the present invention. Thepackage substrate 200 mainly includes acore circuit board 210, adielectric layer 220, at least one embeddedcapacitor 230 and ametal layer 240. Thecore circuit board 210 is, for example, a copper foil substrate with glass fiber and epoxy resin serving as insulating material so as to enhance the strength and support of thepackage substrate 200. In addition, thecore circuit board 210 has at least one conductive throughhole 216. The method of forming the conductive throughhole 216 includes, for example, performing a mechanical drilling to form a through hole and then performing an electrochemical plating to form a layer of conductive material on the inner sidewall of the through hole. As a result, the upper and lower copper foils are connected through the conductive throughhole 216. After an etching operation is performed to pattern the copper foils, a wiring layer for transmitting signals is formed. - As shown in
FIG. 2 , the embeddedcapacitor 230 of the present invention is disposed in thedielectric layer 220. Thedielectric layer 220 may include a firstdielectric layer 222 and asecond dielectric layer 224 that covers afirst wiring layer 212 and asecond wiring layer 214 of thecore circuit board 210 respectively. It should be noted that because the conductive throughhole 216 has already formed in thecore circuit board 210 earlier on, there is no need to perform the process in a subsequent process. Therefore, the location of the conductive throughhole 216 will not affect the space for disposing the embedded capacitor. As shown inFIG. 2 , the embeddedcapacitor 230 can be disposed in thefirst dielectric layer 222 underneath the conductive throughhole 216. Since the disposition of embeddedcapacitor 230 is unaffected by the conductive throughhole 216, the space and degree of freedom of disposing the embeddedcapacitor 230 are enhanced. - In the present embodiment, the embedded
capacitors 230 can be discrete capacitors. The capacitors are pre-soldered to a metal layer 240 (for example, a copper foil) and then thedielectric layer 220 and themetal layer 240 are compressed to thecore circuit board 210 so that the embeddedcapacitor 230 is embedded in thedielectric layer 220. Obviously, epoxy-ceramic composite with high dielectric constant can be used as the embeddedcapacitor 230 to increase the capacitance. Themetal layer 240 may include afirst metal layer 242 and asecond metal layer 244. Thefirst metal layer 242 covers thefirst dielectric layer 222, and thefirst metal layer 242 can be connected to thefirst wiring layer 212 through a conductive via 226 in thefirst dielectric layer 222. In addition, thesecond metal layer 244 covers thesecond dielectric layer 224, and thesecond metal layer 244 can be connected to thesecond wiring layer 214 through a conductive via 228 in thesecond dielectric layer 224. - As mentioned above, the conventional discrete capacitor has a relatively low capacitance. In the present embodiment, epoxy resin-ceramic composite capacitor or other ceramic/polymer composite capacitor with high dielectric constant is used so that the capacitance is increased and the dielectric loss is reduced. Hence, the performance of the
package substrate 200 is enhanced. - In the present embodiment, a build-up method can be used to sequentially fabricate multiple layers of
interconnect structures 250 after the process for assembling the embedded capacitor is completed so that the original four circuit layer substrate is increased to six, eight, ten or twelve circuit layer substrate. By drilling a plurality of blind holes with laser and then filling the blind holes with conductive material, two neighboring wiring layers 252 are connected. Finally, asolder mask layer 260 covers asurface wiring layer 256 in the outermost layer of thepackage substrate 200. Thesolder mask layer 260 has at least oneopening 262 that exposes a contact of thesurface wiring layer 256. In the present embodiment, atop contact 258a is used for electrically connecting to at least one chip or passive element (not shown), and abottom contact 258b is used for electrically connecting to a printed circuit board (not shown). Hence, thepackage substrate 200 serves as a signal transmission medium between the top and bottom elements. -
FIG. 3 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a second embodiment of the present invention. Thepackage substrate 300 mainly includes acore board 310, at least one embeddedcapacitor 330, afirst passivation layer 338 and ametal layer 340. Thecore board 310 is a substrate fabricated using glass fibers and epoxy resin as its insulating material so as to enhance the strength and support of thepackage substrate 300. In addition, the embeddedcapacitor 330 is embedded in thecore board 310 and electrically connected to themetal layer 340. In the present embodiment, the embeddedcapacitor 330 can be an epoxy resin-ceramic composite capacitor or other ceramic/polymer composite capacitor with high dielectric constant formed on themetal layer 340 after performing a high-temperature sintering process. Afterwards, electrode material covers thedielectric material 332 to form anelectrode 334 connected to themetal layer 340. - To prevent the compressing process from breaking or damaging the embedded
capacitors 330, thefirst passivation layer 338 is formed to cover the embeddedcapacitors 330 before compressing the substrate. Thefirst passivation layer 338 is fabricated from polymer material such as epoxy resin or polyimide. Thefirst passivation layer 338 not only has higher pressure resistant strength, but also has the characteristics of preventing the reactants of etching process, plating process and surface treatment process performed prior to the compression process from affecting the embeddedcapacitors 330 and their electrodes. In addition, the interior of anopening 342 on another side of themetal layer 340 can be selectively filled with asecond passivation layer 336 to cover a surface of the embeddedcapacitor 330. The material and function of thesecond passivation layer 336 are identical to thefirst passivation layer 338 and similarly prevent the embeddedcapacitors 330 from possible damage. -
FIG. 4 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a third embodiment of the present invention. Thepackage substrate 400 mainly includes a firstcore circuit board 410, adielectric layer 420, at least one embeddedcapacitor 430 and a secondcore circuit board 440. The first and secondcore circuit boards package substrate 400. In addition, thedielectric layer 420 can be cured or semi-cured glass fiber epoxy resin laminated between the first and the secondcore circuit board core circuit board 410 have a metal layer 412 and at least one first conductive throughhole 414 of the firstcore circuit board 410 is connected to the metal layer 412. The embeddedcapacitor 430 is embedded in the firstcore circuit board 410 and connected to the metal layer 412. Similarly, the two opposing surfaces of the secondcore circuit board 440 have awiring layer 442 and at least one second conductive throughhole 444 of the secondcore circuit board 440 is connected to thewiring layer 442. - As described in above, the embedded
capacitors 430 in the present embodiment can be epoxy resin-ceramic composite capacitors or other ceramic/polymer composite capacitors with high dielectric constant so as to enhance the performance of thepackage substrate 400. Furthermore, before compressing the substrate, thefirst passivation layer 338 inFIG. 3 can be used to cover the embeddedcapacitors 430 inFIG. 4 . Similarly, thesecond passivation layer 336 can be used to fill theopening 416 on the other side of the metal layer 412 to protect the embeddedcapacitors 430 and their electrodes. - Similarly, as shown in
FIG. 4 , a conductive throughhole 450 connecting the metal layer 412 and thewiring layer 442 can be formed in thepackage substrate 400 of the present invention by mechanically drilling to form a through hole and performing an electrochemical plating process to form a conductive layer on the inner sidewall of the through hole. Obviously, the conductive throughhole 450 can be filled with insulating or conductive filling material 452 according to the thickness of thepackage substrate 400 whose details are omitted. In addition, a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures (not shown) according to the circuit requirements after the process for forming the embeddedcapacitors 430 is completed. Furthermore, a solder mask layer covers the outermost surface wiring layer like the one inFIG. 1 . The solder mask layer has at least one opening exposing a contact on the surface wiring layer so that thepackage substrate 400 serves as a signal transmission medium between the top and bottom elements. -
FIG. 5 is a schematic diagram of a portion of a package substrate having embedded capacitor according to a fourth embodiment of the present invention. Thepackage substrate 500 mainly includes acore circuit board 510, at least onedielectric layer 520, at least one embeddedcapacitor 530 and at least onewiring layer 540. Thecore circuit board 510 is, for example, a copper foil substrate fabricated using glass fibers and epoxy resin so as to enhance the strength and support of thepackage substrate 500. In addition, thedielectric layer 520 can be cured or semi-cured epoxy resin or polyimide covering thecore circuit board 510 using a build-up method. In the present embodiment, the two opposing surfaces of thecore circuit board 510 have ametal layer 512 and at least one conductive throughhole 514 of thecore circuit layer 510 connected to the metal layers 512. The embeddedcapacitors 530 are embedded in thecore circuit board 510 and connected to the metal layers 512. - In the present embodiment, the
dielectric layer 520 can be a single layer or multiple layers and thewiring layer 540 can be a single layer or multiple layers. Using multiple layers as an example, thedielectric layer 520 has a plurality of laser-drilled and conductive material filled viaholes 522 for electrically connecting neighboring upper and lower wiring layers 540. Obviously, thewiring layer 540 can be connected to one of the metal layers 512 through the viahole 524. Alternatively, the metal layers 512 are connected to thewiring layer 540 through a throughhole 550 passing through thecore circuit board 510, thedielectric layer 520 and thewiring layer 540 of thepackage substrate 500. - As described in above, the embedded
capacitors 530 in the present embodiment can be epoxy resin-ceramic composite capacitors or other ceramic/polymer composite capacitors with high dielectric constant so as to enhance the performance of thepackage substrate 400. Furthermore, before compressing the substrate, thefirst passivation layer 338 inFIG. 3 can be used to cover the embeddedcapacitors 530 inFIG. 5 (not shown) Similarly, thesecond passivation layer 336 can be used to fill the opening 516 on the other side of themetal layer 512 to protect the embeddedcapacitors 530 and their electrodes. - Similarly, a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures (not shown) according to the circuit requirements after the process for forming the embedded
capacitors 530 is completed. Furthermore, a solder mask layer covers the outermost surface wiring layer like the one inFIG. 1 . The solder mask layer has at least one opening exposing a contact on the surface wiring layer so that thepackage substrate 500 serves as a signal transmission medium between the top and bottom elements. -
FIG. 6 is a schematic diagram of a portion of a package substrate using the substrate having embedded capacitor inFIG. 3 as the core layer. After the process for assembling the embeddedcapacitors 330 is completed, a build-up method or other process can be used to sequentially fabricate multiple layers of interconnect structures 602 on thepackage substrate 600 according to the circuit requirements. The interconnect structure 602 includes at least one dielectric layer 610 and at least onewiring layer 620. Using multiple layers as an example, the dielectric layer 610 includes a plurality of firstdielectric layers 612 and asecond dielectric layer 614. Thefirst dielectric layer 612 covers thefirst metal layer 340, and thesecond dielectric layer 614 covers thecore board 310 orsecond metal layer 344. In addition, thewiring layer 620 includes a plurality of first wiring layers 622, 624 and asecond wiring layer 626. The first wiring layers 622, 624 are connected to each other through a viahole 616 in thefirst dielectric layer 612. Thesecond wiring layer 626 is connected to thesecond metal layer 344 through a viahole 618 in thesecond dielectric layer 614. Furthermore, at least one conductive throughhole 628 can be used to connect between the first wiring layers 622, 624 and thesecond wiring layer 626. - In summary, the embedded capacitor in the present invention can be disposed in a suitable location without having to avert the conductive through holes due to an improvement of the substrate structure. Therefore, the space and degree of freedom for disposing the embedded capacitors are enhanced. In addition, capacitors fabricated using high dielectric constant and low dielectric loss material such as polymer-ceramic composite instead of the conventional discrete capacitors can be used so as to enhance the performance of the package substrate. Furthermore, the embedded capacitors of the present invention are covered with at least one passivation layer to prevent the embedded capacitors from receiving possible damage in the process of compressing the substrate. Hence, overall reliability of the package substrate is improved.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (31)
1. A package substrate having embedded capacitor, comprising:
a core circuit board having at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer;
at least one dielectric layer covering the wiring layer, and the dielectric layer has at least one conductive through hole;
at least one embedded capacitor, embedded in the dielectric layer; and
at least one metal layer covering the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.
2. The package substrate of claim 1 , wherein the at least one embedded capacitor is disposed in a location in the dielectric layer corresponding to the conductive through hole.
3. The package substrate of claim 1 , wherein the at least one wiring layer comprises a first wiring layer and a second wiring layer disposed on two opposing surface of the core circuit board.
4. The package substrate of claim 3 , wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer covers the first wiring layer and the second dielectric layer covers the second wiring layer.
5. The package substrate of claim 4 , wherein the at least one metal layer comprises a first metal layer and a second metal layer, and the first metal layer covers the first dielectric layer and the second metal layer covers the second dielectric layer.
6. The package substrate of claim 1 , further comprising a first passivation layer that covers the embedded capacitor.
7. The package substrate of claim 1 , wherein the metal layer has an opening that exposes a surface of the embedded capacitor and the package substrate further comprise a second passivation layer that covers the surface.
8. The package substrate of claim 6 , wherein the first passivation layer is made of epoxy resin or polyimide.
9. The package substrate of claim 1 , further comprising at least one surface wiring layer disposed on a surface of the package substrate, and the surface wiring layer has at least one contact electrically connected to the metal layer.
10. The package substrate of claim 9 , further comprising a solder mask layer that covers the surface wiring layer and the solder mask layer has at least one opening that exposes the contact.
11. A package substrate having embedded capacitors, comprising:
a first core circuit board having at least one metal layer, the first core circuit board has at least one first conductive through hole connected to the metal layer;
at least one embedded capacitor, embedded in the first core circuit board and connected to the metal layer;
a second core circuit board having at least one wiring layer, the second core circuit board has at least one second conductive through hole connected to the wiring layer; and
a dielectric layer, laminated between the first core circuit board and the second core circuit board.
12. The package substrate of claim 11 , wherein the at least one metal layer comprises a first metal layer and a second metal layer disposed on two opposing surfaces of the first core circuit board.
13. The package substrate of claim 11 , wherein the at least one wiring layer comprises a first wiring layer and a second wiring layer disposed on two opposing surfaces of the second core circuit board.
14. The package substrate of claim 11 , further comprising a passivation layer that covers the embedded capacitor.
15. The package substrate of claim 11 , wherein the metal layer has an opening that exposes a surface of the embedded capacitor and the package substrate further comprise a second passivation layer that covers the surface.
16. The package substrate of claim 11 , further comprising at least one conductive through hole that passes through the first core circuit board, the dielectric layer and the second core circuit board and connects the metal layer and the wiring layer.
17. The package substrate of claim 11 , further comprising at least one surface wiring layer disposed on a surface of the package substrate, the surface wiring layer has at least one contact electrically connected to the metal layer or the wiring layer.
18. The package substrate of claim 17 , further comprising a solder mask layer that covers the surface wiring layer and the solder mask layer has at least an opening that exposes the contact.
19. A package substrate having embedded capacitors, comprising:
a core circuit board having at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer;
at least one embedded capacitor, embedded in the core circuit board and connected to the metal layer;
at least one dielectric layer covering the core circuit board, and the dielectric layer has an embedded hole; and
at least one wiring layer covering the dielectric layer and connected to the embedded hole.
20. The package substrate of claim 19 , wherein the at least one metal layer comprises a first metal layer and a second metal layer disposed on two opposing surfaces of the core circuit board.
21. The package substrate of claim 19 , further comprising at least one through hole that passes through the core circuit board, the dielectric layer and the wiring layer and connects the metal layer and the wiring layer.
22. The package substrate of claim 19 , further comprising a first passivation layer that covers the embedded capacitor.
23. The package substrate of claim 19 , wherein the metal layer has an opening that exposes a surface of the embedded capacitor, and the package substrate further comprises a second passivation layer that covers the surface.
24. The package substrate of claim 19 , further comprising at least one surface wiring layer disposed on a surface of the package substrate, the surface wiring layer has at least one contact electrically connected to the metal layer or the wiring layer.
25. The package substrate of claim 24 , further comprising a solder mask layer that covers the surface wiring layer, and the solder mask layer has at least one opening that exposes the contact.
26. A package substrate having embedded capacitors, comprising:
a core board;
an embedded capacitor, embedded in the core board;
a first passivation layer covering the embedded capacitor; and
a metal layer covering the core board and connected to the embedded capacitor.
27. The package substrate of claim 26 , further comprising:
at least one dielectric layer covering the metal layer, and the dielectric layer has at least one conductive through hole; and
at least one wiring layer covering the dielectric layer, and connected to the conductive through hole.
28. The package substrate of claim 27 , further comprising at least one conductive through hole that passes through the core board, the metal layer, the dielectric layer, the wiring layer and connects the metal layer and the wiring layer.
29. The package substrate of claim 26 , wherein the first passivation layer is made of epoxy resin or polyimide.
30. The package substrate of claim 26 , wherein the metal layer has an opening that exposes a surface of the embedded capacitor, and the package substrate further comprises a second passivation layer that covers the surface.
31. The package substrate of claim 30 , wherein the second passivation layer is made of epoxy resin or polyimide.
Priority Applications (3)
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US12/851,807 US20100294553A1 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
US12/851,803 US20100319973A1 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
Applications Claiming Priority (2)
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TW95141129 | 2006-11-07 | ||
TW095141129A TWI333684B (en) | 2006-11-07 | 2006-11-07 | Package substrate having embedded capacitor |
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US12/851,795 Division US8289725B2 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
US12/851,803 Division US20100319973A1 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
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US12/851,795 Expired - Fee Related US8289725B2 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
US12/851,803 Abandoned US20100319973A1 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
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US12/851,803 Abandoned US20100319973A1 (en) | 2006-11-07 | 2010-08-06 | Package substrate having embedded capacitor |
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Also Published As
Publication number | Publication date |
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TWI333684B (en) | 2010-11-21 |
US20100319970A1 (en) | 2010-12-23 |
US8289725B2 (en) | 2012-10-16 |
TW200822302A (en) | 2008-05-16 |
US20100294553A1 (en) | 2010-11-25 |
US20100319973A1 (en) | 2010-12-23 |
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