JP2010153877A - 半導体チップ - Google Patents
半導体チップ Download PDFInfo
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- JP2010153877A JP2010153877A JP2010003235A JP2010003235A JP2010153877A JP 2010153877 A JP2010153877 A JP 2010153877A JP 2010003235 A JP2010003235 A JP 2010003235A JP 2010003235 A JP2010003235 A JP 2010003235A JP 2010153877 A JP2010153877 A JP 2010153877A
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Abstract
【解決手段】半導体チップ1には半導体基板主面の周辺部に複数の第1の電極パッド2、第1の電極パッド2より内側の領域に少なくとも1個の第2の電極パッド3が配設されている。第1の電極パッド2の配列間には第2の電極パッド3の数以上の間隙部が設けられている。これにより、特性試験時には間隙部を通じてプローブカードとのワイヤ接続を容易に行なうことができ、実装時には、主面に第1の電極パッド2と接続するための第1のボンディングパッド5を、反対面には第2の電極パッド3と接続するための第2のボンディングパッド8が配設された配線基板4を用いることにより、第2の電極パッド3とのワイヤ接続を通じて、回路ブロックに短い配線で電源を供給することができる。
【選択図】図1
Description
図1は本発明に係る半導体装置の構造を説明する図であり、図1(a)は上記半導体装置の模式断面図、図1(b)は半導体チップ上の電極パッドの配置を示す平面図、図1(c)は図1(a)において矢印方向から見た配線基板を示す平面図である。
次に、図5(a)、(b)(c)は本発明の他の実施例を説明する図である。図5(a)は上記半導体装置の模式断面図、図5(b)は半導体チップ上の電極パッドの配置を示す平面図、図5(c)は図5(a)において矢印方向から見た配線基板4を示す平面図であり、それぞれ図1(a)、(b)(c)と対応し同一のものには同一番号を付してある。
上述した第2の電極パッドあるいは第3の電極パッドが配設された半導体チップに対しては配線基板に実装する前に電気的導通の確認及び機能確認等のため特性試験を行わねばならない。この特性試験に際しては、半導体チップに配設されている電極パッドへのプローブの接触が良好で且つ安価なカンチレバー型プローブカードが用いられる。図6はカンチレバー型プローブカードを示す断面図である。同図に見られるように,プローブカード20は半導体ウェーハ上に形成されている切り離し前の半導体チップ21の各電極パッド22に接触させるプローブ23とそのプローブ23を半導体テスターに接続するためのインターフェイス回路が形成されているカード基板24から成っており、図8に示した従来型の半導体チップ30の周辺の電極パッド31と同一の配置となるように略放射状に半導体チップ30を取り囲むよう列状にプローブが配設された構造を有している。したがって、このプローブカード20を従来型の半導体チップ30に対向して配置したとき、半導体チップ30上の全ての電極パッド31に同時にプローブを当接させることが可能となる。
2 第1の電極パッド
3 第2の電極パッド
4、32 配線基板
5 第1のボンディングパッド
6、34 バンプ
7 開口部
8 第2のボンディングパッド
9、35 ボールランド
10、15 ボンディングワイヤ
11、36 半田ボール
12、13、16、38 熱硬化性樹脂
14 第3の電極パッド
20 プローブカード
22、31 電極パッド
23 プローブ
24 カード基板
25 カード基板開口部
26 プローブ固定台座
33 ボンディングパッド
37 間隙部
Claims (1)
- 半導体基板主面の周辺部に第1の電極パッドが複数配設され、該第1の電極パッドより内側の領域に少なくとも1個の第2の電極パッドが配設された半導体チップにおいて、
該第1の電極パッドは該半導体基板主面の周辺部に所定ピッチでパッド列をなして配設され、該パッド列には上記所定ピッチ以上の距離を離間させた間隙部が設けられ、
該間隙部は該第2の電極パッドの数以上設けられていることを特徴とする半導体チップ。
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JP2005059387A Division JP4767556B2 (ja) | 2005-03-03 | 2005-03-03 | 半導体装置 |
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Citations (1)
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JPH02146441U (ja) * | 1989-05-17 | 1990-12-12 |
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JPH02146441U (ja) * | 1989-05-17 | 1990-12-12 |
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