JP2010141172A - Chip-like solid electrolytic capacitor and manufacturing method therefor - Google Patents

Abstract

A chip-shaped solid electrolytic capacitor capable of simultaneously satisfying the contradicting demands of small size, large capacity, low ESR and low ESL.
A chip-shaped solid electrolytic capacitor (10a) according to the present invention is a chip-shaped solid electrolytic capacitor formed by resin-sealing a plurality of capacitor elements (1) having two polar portions of a cathode and an anode. , Two first electrodes (5) arranged at a predetermined interval, and one second electrode (6) arranged between the first electrodes (5). The two capacitor elements (1a, 1b) constituting the pair are arranged such that the anodes are staggered around the cathode, the anodes are respectively connected to separate first electrodes (5), and the cathode is the second The cathode is connected to the electrode (6), and the cathode is further connected to the first electrode (5) on the side to which the anode of the capacitor element is not connected via an insulating masking portion (7). To do.
[Selection] Figure 2

Description

  The present invention relates to a chip-shaped solid electrolytic capacitor and a method for manufacturing the same.

  Various electronic devices are becoming smaller / thinner, more efficient, and faster every year. As a result, semiconductor devices (chip components) mounted on electronic devices are made smaller / thinner, with low ESR (Equivalent Series Resistance) / low ESL (Equivalent Series Inductance) for high frequency compatibility. : Equivalent series inductance), there is an increasing demand for contradictory performance.

  By the way, although ceramic capacitors are frequently used in various electronic devices, chip-shaped solid electrolytic capacitors using a valve action metal such as tantalum are used in circuits that require a large capacity.

  Chip-type solid electrolytic capacitors mainly have a lead frame as a skeleton. As a structure for reducing the ESR of this type of chip-shaped solid electrolytic capacitor, a multi-element structure in which a plurality of capacitor elements are sealed in one package is known (for example, see Patent Document 1).

In addition, a chip-shaped solid electrolytic capacitor that realizes low ESR with a small size and a large capacity has been proposed (see, for example, Patent Document 2).
JP 2005-93994 A JP 2002-110458 A

  However, the chip-shaped solid electrolytic capacitor described in Patent Document 1 adopting a multi-element structure has poor volume efficiency of the capacitor element because the lead frame is sealed, and it is difficult to realize a small and large capacity. It was. Further, this type of chip-shaped solid electrolytic capacitor has a drawback that ESL that affects impedance in a high frequency region is high.

  On the other hand, the chip-shaped solid electrolytic capacitor described in Patent Document 2 adopting the bottom electrode structure has a small size and a large capacity and low ESR characteristics. In addition, since the structure does not require a lead frame, low ESL can be achieved to some extent. However, the impedance is still high in the ultra-high frequency region from several tens of megahertz to gigahertz, and further reduction in ESL has been demanded.

  Therefore, an object of the present invention is to provide a chip-shaped solid electrolytic capacitor that can simultaneously satisfy the conflicting demands of small size, large capacity, low ESR, and low ESL.

In order to solve the above problems, a solid electrolytic capacitor according to the present invention is a chip-shaped solid electrolytic capacitor formed by resin-sealing a plurality of capacitor elements having two polar portions of a cathode and an anode,
Two first electrodes arranged at a predetermined interval and one second electrode arranged between the first electrodes, and any two of the plurality of capacitor elements are: The two capacitor elements constituting the capacitor element pair are arranged such that the anodes are staggered around the cathode, and the anodes are respectively connected to the separate first electrodes, The cathode is connected to the second electrode, and the cathode is further connected to the first electrode on the side where the anode of the capacitor element is not connected via an insulating masking portion. .

Further, the solid electrolytic capacitor according to the present invention is a chip-shaped solid electrolytic capacitor formed by resin-sealing a plurality of capacitor elements having two polar portions of a cathode and an anode,
Two first electrodes arranged at a predetermined interval and one second electrode arranged between the first electrodes, and any two of the plurality of capacitor elements are: The two capacitor elements constituting the capacitor element pair are arranged so that the same polarity portion faces each other, the opposite polarity portions are connected to the second electrode, and the polarity on the other side Each of the portions is connected to a separate first electrode.

According to this configuration of the present invention, since it has a multi-element structure that does not require a lead frame, low ESR can be realized while ensuring the conventional volume efficiency. Further, according to this configuration, the same polarity portions of the two capacitor elements constituting the capacitor element pair are faced to each other, or the anodes of the two capacitor elements are arranged so as to be staggered around the cathode. The charge / discharge current flowing in each element during charge / discharge is in the opposite direction.
Therefore, since the magnetic fields generated by the charge / discharge current cancel each other, the counter electromotive force generated under the influence of the magnetic field in the high frequency region is reduced, and a low ESL can be realized.

  In addition, this configuration has a symmetrical electrode arrangement in which the first electrode is arranged between two second electrodes arranged at a predetermined interval, so that there is a problem even when mounted in the reverse direction of 180 degrees. Will not occur.

Specifically, the capacitor element is formed by forming a capacitor anode body made of a valve metal around the anode lead, and sequentially forming a cathode layer and a cathode lead layer on the surface of the capacitor anode body. Preferably there is.
In this case, the anode lead may be connected to the second electrode and the cathode lead layer may be connected to the first electrode. Conversely, the anode lead may be connected to the first electrode, and A cathode lead layer may be connected to the second electrode.

In order to solve the above-described problem, a method for manufacturing a solid electrolytic capacitor according to the present invention includes two first electrodes arranged at a predetermined interval and one first electrode arranged between the first electrodes. A manufacturing method of a chip-shaped solid electrolytic capacitor including a second electrode and m (where m ≧ 2) capacitor elements having two polar portions of a cathode and an anode,
The first strip-shaped conductor to be the first electrode and the second strip-shaped conductor to be the second electrode are arranged at predetermined intervals so that the major axis direction is parallel, and n pieces prepared in advance Of the capacitor elements (where n ≧ m), any two capacitor elements are capacitor element pairs,
The two capacitor elements constituting the capacitor element pair are arranged so that the anodes are staggered around the cathode, and the anodes are connected to the separate first band conductors arranged on both sides of the second band conductor. And connecting the cathode to the second strip conductor, and further connecting the cathode to the first strip conductor on the side where the anode of the capacitor element is not connected via an insulating masking portion, or The opposite polar parts of the two capacitor elements constituting the capacitor element pair are connected to the second strip conductor, and the other polar portion is disposed on both sides of the second strip conductor. Each of the n capacitor elements was collectively sealed with an exterior resin after being connected to each of the strip-shaped conductors, and the obtained exterior resin sealing body was replaced with the m capacitors. Characterized by cutting at a position to include children.

According to this configuration, a large number (n) of capacitor elements are collectively sealed with resin, and then cut into pieces by cutting with a diamond cutter or the like. Capacitance and chip size can be arbitrarily and easily adjusted by changing the number of capacitor elements included in one chip.
Further, according to this configuration, it is not necessary to prepare a mold for resin molding for each product having a different capacitance or chip size, so that the manufacturing cost can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the chip-shaped solid electrolytic capacitor which can satisfy simultaneously the conflicting request | requirement of small size large capacity | capacitance and low ESR and low ESL can be provided.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment shown below is only an example, and the present invention is not limited to this.

[Example 1]
FIG. 1 shows a state of the solid electrolytic capacitor element according to Example 1 before sealing the exterior resin.
Capacitor element 1 is a porous body formed by pressing and sintering the tantalum powder while embedding an anode lead in tantalum powder, which is a valve action metal, and forming a dielectric oxide film layer on the surface of the porous body After the capacitor anode body was prepared, a conductive polymer layer as a cathode, and a carbon layer and a silver layer as a cathode lead layer were sequentially formed on the surface of the capacitor anode body.

  Later, the strip-shaped conductor 5a to be the anode electrode 5 and the strip-shaped conductor 6a to be the cathode electrode 6 were previously arranged at predetermined intervals so that the major axis directions of the respective strip-shaped conductors were parallel.

  Subsequently, an arbitrary two capacitor elements (for example, 1a and 1b) of the plurality of capacitor elements 1 thus manufactured constitute a capacitor element pair, and the capacitor elements 1a and 1b constituting the pair are arranged in the major axis direction of the strip conductor. Placed adjacent to each other. Further, the capacitor elements 1a and 1b are arranged so that the anode (or cathode) of the capacitor element 1a and the cathode (or anode) of the capacitor element 1b are adjacent to each other. Then, each anode lead 2 and the strip conductor 5 a were connected via the metal block 3, and the cathode lead layers of the capacitor elements 1 a and 1 b were connected to the strip conductor 6 a via the conductive adhesive 4. An insulating masking portion 7 (for example, insulating tape, insulating resin, etc.) is disposed between the cathode lead layer of each capacitor element 1 and the strip conductor 5a, whereby the cathode lead layer and the strip conductor 5a To avoid contact.

Thereafter, the plurality of capacitor elements 1 (14 in this example) that have been connected are collectively sealed with an exterior resin, and the resulting exterior resin sealing bodies are line α-α, line β-β, It cut | disconnected by the line | wire (gamma) -gamma and separated into pieces. Note that the number of capacitor elements 1 to be collectively sealed may be equal to or greater than the number of capacitor elements 1 included in one solid electrolytic capacitor.
In the present embodiment, since six capacitor elements 1 are included in one solid electrolytic capacitor, the number of capacitor elements 1 to be collectively sealed may be six or more.

  FIG. 2 shows a chip-shaped solid electrolytic capacitor 10a according to Example 1 manufactured through the above steps. 2A is a transverse sectional view of the solid electrolytic capacitor 10a, and FIG. 2B is a longitudinal sectional view of the solid electrolytic capacitor 10a. In the following description, the dimension in the x direction in FIGS. 2A and 2B is “width”, the dimension in the y direction is “length”, and the dimension in the z direction is “height”.

  As shown in FIG. 2A, in this embodiment, six capacitor elements 1 are arranged side by side in the length direction. Further, as shown in FIG. 2B, the anode electrode 5 and the cathode electrode 6 are disposed on the lower surface of the solid electrolytic capacitor 10a. In this embodiment, one cathode electrode 6 is arranged between two anode electrodes 5 arranged at a predetermined interval.

  The chip size is length: 7.3 mm, width: 4.3 mm, and height: 1.2 mm. The rated voltage and capacitance are 6.3 V and 100 μF, respectively.

[Example 2]
FIG. 3 shows a state of the solid electrolytic capacitor element according to Example 2 before sealing the exterior resin.
Capacitor element 1 is a porous body formed by pressing and sintering the tantalum powder while embedding an anode lead in tantalum powder, which is a valve action metal, and forming a dielectric oxide film layer on the surface of the porous body After the capacitor anode body was prepared, a conductive polymer layer as a cathode, and a carbon layer and a silver layer as a cathode lead layer were sequentially formed on the surface of the capacitor anode body.

  Later, the strip-shaped conductor 5b to be the anode electrode 5 and the strip-shaped conductor 6b to be the cathode electrode 6 were previously arranged at predetermined intervals so that the major axis directions of the respective strip-shaped conductors were parallel.

  Subsequently, an arbitrary two capacitor elements (for example, 1c, 1d) of the plurality of capacitor elements 1 that are produced constitute a capacitor element pair, and the capacitor elements 1c, 1d that constitute the pair have the same polarity portion. Arranged to face each other. In this embodiment, the capacitor elements 1c and 1d are arranged so that the anode lead 2 side faces each other. Then, each anode lead 2 and the strip conductor 5b were connected through the metal block 3, and the cathode lead layers of the capacitor elements 1c and 1d were connected to separate strip conductors 6b. The cathode lead layer and the strip-like conductor 6 b were connected via the conductive adhesive 4.

  Thereafter, the plurality of capacitor elements 1 (28 in this example) that have been connected are collectively sealed with an exterior resin, and the obtained exterior resin sealing bodies are line α-α, line β-β, It cut | disconnected by the line | wire (gamma) -gamma and separated into pieces. In the present embodiment, since 12 capacitor elements 1 are included in one solid electrolytic capacitor, the number of capacitor elements 1 to be collectively sealed may be 12 or more.

  FIG. 4 shows a chip-shaped solid electrolytic capacitor 10b according to Example 2 manufactured through the above steps. 4A is a transverse sectional view of the solid electrolytic capacitor 10b, and FIG. 4B is a longitudinal sectional view of the solid electrolytic capacitor 10b.

  As shown in FIG. 4A, in this embodiment, two capacitor elements 1 are arranged side by side in the width direction and six in the length direction. That is, a total of twelve capacitor elements 1 are arranged in the solid electrolytic capacitor 10a. Further, as shown in FIG. 4B, the anode electrode 5 and the cathode electrode 6 are disposed on the lower surface of the solid electrolytic capacitor 10b. In this embodiment, one anode electrode 5 is arranged between two cathode electrodes 6 arranged at a predetermined interval. The chip size, rated voltage, and capacitance are all the same as those of the solid electrolytic capacitor 10a according to the first embodiment.

[Example 3]
FIG. 5 shows a state of the solid electrolytic capacitor element according to Example 3 before sealing the exterior resin.
In this embodiment, the two capacitor elements 1e and 1f constituting the pair are arranged so that the cathode sides face each other. Then, the cathode lead layers of the capacitor elements 1 e and 1 f and the strip conductor 6 c are connected through the conductive adhesive 4, and each anode lead 2 is connected to the separate strip conductor 5 c through the metal block 3. . Therefore, in this embodiment, one cathode electrode 6 is arranged between two anode electrodes 5 arranged at a predetermined interval (see FIG. 6B).

  Other configurations and manufacturing processes were the same as those of the solid electrolytic capacitor element according to Example 2.

  FIG. 6 shows a chip-shaped solid electrolytic capacitor 10c according to the third embodiment. 6A is a transverse sectional view of the solid electrolytic capacitor 10c, and FIG. 6B is a longitudinal sectional view of the solid electrolytic capacitor 10c.

  As shown in FIG. 6A, also in this embodiment, two capacitor elements 1 are arranged side by side in the width direction and six in the length direction. That is, a total of 12 capacitor elements 1 are arranged in the solid electrolytic capacitor 10c. The chip size, rated voltage, and capacitance are all the same as those of the solid electrolytic capacitor 10a according to the first embodiment.

[Conventional example]
As a conventional example, a solid electrolytic capacitor described in Patent Document 2 was produced. As shown in FIG. 7, in the solid electrolytic capacitor 10d according to the conventional example, only one relatively large capacitor element 1 ′ is arranged. The chip size, rated voltage, and capacitance are all the same as those of the solid electrolytic capacitor 10a according to the first embodiment.

Table 1 shows the dimensions of the capacitor elements used in Examples 1 to 3 and the conventional example.

[Results of comparative study]
100 chip-shaped solid electrolytic capacitors according to Examples 1 to 3 and the conventional example were produced, and the ESR value and ESL value were measured. The measurement results (average values) are shown in Table 2. The ESR value was measured with an LCR measuring instrument manufactured by Hewlett Packard, and the ESL value was measured with an impedance analyzer manufactured by Agilent. The measurement temperatures were all room temperature.

As shown in Table 2, in the solid electrolytic capacitor according to each example adopting the lower surface electrode structure and the multi-element structure that do not require a lead frame, the electrode lead area of the capacitor element arranged inside increases, Compared with the conventional example, the ESR could be reduced.
Further, in the solid electrolytic capacitor according to Example 1, the ESL can be greatly reduced compared to the conventional example by arranging the polar parts (anode and cathode) of adjacent capacitor elements to be staggered. It was.
In the solid electrolytic capacitors according to Example 2 and Example 3 as well, the same polarity portions of the capacitor elements constituting the pair are arranged facing each other, so that magnetic field cancellation occurs during charging and discharging, and ESL is compared with the conventional example. Can be greatly reduced.

The preferred embodiments of the solid electrolytic capacitor according to the present invention have been described above, but the present invention is not limited to this.
For example, in each embodiment, the number of capacitor elements included in one solid electrolytic capacitor is six or twelve, but can be changed to any number of two or more. Specifically, by changing the number of capacitor elements of Example 2 and Example 3 to 6, the chip size is length: 3.65 mm, width: 4.3 mm, height: 1.2 mm, electrostatic The capacity can be 50 μF. In the present invention, low ESL is realized by canceling out magnetic fields during charging / discharging, and therefore, an even number of capacitor elements is more desirable.

  In Example 2, the capacitor element 1 is installed so that the anode lead 2 faces the capacitor element 1, but the capacitor element 1 c constituting the capacitor element pair by shifting the burying position of the anode lead 2 from the center of the capacitor element 1, The capacitor element 1 may be arranged so that the 1d anode leads 2 are arranged in the length direction (y direction in FIG. 4).

  In each embodiment, tantalum is used as the anode material, but other valve action metals such as niobium may be used. Furthermore, in each Example, although the conductive polymer was used as a cathode material, you may replace with other cathode materials, such as manganese dioxide. Those skilled in the art will readily understand that equivalent effects can be obtained even if such replacement is performed.

It is a top view which shows the state before exterior resin sealing of the solid electrolytic capacitor which concerns on Example 1. FIG. It is sectional drawing of the solid electrolytic capacitor which concerns on Example 1, Comprising: (A) is a cross-sectional view, (B) is a longitudinal cross-sectional view in line BB of (A). It is a top view which shows the state before exterior resin sealing of the solid electrolytic capacitor which concerns on Example 2. FIG. It is sectional drawing of the solid electrolytic capacitor which concerns on Example 2, Comprising: (A) is a cross-sectional view, (B) is a longitudinal cross-sectional view in line BB of (A). 6 is a plan view showing a state of a solid electrolytic capacitor according to Example 3 before sealing an exterior resin. FIG. It is sectional drawing of the solid electrolytic capacitor which concerns on Example 3, Comprising: (A) is a cross-sectional view, (B) is a longitudinal cross-sectional view in line BB of (A). It is sectional drawing of the solid electrolytic capacitor which concerns on a prior art example, Comprising: (A) is a cross-sectional view, (B) is a longitudinal cross-sectional view in line BB of (A).

Explanation of symbols

1 Capacitor element 2 Anode lead 3 Metal block 4 Conductive adhesive 5 Anode electrode 6 Cathode electrode 7 Masking portion

Claims (7)

A chip-shaped solid electrolytic capacitor formed by resin-sealing a plurality of capacitor elements having two polar parts of a cathode and an anode,
Two first electrodes arranged at a predetermined interval;
One second electrode disposed between the first electrodes;
With
Among the plurality of capacitor elements, any two capacitor elements constitute a capacitor element pair,
The two capacitor elements constituting the capacitor element pair are arranged so that the anodes are staggered around the cathode, the anodes are connected to the separate first electrodes, and the cathodes are connected to the second electrodes. A chip-shaped solid electrolytic capacitor, characterized in that the cathode is further connected to the first electrode on the side where the anode of the capacitor element is not connected via a masking portion having insulation properties. A chip-shaped solid electrolytic capacitor formed by resin-sealing a plurality of capacitor elements having two polar parts of a cathode and an anode,
Two first electrodes arranged at a predetermined interval;
One second electrode disposed between the first electrodes;
With
Among the plurality of capacitor elements, any two capacitor elements constitute a capacitor element pair,
The two capacitor elements constituting the capacitor element pair are arranged so that the same polarity portions face each other, the opposite polarity portions are connected to the second electrode, and the other polarity portions are respectively separated from each other. A chip-shaped solid electrolytic capacitor characterized in that it is connected to one electrode.   The capacitor element is produced by forming a capacitor anode body made of a valve metal around an anode lead, and sequentially forming a cathode layer and a cathode lead layer on the surface of the capacitor anode body. The chip-shaped solid electrolytic capacitor according to claim 1 or 2.   4. The chip-shaped solid electrolytic capacitor according to claim 3, wherein the anode lead is connected to the second electrode, and the cathode lead layer is connected to the first electrode.   4. The chip-shaped solid electrolytic capacitor according to claim 3, wherein the anode lead is connected to the first electrode, and the cathode lead layer is connected to the second electrode. Two first electrodes arranged at a predetermined interval, one second electrode arranged between the first electrodes, and m pieces having two polar parts of a cathode and an anode (where m ≧ 2) a manufacturing method of a chip-shaped solid electrolytic capacitor including the capacitor element of
The first strip conductor serving as the first electrode and the second strip conductor serving as the second electrode are arranged at a predetermined interval so that the major axis direction is parallel,
Among n capacitor elements prepared in advance (where n ≧ m), any two capacitor elements are used as a capacitor element pair.
The two capacitor elements constituting the capacitor element pair are arranged so that the anodes are staggered around the cathode, and the anodes are connected to the separate first band conductors arranged on both sides of the second band conductor. And connecting the cathode to the second strip conductor, and further connecting the cathode to the first strip conductor on the side where the anode of the capacitor element is not connected via an insulating masking portion,
After sealing the n capacitor elements together with an exterior resin,
A chip-shaped solid electrolytic capacitor manufacturing method, wherein the obtained exterior resin sealing body is cut at a position where the m capacitor elements are included. Two first electrodes arranged at a predetermined interval, one second electrode arranged between the first electrodes, and m pieces having two polar parts of a cathode and an anode (where m ≧ 2) a manufacturing method of a chip-shaped solid electrolytic capacitor including the capacitor element of
The first strip conductor serving as the first electrode and the second strip conductor serving as the second electrode are arranged at a predetermined interval so that the major axis direction is parallel,
Among n capacitor elements prepared in advance (where n ≧ m), any two capacitor elements are used as a capacitor element pair.
The same polarity part of the two capacitor elements constituting the capacitor element pair facing each other is connected to the second strip conductor, and the other polar part is disposed on both sides of the second strip conductor. Connect to each strip conductor,
After sealing the n capacitor elements together with an exterior resin,
A chip-shaped solid electrolytic capacitor manufacturing method, wherein the obtained exterior resin sealing body is cut at a position where the m capacitor elements are included.

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