JP2005158903A - Solid electrolytic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower the ESR of a solid electrolytic capacitor using a plurality of capacitor elements and to increase capacitance per unit area by utilizing dead space effectively. <P>SOLUTION: A plurality of capacitor elements 1 are mounted on a substrate 2 where a first conductive pattern 21 and a second conductive pattern 22 are formed such that the anode lead wires 11a and 11b of two capacitor elements 1a and 1b are directed oppositely from each other. In the extension space up to the forward end of the anode lead wire on the end face where the anode lead wire 11a of one capacitor element 1a is led out, a pair of capacitor elements arranged with the anode lead wire 11b of the other capacitor element 1b are mounted as a unit 12 on the substrate 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid electrolytic capacitor using a plurality of capacitor elements.

  In recent years, electronic devices such as mobile phones, personal computers, digital cameras, and the like have been mounted with higher density electronic components on wiring boards due to dramatic progress in miniaturization technology for surface mount devices. Under such circumstances, the tantalum solid electrolytic capacitor has an excellent characteristic that it can be reduced in size and increased in capacity, and is frequently used in applications such as a smoothing filter of a power supply device. In addition to tantalum metal, valve action metals include metals such as aluminum, niobium, and titanium. However, tantalum metal has excellent characteristics in terms of capacitance and dielectric film characteristics, so it has a small and large capacity. Most commonly used in applications.

  By the way, in such a tantalum electrolytic capacitor, a low ESR is required in a high frequency region with a high frequency of the CPU, and in order to meet this demand, in recent years, a conductive material such as polypyrrole, polythiophene, or a derivative thereof is required. Solid electrolytic capacitors using a conductive polymer as a solid electrolyte have been put into practical use.

  However, even in such a solid electrolytic capacitor, it cannot be said that the performance with respect to the high frequency of the CPU is sufficient, and further lower ESR is desired.

The following patent documents exist in the technology regarding the low ESR in such a solid electrolytic capacitor.
JP 2001-284192 A JP 2002-134362 A

  The solid electrolytic capacitor described in Patent Document 1 employs a structure in which a plurality of capacitor elements are stacked, and the resistance component of each capacitor element forms a parallel circuit. ESR is reduced.

  However, in such a configuration, it is necessary to stack a plurality of capacitor elements in order to increase the capacity of the solid electrolytic capacitor, so that the product size in the height direction of the solid electrolytic capacitor becomes large. End up.

  In addition, the solid electrolytic capacitor described in Patent Document 2 employs a structure in which a plurality of capacitor elements are arranged in parallel, and the resistance components of the individual capacitor elements also form a parallel circuit. The ESR of the entire electrolytic capacitor is reduced.

  However, according to such an arrangement of the capacitor element, the product size in the height direction will not increase, but if it is intended to expand the capacitance, it will extend only to one side of the solid electrolytic capacitor in the lateral direction. become.

  Further, in the solid electrolytic capacitors disclosed in Patent Document 1 and Patent Document 2, the capacitor elements are aligned by aligning the lead-out direction of the anode lead-out line to the same direction, and the anode lead-out line and the lead frame or the anode lead are joined. However, the vicinity of the junction between the lead-out line of the anode and the lead frame or the anode lead does not contribute to the capacitance of the solid electrolytic capacitor. It becomes a space. When the anode lead lines of the capacitor elements are aligned so as to be in the same direction, this dead space increases in proportion to the number of capacitor elements, which increases the capacitance per unit volume. It is not intended.

  In the present invention, a plurality of capacitor elements are used to reduce the ESR of the solid electrolytic capacitor, and the effective use of dead space increases the capacitance per unit volume.

  The solid electrolytic capacitor of the present invention includes a dielectric oxide film formed on the surface of a sintered body formed by molding a valve action metal powder and sintered into a prismatic shape so as to derive an anode lead line from one end face. A capacitor element formed by sequentially forming a solid electrolyte layer and a cathode layer on an oxide film has a first conductive pattern electrically connected to the anode lead-out line, and a second electrically connected to the cathode layer. A solid electrolytic capacitor array in which a plurality of conductive elements are mounted on the upper surface of a substrate and the capacitor elements are molded with a resin. The two capacitor elements are arranged so that their anode lead lines are opposite to each other. And a capacitor in which the anode lead-out line of the other capacitor element is arranged in the space extending from the end face leading out the anode lead-out line of one capacitor element to the tip of the anode lead-out line. Characterized in that mounted on the substrate support element pair as a unit unit.

  Since the solid electrolytic capacitor of this invention has arrange | positioned the several capacitor | condenser element as a parallel circuit, ESR of the whole solid electrolytic capacitor can be reduced.

  In addition, since the dead spaces of the individual capacitor elements are overlapped, the dead space of the entire solid electrolytic capacitor can be reduced, and the capacitance per unit volume of the solid electrolytic capacitor can be increased. .

(First embodiment)
A perspective view in which a part of the solid electrolytic capacitor of the present invention is cut away is shown in FIG.

  Reference numeral 1 in FIG. 1 denotes a capacitor element, in which a tantalum metal powder is molded into a prism shape, and a dielectric oxide film is formed on a sintered body in which an anode lead wire 11 made of a tantalum round bar is embedded and sintered. Further, a solid electrolyte layer made of a conductive polymer such as polypyrrole, polythiophene or a derivative thereof is formed on the dielectric oxide film layer, and a cathode layer made of a silver paste layer, a graphite layer, or the like is sequentially formed. is there.

  In this capacitor element 1, an anode lead-out line 11 is led out from one end face of the sintered body, and the lead-out position is derived from a substantially center position of the end face.

  Reference numeral 2 denotes a substrate made of an insulator, and a conductive pattern is formed on the surface thereof. As shown in FIG. 2A, the conductive pattern includes a first conductive pattern 21 electrically connected to the anode lead-out line of the capacitor element, and a second conductive pattern 22 electrically connected to the cathode layer of the capacitor element. Is formed. On the back side of the substrate, as shown in FIG. 2B, an electrode 25 made of a BGA electrode to which solder balls are connected is formed. The conductive patterns 21 and 22 on the front surface of the substrate and the electrode 25 on the back surface are connected by a through hole 24 as shown in FIG.

  The substrate 2 has an insulating property and can be used as an epoxy resin, polyimide resin, fluororesin, or the like as a material. The conductive pattern is made of copper foil, the through hole is formed by copper plating, and nickel plating and gold plating are further formed on the copper plating as required.

  Reference numeral 3 denotes a rod-shaped connecting member made of a conductive member, which electrically connects the anode lead-out line and the first conductive pattern. As the material of the connecting member, copper, copper alloy, 42 alloy (iron-42% nickel alloy) or the like can be used.

  Reference numeral 4 denotes an exterior resin made of an epoxy resin or the like, and is formed by transfer molding or the like.

  Next, the mounting position of the capacitor element in the solid electrolytic capacitor of the present invention will be described. FIG. 3 is a top view showing a state in which the capacitor element is mounted on the substrate.

  FIG. 3 shows an example in which six capacitor elements are mounted on a substrate. The capacitor elements are arranged such that the two capacitor elements 1a and 1b have their anode lead lines 11a and 11b in opposite directions. Then, the anode lead-out line 11b of the other capacitor element 1b is arranged in an extended space (indicated by a thick dotted line in the drawing) of the end face from which the anode lead-out line 11a of one capacitor element 1a is led out to the tip of the anode lead-out line 11a. To be mounted.

  The extension space of the end surface from which the anode lead-out line 11a of the capacitor element 1a is extended to the tip of the anode lead-out line 11a is a dead space that does not contribute to the capacitance of the solid electrolytic capacitor. If mounted on the substrate 2 in such an arrangement, the dead spaces of the individual capacitor elements overlap, so that the dead space of the entire solid electrolytic capacitor can be reduced, and the static capacity per unit volume of the solid electrolytic capacitor can be reduced. It is possible to increase the electric capacity.

  The two capacitor element pairs are set as unit units 12 (indicated by thin dotted lines in the figure), and the capacitor element pairs of the plurality of unit units 12 are mounted on the substrate. In FIG. 3, capacitor unit pairs of three unit units are mounted in parallel.

  The number of capacitor elements 1 mounted on the substrate 2 is arbitrary as long as it is two or more, and can be appropriately designed according to the capacitance and ESR characteristics required for the solid electrolytic capacitor.

  Here, as a comparative example, the case where the capacitor element is mounted at a position as shown in FIG. 4 is compared. As shown in FIG. 4A, when the anode lead-out wires 11 face each other at the mounting position of the capacitor element 1, a lot of dead space of the capacitor element 1 is left. An increase in capacitance per unit volume cannot be expected.

  Also, as shown in FIG. 4B, when the anode lead-out line 11a of one capacitor element 1a is mounted so as to be arranged in the vicinity of the side surface of the other capacitor element 1b, the dead space should be reduced. However, if the shape of the connecting member 3 is not complicated, the anode lead-out lines cannot be joined. Therefore, the process of processing the connecting member 3 becomes complicated, and the manufacturing process becomes complicated.

  The solid electrolytic capacitor according to the present invention described above is manufactured by the following process.

  First, the capacitor element 1 is prepared by a known technique. Capacitor element 1 is obtained by molding tantalum powder into a prismatic shape, embedding anode lead-out wire 11 made of tantalum wire and sintering it to obtain a sintered body. Further, the sintered body is immersed in an electrolytic solution such as phosphoric acid, and a dielectric oxide film is formed on the tantalum surface of the sintered body by an anodic oxidation method in which a predetermined DC voltage is applied. Next, a solid electrolyte layer made of a derivative such as polythiophene is formed on the dielectric oxide film layer. Further, on the solid electrolyte layer, a graphite paste is applied and dried to form a graphite layer, and further a silver paste is applied and dried to form a silver paint layer.

  The substrate 2 has a predetermined through-hole formed in a double-sided copper-clad insulating plate made of epoxy resin, and then unnecessary copper foil is removed by etching, and a first conductive pattern 21 having a predetermined shape and a first shape are formed on the surface of the substrate 2. Two conductive patterns 22 are formed. A land 23 for joining solder balls is formed in a rectangular shape on the back surface of the substrate 2. The thickness of the copper foil in such a double-sided copper-clad insulating plate is 5 to 18 μm. Then, a copper plating layer is formed on the inner surface of the through hole in the substrate by copper plating. Copper plating can be either electroplating or electroless plating. , And a thickness of 10 to 25 μm. Furthermore, if necessary, nickel plating or gold plating is applied to form the through hole 24. Through the through holes 24, the first conductive pattern 21 and the second conductive pattern 22 on the surface of the substrate are electrically connected to the land 23 on the back surface of the substrate. Further, a solder ball is joined to the land 23 on the back surface of the substrate 2 to form a BGA electrode 25. The conductive patterns 21 and 22 and the through holes 24 on the substrate 2 can be formed by using a general printed circuit board manufacturing technique such as electroplating or electroless plating.

  Next, the connection member 3 is bonded onto the first conductive pattern of the substrate 2. The thickness of the connecting member 3 is formed to match the length from the substrate mounting surface of the capacitor element 1 to the lower end of the anode lead-out line 11. The connecting member 3 is joined to the first conductive pattern 21 by a conductive adhesive or soldering.

  Further, the capacitor element 1 is mounted on the substrate 2. The mounting position is as described above. When the capacitor element 1 is mounted on the substrate 2, the cathode layer formed on the capacitor element 1 and the second conductive pattern 22 are joined by a conductive adhesive.

  When the capacitor element 1 is bonded to the second conductive pattern 22, the anode lead wire 11 of the capacitor element 1 is mounted on the connection member 3. At this stage, since the anode lead-out wire 11 and the joining member 3 are only in light contact, the anode lead-out wire 11 and the connection member 3 are welded in order to secure electrical connection. For welding, a resistance welding method, a laser welding method, or the like can be used.

  Next, the mounting surface of the capacitor element on the substrate is transfer molded with an epoxy resin to form the exterior resin 4 to complete the solid electrolytic capacitor. The exterior resin 4 may be molded by a method other than transfer molding, and the exterior resin 4 can be formed by a printing method or a potting method.

(Second Embodiment)
A second embodiment of the present invention will be described.
FIG. 5A is a perspective view showing the shape of a capacitor element used in the second embodiment of the present invention, and FIG. 5B is a cross-sectional view showing a solid electrolytic capacitor of the second embodiment of the present invention. is there.

  In the solid electrolytic capacitor of the second embodiment, the capacitor element 1 is formed by using a flat plate as the anode lead-out wire 11 embedded in the capacitor element 1. In this case, it is preferable that the anode lead-out line is substantially at the center position of the capacitor element and that the substrate mounting end face of the capacitor element and the flat surface of the anode lead-out line are parallel to each other.

  Then, as shown in FIG. 5A, the plate-like anode lead-out line 11 is bent so that the tip of the anode lead-out line becomes the same height as the substrate contact end surface of the capacitor element 1.

  Then, a capacitor element is mounted on the same substrate as that of the first embodiment. The mounting position of the capacitor element in the solid electrolytic capacitor of the second embodiment is the same as that of the first embodiment, and the mounting position of the capacitor element is the anode lead-out line on the end face from which the anode lead-out line of one capacitor element is derived. The anode lead-out line of the other capacitor element is arranged in the extended space to the tip of the other capacitor element.

  Even if the anode lead-out line is bent, the extension space of the end face from which the anode lead-out line of the capacitor element is extended to the tip of the anode lead-out line is a dead space that does not contribute to the capacitance of the solid electrolytic capacitor. If the capacitor elements are arranged as described above, the dead spaces of the individual capacitor elements overlap each other, so that the dead space of the entire solid electrolytic capacitor can be reduced, and the unit volume per unit volume of the solid electrolytic capacitor can be reduced. The capacitance can be increased.

  In the solid electrolytic capacitor of the second example, the connection member in the solid electrolytic capacitor of the first embodiment is not used.

  Since the anode lead-out line 11 is bent and has the same height as the board mounting surface of the capacitor element 1, when the capacitor element 1 is mounted on the board 2, the anode copper lead-out line 11 becomes the first conductive pattern 21. Further, the cathode layer of the capacitor element 1 comes into contact with the second conductive pattern 22. The first conductive pattern 21 and the anode lead-out line 11 can be joined by a conductive adhesive or welding. Further, the cathode layer of the capacitor element 1 and the second conductive pattern 22 can be joined by a conductive adhesive as in the first embodiment.

1 is a partially cutaway perspective view showing a first embodiment of a solid electrolytic capacitor of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is drawing which shows the structure of the board | substrate used for the solid electrolytic capacitor of this invention, (a) is an upper surface perspective view of a board | substrate, (b) is a back surface perspective view of a board | substrate, (c) is sectional drawing. It is drawing which shows the mounting position of the capacitor | condenser element to the board | substrate of the solid electrolytic capacitor of this invention. It is drawing which shows the mounting position of the capacitor | condenser element to the board | substrate of the solid electrolytic capacitor of a comparative example. It is drawing which shows 2nd Embodiment of the solid electrolytic capacitor of this invention, (a) is a perspective view which shows the structure of a capacitor | condenser element, (b) is sectional drawing of a solid electrolytic capacitor.

Explanation of symbols

1, 1a, 1b Capacitor element 11, 11a, 11b Anode lead-out line 12 Unit unit (capacitor element pair)
2 Substrate 21 First conductive pattern 22 Second conductive pattern 23 Land 24 Through hole 25 Electrode 3 Connecting member 4 Exterior resin

Claims (1)

A dielectric oxide film is formed on the surface of the sintered body that is molded into a prismatic shape so that the anode lead wire is derived from one end face of the valve action metal powder, and a solid electrolyte layer is formed on the dielectric oxide film. And a capacitor element formed by sequentially forming a cathode layer,
A plurality of capacitor elements are mounted on the top surface of the substrate on which the first conductive pattern electrically connected to the anode lead-out line and the second conductive pattern electrically connected to the cathode layer are formed. A solid electrolytic capacitor array formed by molding,
Two capacitor elements are arranged so that the anode lead-out lines are in opposite directions, and the other capacitor element is disposed in an extension space from the end face leading out the anode lead-out line of one capacitor element to the tip of the anode lead-out line. A solid electrolytic capacitor characterized in that a capacitor element pair in which an anode lead-out wire is disposed is mounted on a substrate as a unit unit.