JP2002110459A - Solid electrolytic chip capacitor - Google Patents

Solid electrolytic chip capacitor

Info

Publication number
JP2002110459A
JP2002110459A JP2000296598A JP2000296598A JP2002110459A JP 2002110459 A JP2002110459 A JP 2002110459A JP 2000296598 A JP2000296598 A JP 2000296598A JP 2000296598 A JP2000296598 A JP 2000296598A JP 2002110459 A JP2002110459 A JP 2002110459A
Authority
JP
Japan
Prior art keywords
electrode
solid electrolytic
layer
chip
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000296598A
Other languages
Japanese (ja)
Inventor
Kazuo Uzawa
一夫 鵜沢
Junichi Murakami
村上  順一
Nobuo Yuuhi
伸夫 夕日
Hisashi Suwa
壽志 諏訪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Corp
Original Assignee
Nichicon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichicon Corp filed Critical Nichicon Corp
Priority to JP2000296598A priority Critical patent/JP2002110459A/en
Publication of JP2002110459A publication Critical patent/JP2002110459A/en
Pending legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized chip capacitor having large capacitance at a low cost. SOLUTION: The chip capacitor has a lead 1, a capacitor element 2 formed of a dielectric oxide film, a solid electrolytic layer, and a cathode lead-out layer; an electrode substrate 7 to be a capacitor electrode; and a packaging resin 2. The electrode substrate 7 is provided with an insulating layer 4 having at least two through-holes, a conductive plate 3 disposed to cover one of the through-holes, and an electrode layer 10 formed by burying the through-holes.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はチップ状固体電解コ
ンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip solid electrolytic capacitor.

【0002】[0002]

【従来の技術】従来のチップ状固体電解コンデンサは、
図5のように陽極リード1を有し固体電解質層、陰極引
出層を形成したコンデンサ素子2をリードフレーム11
に接続し、外装樹脂9の側面からリードフレーム11を
導出し、外装樹脂9に沿って折り曲げ加工し、基板接地
面に電極を形成していた。また特開平8−148386
号公報では、コンデンサ素子を支持する段差を形成した
絶縁スルーホール電極基板にコンデンサ素子および導出
リードをそれぞれ導電性接着剤にて接続する製造方法が
提案されている。
2. Description of the Related Art Conventional chip-shaped solid electrolytic capacitors are:
A capacitor element 2 having an anode lead 1 and a solid electrolyte layer and a cathode extraction layer as shown in FIG.
Then, the lead frame 11 is led out from the side surface of the exterior resin 9 and bent along the exterior resin 9 to form an electrode on the substrate ground plane. Also, Japanese Patent Application Laid-Open No. 8-148386.
Japanese Patent Laid-Open Publication No. H11-15064 proposes a manufacturing method in which a capacitor element and a lead are connected to an insulating through-hole electrode substrate having a step for supporting the capacitor element with a conductive adhesive.

【0003】[0003]

【発明が解決しようとする課題】また部品の高密度実装
化が進められる中、チップ状固体電解コンデンサは小形
化が求められてきた。しかしながら図5のようにリード
フレームを折り曲げて外部電極を形成する従来のチップ
状固体電解コンデンサでは、製品体積が小さくなるほど
体積中に占めるリードフレームの割合が増え、収納する
コンデンサ素子の体積が十分取れないという問題があっ
た。さらに、基板に搭載する際、部品間距離を短縮する
と、隣接する部品がリフローはんだ付けでわずかに位置
ずれする場合があるため、電子部品の側面にリードフレ
ームを構成する従来のチップ状固体電解コンデンサなど
は部品間で短絡する危険があり、さらなる高密度実装が
進められないという問題があった。一方、段差を形成し
たスルーホール電極基板にコンデンサ素子を導電性接着
剤にて接続してチップ部品の下面、すなわち基板接地面
のみに電極形成した構造のチップ部品が提案されている
が、電極基板の製作コストがかさむ上、コンデンサ素子
の導出リードは通常タンタルなどの弁作用金属が用いら
れ、導電性接着剤による電気的接続では表面酸化により
接続界面の抵抗が増加してコンデンサ特性が劣化し、さ
らには接合強度が弱くなり剥離を生じさせるという問題
があった。また、上記従来のコンデンサは電極端子自体
の厚さが少なくとも80μm以上となるため、製品下面
とコンデンサ素子下面との距離が140μm以上とな
り、部品の小型化に伴う素子収容容量を向上させる阻害
要因となっていた。
Further, as components are mounted at a high density, there is a demand for miniaturization of chip-shaped solid electrolytic capacitors. However, in the conventional chip-shaped solid electrolytic capacitor in which the lead frame is bent to form external electrodes as shown in FIG. 5, the smaller the product volume, the larger the proportion of the lead frame in the volume, and the volume of the capacitor element to be housed is sufficient. There was no problem. Furthermore, when mounting on a board, if the distance between components is shortened, adjacent components may be slightly displaced by reflow soldering, so a conventional chip-shaped solid electrolytic capacitor that forms a lead frame on the side of electronic components In such a case, there is a danger of short-circuiting between components, and there is a problem that further high-density mounting cannot be advanced. On the other hand, a chip component having a structure in which a capacitor element is connected to a stepped through-hole electrode substrate with a conductive adhesive and an electrode is formed only on the lower surface of the chip component, that is, only on the substrate ground plane, has been proposed. In addition to the increased manufacturing cost, the lead-out lead of the capacitor element is usually made of a valve metal such as tantalum, and the electrical connection using a conductive adhesive increases the resistance at the connection interface due to surface oxidation, deteriorating the capacitor characteristics. Further, there is a problem that the bonding strength is weakened and peeling is caused. Further, in the conventional capacitor, since the thickness of the electrode terminal itself is at least 80 μm or more, the distance between the lower surface of the product and the lower surface of the capacitor element is 140 μm or more. Had become.

【0004】[0004]

【課題を解決するための手段】本発明は、貫通孔を有す
る絶縁層と、貫通孔を覆う導電板と、貫通孔をはんだペ
ースト等で埋めて形成した電極層とを有する電極基板と
導出リードを具備したコンデンサ素子とを電気的に接続
した構造とすることにより、該電極基板の厚みを薄くで
き、素子収納容量に優れたチップ状コンデンサが実現で
きるものであり、また該コンデンサの側面のリードをな
くすことで高密度実装も可能とするものである。すなわ
ち、導出リード1を具備し、誘電体酸化皮膜、固体電解
質層、陰極引出層を形成したコンデンサ素子2と、コン
デンサの電極となる電極基板7と、外装樹脂9を有する
チップ状コンデンサにおいて、上記電極基板7が、少な
くとも2箇所の貫通孔を有する絶縁層4と、該貫通孔の
一方を覆うように配置した導電板3,3と、貫通孔内を
埋めて形成した電極層10,10とを有することを特徴
とするチップ状固体電解コンデンサである。
SUMMARY OF THE INVENTION The present invention is directed to an electrode substrate having an insulating layer having a through hole, a conductive plate covering the through hole, an electrode layer formed by filling the through hole with a solder paste, and a lead. By electrically connecting the capacitor element with the capacitor element, the thickness of the electrode substrate can be reduced, and a chip capacitor excellent in element storage capacity can be realized. By eliminating the above, high-density mounting is also possible. That is, in the chip-shaped capacitor having the lead-out lead 1 and having the dielectric oxide film, the solid electrolyte layer, and the cathode extraction layer formed thereon, the electrode substrate 7 serving as the electrode of the capacitor, and the exterior resin 9, An electrode substrate 7 includes an insulating layer 4 having at least two through holes, conductive plates 3 and 3 arranged to cover one of the through holes, and electrode layers 10 and 10 formed to fill the through holes. It is a chip-shaped solid electrolytic capacitor characterized by having.

【0005】上記電極基板7が、貫通孔内と導電板3,
3上にメッキ層6a〜6dを有し、貫通孔内のメッキ層
6b,6dと電極層10,10とが接すること特徴とす
るチップ状固体電解コンデンサである。
[0005] The electrode substrate 7 is provided between the through hole and the conductive plate 3.
3 is a chip-shaped solid electrolytic capacitor characterized by having plating layers 6a to 6d on the substrate 3 and contacting the plating layers 6b and 6d in the through holes with the electrode layers 10 and 10.

【0006】そして、上記電極層が、はんだペーストお
よび/または銀ペーストの印刷、はんだ浴へのディッピ
ング、はんだボール接続のうち少なくとも1種以上で形
成したことを特徴とするチップ状固体電解コンデンサで
ある。
[0006] A chip-shaped solid electrolytic capacitor characterized in that the electrode layer is formed by at least one of printing of a solder paste and / or silver paste, dipping in a solder bath, and solder ball connection. .

【0007】上記はんだペースト、はんだ浴、はんだボ
ールが、錫または錫合金であることを特徴とする請求項
1〜3記載のチップ状固体電解コンデンサ。
The solid electrolytic capacitor according to claim 1, wherein said solder paste, solder bath and solder ball are made of tin or a tin alloy.

【0008】[0008]

【発明の実施の形態】電極基板の貫通孔にはんだペース
ト等の導電性ペーストの印刷やはんだ浴へのディッピン
グ、はんだボール接続で電極層を形成するため、下面電
極の垂直方向の位置精度を高めることができ、チップ状
固体電解コンデンサを基板に安定して搭載することがで
きる。また、導出リードを金属条材と導電性接着剤を介
して電極基板に電気的に接続し、さらにコンデンサ素子
を導電性接着剤を介して電極基板と電気的に接続し、該
電極基板が貫通孔を有する絶縁層と貫通孔を埋めて形成
した電極層を形成することで、コンデンサ素子に接続し
たリードフレームを外部電極とするコンデンサより素子
収納容量に優れたチップ状コンデンサを実現することが
できる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Since an electrode layer is formed by printing a conductive paste such as a solder paste in a through hole of an electrode substrate, dipping in a solder bath, and connecting a solder ball, the vertical positional accuracy of the lower electrode is improved. Therefore, the chip-shaped solid electrolytic capacitor can be stably mounted on the substrate. In addition, the lead lead is electrically connected to the electrode substrate via the metal strip and the conductive adhesive, and further, the capacitor element is electrically connected to the electrode substrate via the conductive adhesive. By forming the insulating layer having holes and the electrode layer formed by filling the through holes, it is possible to realize a chip-shaped capacitor having a higher element storage capacity than a capacitor having a lead frame connected to a capacitor element as an external electrode. .

【0009】さらに、導電板3,3を有することにより
電極基板7の厚みを厚くすることなく、電極層10,1
0の幅と位置を各々任意に設計することができ、少なく
とも部品側面に電極が形成されない構造とすることがで
きる。よって、部品間距離が0.1〜0.15mm程度
で基板設計した高密度実装基板で、リフローはんだ付け
時に部品の位置ずれが生じても、部品側面に導電部分が
ない構造であるため、部品間で電気的短絡が発生しな
い。その上角柱状の金属条材を導出リードと陽極外部端
子との接続に用い、電極基板7をほぼ平面状の基板とす
ることができるので低コストで極めて生産性の優れたコ
ンデンサを得ることができる。さらに、厚さの制約があ
るリードフレームを電極に使用しないので、極めて優れ
た体積有効活用率を有するチップ状固体電解コンデンサ
を提供することが可能である。
Further, by providing the conductive plates 3 and 3, the electrode layers 10 and 1 can be formed without increasing the thickness of the electrode substrate 7.
The width and position of 0 can be arbitrarily designed, and a structure in which no electrode is formed at least on the side surface of the component can be adopted. Therefore, a high-density mounting board designed with a distance between components of about 0.1 to 0.15 mm and having a structure in which there is no conductive portion on the side surface of the component even if the component is misaligned during reflow soldering. No electrical short circuit occurs between them. The upper prism-shaped metal strip is used for connection between the lead-out lead and the anode external terminal, and the electrode substrate 7 can be a substantially planar substrate. Therefore, a low-cost, extremely productive capacitor can be obtained. it can. Further, since a lead frame having a limited thickness is not used for an electrode, it is possible to provide a chip-shaped solid electrolytic capacitor having an extremely excellent volume effective utilization rate.

【0010】[0010]

【実施例】〔実施例1〕 以下に本発明の実施例につい
て図面に基づき具体的に説明する。図1は、本発明の実
施例を示すチップ状固体電解コンデンサの断面図であ
る。
[Embodiment 1] An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a cross-sectional view of a chip-shaped solid electrolytic capacitor showing an embodiment of the present invention.

【0011】導出リード1を具備したタンタル焼結体
に、公知の方法で誘電体酸化皮膜、固体電解質層、陰極
引出層を形成しコンデンサ素子2とした。2箇所の貫通
孔を設けた厚さ50μmのポリイミドフィルムの上面に
エポキシ系接着剤を塗布し、導電板3,3として厚さ1
8μmの圧延銅板を用いて、貫通孔を覆うように塗布面
に配置した後硬化させ、無光沢錫メッキで導電板と接す
るメッキ層6a〜6dを形成し、残った貫通孔にはんだ
ペーストを印刷し電極10,10とし、厚さ80μmの
電極基板7を形成した。次に、鉄−ニッケル合金を母材
とし、表面に無光沢錫メッキを施した金属条材5と、導
出リードを抵抗溶接し、金属条材とメッキ層6a、コン
デンサ素子2とメッキ層6cとを導電性接着剤8で各々
電気的に接続した後、コンデンサ素子を外装樹脂で被覆
し、1.6×0.8×0.8mm(1608サイズ)の
チップ状固体電解コンデンサを作製した。
A dielectric oxide film, a solid electrolyte layer, and a cathode extraction layer were formed on a tantalum sintered body provided with the lead 1 by a known method to obtain a capacitor element 2. An epoxy adhesive is applied to the upper surface of a 50 μm-thick polyimide film having two through holes, and the conductive plates 3 and 3 have a thickness of 1 μm.
Using a rolled copper plate of 8 μm, it is placed on the application surface so as to cover the through-holes and then cured, and the plating layers 6a to 6d in contact with the conductive plate are formed by matte tin plating, and the solder paste is printed in the remaining through-holes The electrodes 10, 10 were used to form an electrode substrate 7 having a thickness of 80 μm. Next, a metal strip 5 whose surface is matte tin-plated with an iron-nickel alloy as a base material and a lead lead are resistance-welded to form a metal strip and a plating layer 6a, a capacitor element 2 and a plating layer 6c. Were electrically connected with a conductive adhesive 8, respectively, and then the capacitor element was covered with an exterior resin to produce a chip-shaped solid electrolytic capacitor of 1.6 × 0.8 × 0.8 mm (1608 size).

【0012】〔実施例2〕 図2は本発明のその他の実
施例によるチップ状固体電解コンデンサの断面図であ
る。導電板として厚さ18μmの圧延銅板2枚を配置
し、ポリイミド樹脂を塗布、硬化して絶縁層4を形成し
た後、導電板上のポリイミド樹脂の一部を除去して絶縁
層4に貫通孔を形成し、無光沢はんだメッキでメッキ層
6a〜6dを形成後、残った貫通孔にはんだペーストを
印刷して電極10,10を形成し厚さ80μmの電極基
板7とした。その他は実施例と同様にして、1608サ
イズのチップ状固体電解コンデンサを作製した。
Embodiment 2 FIG. 2 is a sectional view of a chip solid electrolytic capacitor according to another embodiment of the present invention. Two 18 μm-thick rolled copper plates are arranged as conductive plates, and a polyimide resin is applied and cured to form an insulating layer 4. Then, a part of the polyimide resin on the conductive plate is removed to form a through hole in the insulating layer 4. After the plating layers 6a to 6d were formed by matte solder plating, solder paste was printed on the remaining through holes to form electrodes 10 and 10, thereby forming an electrode substrate 7 having a thickness of 80 μm. Otherwise, a 1608 size chip-shaped solid electrolytic capacitor was manufactured in the same manner as in the example.

【0013】従来例としてリードフレームを用いた16
08サイズのコンデンサを、比較例として特開平8−1
48386号公報記載の段付スルーホール電極基板を用
いた1608サイズのコンデンサを作製し、実施例1、
実施例2、従来例、比較例で、従来例を1.00とした
ときの製品内に最大収容可能な素子収容容積比率と、外
部電極である電極層またはリードフレームの設計値に対
する垂直方向の電極位置バラツキを表1に示した。
As a conventional example, a lead frame using 16
As a comparative example, a capacitor of 08 size was disclosed in
A 1608-size capacitor using a stepped through-hole electrode substrate described in Japanese Patent No. 48386 was manufactured.
In Example 2, the conventional example, and the comparative example, when the conventional example was set to 1.00, the element accommodation volume ratio that could be maximally accommodated in the product and the vertical direction with respect to the design value of the electrode layer or the lead frame as the external electrode. Table 1 shows electrode position variations.

【0014】[0014]

【表1】 [Table 1]

【0015】表1より本発明による実施例1,2は、従
来例、比較例より素子収容容積比率が高く優れており、
電極位置バラツキも従来例より少なく優れていることが
分かる。
Table 1 shows that Examples 1 and 2 according to the present invention have a higher element accommodation volume ratio than the conventional example and the comparative example.
It can be seen that the electrode position variation is smaller than that of the conventional example and is superior.

【0016】その他の実施例を図3,4に示す。金属条
材5の形状は角柱が望ましく、好ましくは三〜六角柱で
ある。金属条材5の形状を角柱とし、角柱の側面と内部
電極とを導電性接着剤で接続することで、電気的・物理
的に長期に安定した接続が可能となり、さらに角柱は転
がりにくいので作業性を改善することができる。なお、
金属条材5の導出リード溶接箇所を切り欠き加工しても
よい。
Another embodiment is shown in FIGS. The shape of the metal strip 5 is desirably a prism, preferably a tri-hexagonal prism. By making the shape of the metal strip 5 into a prism and connecting the side surface of the prism and the internal electrode with a conductive adhesive, a stable connection can be made electrically and physically for a long period of time, and the prism is hard to roll. Performance can be improved. In addition,
The lead welding portion of the metal strip 5 may be cut out.

【0017】実施例1、2では、電極層10の形成には
んだペーストの印刷を用いたが、銀ペースト、銀ペース
トとはんだペーストの印刷、はんだ浴へのディッピン
グ、はんだボール接続で構成しても実施例と同等の効果
が得られる。
In the first and second embodiments, the printing of the solder paste is used for forming the electrode layer 10. However, the electrode layer 10 may be formed by silver paste, printing of silver paste and solder paste, dipping in a solder bath, and solder ball connection. An effect equivalent to that of the embodiment can be obtained.

【0018】また、絶縁フィルムに導電板を貼り付け
後、または、導電板に絶縁性樹脂を塗布、硬化後、エッ
チング加工にて導電板の不要な部分を除去してもよい。
After the conductive plate is attached to the insulating film, or after the conductive plate is coated with an insulating resin and cured, unnecessary portions of the conductive plate may be removed by etching.

【0019】金属条材は外装樹脂9で外部と絶縁するこ
とを基本とするが、設計寸法的・製造設備の加工精度的
に外部に表出する可能性があることを見越し、実装はん
だ付け時、はんだに容易に濡れない材料が望ましく、ニ
ッケルまたはニッケル合金が好ましい。また金属条材の
表面メッキは前出の電極基板7と同じく無光沢はんだメ
ッキなどの材料を用いることができ、金属条材5の表面
にメッキ処理することで、導電性接着剤8との接続を電
気的、物理的に安定させることができる。
The metal strip material is basically insulated from the outside by the exterior resin 9, but in consideration of the possibility of being exposed to the outside due to the design dimensions and processing accuracy of the manufacturing equipment, the A material that does not easily wet with solder is desirable, and nickel or a nickel alloy is preferred. For the surface plating of the metal strip, a material such as matte solder plating can be used as in the case of the above-described electrode substrate 7, and the surface of the metal strip 5 is plated to be connected to the conductive adhesive 8. Can be electrically and physically stabilized.

【0020】なお、実施例1,2の電極基板厚みを80
μmとしたが、より薄い材料を用いた方が体積有効活用
効果が向上することは言うまでもなく、現在のリードフ
レーム材料として広く使用されているものが厚さ120
μmを中心に80μmから150μmであることに対し
いわゆるフレキシブル基板ではより薄くすることが可能
である。しかしながら基板厚みが25μm未満では基板
の剛性が弱くコンデンサの組立工程でのハンドリング性
が著しく劣化し生産性が極めて悪くなる。一方、90μ
mを超える基板厚みでは固体電解コンデンサに占める体
積比が大なるものとなり、体積効率が劣化する。よって
体積有効活用性、材料の入手性、さらにチップ状固体電
解コンデンサの生産性から電極基板厚さは25〜90μ
mの範囲が好ましい。
In the first and second embodiments, the thickness of the electrode substrate is set to 80.
It is needless to say that the use of a thinner material improves the volume effective utilization effect.
A thickness of 80 μm to 150 μm centering on μm can be made thinner with a so-called flexible substrate. However, when the thickness of the substrate is less than 25 μm, the rigidity of the substrate is weak, and the handleability in the capacitor assembling process is significantly deteriorated, and the productivity is extremely deteriorated. On the other hand, 90μ
If the substrate thickness exceeds m, the volume ratio occupying the solid electrolytic capacitor becomes large, and the volume efficiency deteriorates. Therefore, from the viewpoint of effective volume utilization, availability of materials, and productivity of the solid electrolytic capacitor chip, the thickness of the electrode substrate is 25 to 90 μm.
The range of m is preferred.

【0021】さらに、導電板にエッチングまたはパンチ
ング加工したものを用いて、連続した複数個の電極基板
を作製し、各電極基板に複数個のコンデンサ素子を各々
接続し、一括して外装樹脂で被覆後個々のコンデンサに
切り離してもよい。
Further, a plurality of continuous electrode substrates are manufactured by using the conductive plate etched or punched, and a plurality of capacitor elements are connected to each electrode substrate, and are collectively covered with an exterior resin. It may be later separated into individual capacitors.

【0022】[0022]

【発明の効果】上記のとおり本発明によるチップ状コン
デンサは、少なくとも2箇所の貫通孔を有する絶縁層
と、貫通孔を覆う導電板と、貫通孔を埋める電極層とを
有する電極基板を用いることで、製品側面に導通部を設
けることなく下面に電極を形成できるので高密度実装に
対応でき、さらに内部電極と外部電極との位置を任意に
設計できるので、極めて優れた体積有効活用率を有し、
また、電極基板下面の電極層を導電性ペースト印刷、は
んだ浴へのディッピング等で形成しているため、平面度
のバラツキが少なく安定した基板搭載が可能なチップ状
固体電解コンデンサを安価に得ることができる。
As described above, the chip-shaped capacitor according to the present invention uses an electrode substrate having an insulating layer having at least two through holes, a conductive plate covering the through holes, and an electrode layer filling the through holes. Since electrodes can be formed on the lower surface without providing a conductive part on the side of the product, it can be used for high-density mounting, and the positions of the internal and external electrodes can be arbitrarily designed. And
In addition, since the electrode layer on the lower surface of the electrode substrate is formed by conductive paste printing, dipping into a solder bath, etc., it is possible to obtain a low-cost chip-shaped solid electrolytic capacitor capable of stably mounting the substrate with little variation in flatness. Can be.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例によるチップ状固体電解コンデ
ンサの断面図である。
FIG. 1 is a cross-sectional view of a chip-shaped solid electrolytic capacitor according to an embodiment of the present invention.

【図2】本発明のその他の実施例によるチップ状固体電
解コンデンサの断面図である。
FIG. 2 is a sectional view of a chip-shaped solid electrolytic capacitor according to another embodiment of the present invention.

【図3】金属条材を六角柱とした実施例によるチップ状
固体電解コンデンサの断面図である。
FIG. 3 is a cross-sectional view of a chip-shaped solid electrolytic capacitor according to an embodiment in which a metal strip is a hexagonal column.

【図4】金属条材を三角柱とした実施例によるチップ状
固体電解コンデンサの断面図である。
FIG. 4 is a cross-sectional view of a chip-shaped solid electrolytic capacitor according to an embodiment in which a metal strip is used as a triangular prism.

【図5】従来のチップ状コンデンサの断面図である。FIG. 5 is a sectional view of a conventional chip capacitor.

【符号の説明】[Explanation of symbols]

1 導出リード 2 コンデンサ素子 3 導電板 4 絶縁層 5 金属条材 6a メッキ層(陽極側内部電極) 6b メッキ層(陽極側外部電極) 6c メッキ層(陰極側内部電極) 6d メッキ層(陰極側外部電極) 7 電極基板 8 導電性接着剤 9 外装樹脂 10 電極層 11 リードフレーム REFERENCE SIGNS LIST 1 lead-out 2 capacitor element 3 conductive plate 4 insulating layer 5 metal strip 6 a plating layer (anode internal electrode) 6 b plating layer (anode external electrode) 6 c plating layer (cathode internal electrode) 6 d plating layer (cathode external) Electrode) 7 electrode substrate 8 conductive adhesive 9 exterior resin 10 electrode layer 11 lead frame

───────────────────────────────────────────────────── フロントページの続き (72)発明者 夕日 伸夫 京都府京都市中京区御池通烏丸東入一筋目 仲保利町191番地の4 上原ビル3階 ニ チコン株式会社内 (72)発明者 諏訪 壽志 京都府京都市中京区御池通烏丸東入一筋目 仲保利町191番地の4 上原ビル3階 ニ チコン株式会社内 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Nobuo Sunset 4th floor of Uehara Bldg., 3rd floor, 191-st. Nichicon Co., Ltd., 3rd floor, Uehara Building, 191 Nakabori-cho, Oike-dori Karasuma-Higashi-iri, Nakagyo-ku, Kyoto-shi

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 導出リードを具備し、誘電体酸化皮膜、
固体電解質層、陰極引出層を形成したコンデンサ素子
と、コンデンサの電極となる電極基板と、外装樹脂を有
するチップ状固体電解コンデンサにおいて、 上記電極基板が、少なくとも2箇所の貫通孔を有する絶
縁層と、該貫通孔の一方を覆うように配置した導電板
と、貫通孔内を埋めて形成した電極層とを有することを
特徴とするチップ状固体電解コンデンサ。
1. A lead oxide lead, comprising: a dielectric oxide film;
A solid electrolyte layer, a capacitor element formed with a cathode extraction layer, an electrode substrate serving as an electrode of the capacitor, and a chip-shaped solid electrolytic capacitor having an exterior resin, wherein the electrode substrate has an insulating layer having at least two through holes. A chip-shaped solid electrolytic capacitor, comprising: a conductive plate arranged to cover one of the through holes; and an electrode layer formed by filling the inside of the through hole.
【請求項2】 請求項1記載の電極基板が、導電板上に
接するメッキ層を有し、貫通孔内のメッキ層と電極層と
が接することを特徴とするチップ状固体電解コンデン
サ。
2. The chip-shaped solid electrolytic capacitor according to claim 1, wherein the electrode substrate has a plating layer in contact with the conductive plate, and the plating layer in the through hole and the electrode layer are in contact with each other.
【請求項3】 上記電極層が、はんだペーストおよび/
または銀ペーストの印刷、はんだ浴へのディッピング、
はんだボール接続のうち少なくとも1種以上で形成した
ことを特徴とする請求項1、2記載のチップ状固体電解
コンデンサ。
3. The method according to claim 1, wherein the electrode layer comprises a solder paste and / or
Or printing silver paste, dipping into solder bath,
3. The solid electrolytic capacitor according to claim 1, wherein at least one of the solder ball connections is formed.
【請求項4】 上記はんだペースト、はんだ浴、はんだ
ボールが、錫または錫合金であることを特徴とする請求
項1〜3記載のチップ状固体電解コンデンサ。
4. The solid electrolytic capacitor according to claim 1, wherein said solder paste, solder bath and solder ball are made of tin or tin alloy.
JP2000296598A 2000-09-28 2000-09-28 Solid electrolytic chip capacitor Pending JP2002110459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000296598A JP2002110459A (en) 2000-09-28 2000-09-28 Solid electrolytic chip capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000296598A JP2002110459A (en) 2000-09-28 2000-09-28 Solid electrolytic chip capacitor

Publications (1)

Publication Number Publication Date
JP2002110459A true JP2002110459A (en) 2002-04-12

Family

ID=18778851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000296598A Pending JP2002110459A (en) 2000-09-28 2000-09-28 Solid electrolytic chip capacitor

Country Status (1)

Country Link
JP (1) JP2002110459A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004055699A (en) * 2002-07-18 2004-02-19 Nec Tokin Corp Solid electrolytic capacitor and its manufacturing method
DE102004042753A1 (en) * 2004-09-03 2006-03-30 Epcos Ag chip capacitor
JP2007184308A (en) * 2005-12-29 2007-07-19 Nichicon Corp Manufacturing method of chip-like solid electrolytic capacitor
KR100747920B1 (en) 2004-12-10 2007-08-08 엔이씨 도낀 가부시끼가이샤 Solid electrolytic capacitor with face-down terminals, manufacturing method of the same, and lead frame for use therein
US8062385B2 (en) 2008-02-12 2011-11-22 Kemet Electronics Corporation Solid electrolytic capacitor with improved volumetric efficiency method of making

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004055699A (en) * 2002-07-18 2004-02-19 Nec Tokin Corp Solid electrolytic capacitor and its manufacturing method
US7010838B2 (en) 2002-07-18 2006-03-14 Nec Tokin Corp. Thin surface mounted type solid electrolytic capacitor
DE102004042753A1 (en) * 2004-09-03 2006-03-30 Epcos Ag chip capacitor
KR100747920B1 (en) 2004-12-10 2007-08-08 엔이씨 도낀 가부시끼가이샤 Solid electrolytic capacitor with face-down terminals, manufacturing method of the same, and lead frame for use therein
JP2007184308A (en) * 2005-12-29 2007-07-19 Nichicon Corp Manufacturing method of chip-like solid electrolytic capacitor
JP4588630B2 (en) * 2005-12-29 2010-12-01 ニチコン株式会社 Manufacturing method of chip-shaped solid electrolytic capacitor
US8062385B2 (en) 2008-02-12 2011-11-22 Kemet Electronics Corporation Solid electrolytic capacitor with improved volumetric efficiency method of making

Similar Documents

Publication Publication Date Title
KR100826391B1 (en) Chip type solid electrolytic capacitor
JP4492265B2 (en) Chip type solid electrolytic capacitor
JP4479050B2 (en) Solid electrolytic capacitor
KR100610462B1 (en) Solid electrolytic capacitor, transmission-line device, method of producing the same, and composite electronic component using the same
JP2009099913A (en) Multi terminal type solid-state electrolytic capacitor
JP4810772B2 (en) Circuit module
JP3509733B2 (en) Electronic components
JP2009164168A (en) Interposer for capacitor
JP2002237431A (en) Solid-state electrolytic capacitor and method of manufacturing the same
JP4276774B2 (en) Chip-shaped solid electrolytic capacitor
JP2002110459A (en) Solid electrolytic chip capacitor
JP2002299161A (en) Composite electronic component
US7268408B2 (en) Wiring board, method for manufacturing wiring board and electronic component using wiring board
JP2002008944A (en) Chip-like capacitor
JP2007013043A (en) Electrode assembly for mounting electric element, electric component employing the same, and solid electrolytic capacitor
JP2002353073A (en) Circuit module
JPH0684716A (en) Manufacture of solid electrolytic capacitor
JP2004281716A (en) Chip-like solid electrolytic capacitor
JP2005158903A (en) Solid electrolytic capacitor
JP3149419B2 (en) Method for manufacturing solid electrolytic capacitor
JP2008021774A (en) Chip-type solid electrolytic capacitor, and manufacturing method thereof
JP2005311216A (en) Solid electrolytic capacitor and its manufacturing method
JP2003133176A (en) Thin solid electrolytic capacitor and manufacturing method therefor
JP2011176067A (en) Solid-state electrolytic capacitor
JP2738183B2 (en) Chip-shaped solid electrolytic capacitor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051114

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080522

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080602

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20081222