JP2010141083A - Method for manufacturing semiconductor device substrate, and method for manufacturing electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device substrate, suppressing contraction of a substrate generated in a production process of a semiconductor device substrate, reducing faults generated by one cause of displacement of pattern portions or the like to be formed, and suppressing increasing of manufacturing costs and lowering of productivity. <P>SOLUTION: In a process of forming a silicon oxide film, a silicon oxide film (241a) is formed on a glass substrate (210) by using a general film formation method such as a CVD method or the like. Here, film formation conditions in forming the silicon oxide film (241a) are adjusted so that a compressive stress in the silicon oxide film (241a) is 170 MPa or greater. Subsequently, in an annealing treatment process, an annealing treatment is carried out to the silicon oxide film (241a) under the temperature condition that a treatment temperature is set at a temperature of a distortion point of the glass substrate (210) or less, and at an annealing temperature of an activation temperature of a semiconductor layer to be formed on the glass substrate (210) or higher. In the present embodiment, the temperature of a distortion point of the glass substrate (210) is approximately 500°C. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a semiconductor device substrate manufacturing method for manufacturing a semiconductor device substrate on which a semiconductor element such as a TFT (Thin Film Transistor) is formed, and to a liquid crystal device or the like by applying such a manufacturing method. The present invention relates to a technical field of a method of manufacturing an electro-optical device capable of manufacturing the electro-optical device.

When manufacturing this type of semiconductor device substrate, a semiconductor element such as a TFT is formed using a base film formed on the substrate as a base. Patent Document 1 proposes a technique for suppressing the shrinkage of the substrate caused by heat treatment and increasing the yield of semiconductor elements.

JP 2001-342031 A

However, when a base film made of an insulating film is formed on a substrate and then a circuit portion including a semiconductor element or a pattern portion such as a wiring is formed thereon, heat treatment is performed when the base film is formed. The substrate shrinks due to the temperature rise due to the heat treatment. According to such shrinkage of the substrate, even if the position where the circuit portion and the pattern portion are formed is set with respect to the substrate before shrinkage, the circuit portion is shifted from the initially set position by the shrinkage. Etc. are formed. In addition, even if the formation position of the circuit unit or the like is newly set in a state where the substrate is contracted, the accuracy of setting the formation position of the circuit unit or the like does not catch up with the amount of contraction of the substrate, or the circuit unit or the like is formed. In some cases, variations in misalignment of the formation position of the circuit portion or the like cannot be corrected due to the mask used in the process, and it is difficult to accurately form the circuit portion or the pattern portion in the target region on the substrate. The following technical problem arises.

On the other hand, in a manufacturing process of an electro-optical device such as a liquid crystal device, when a pattern portion such as a light-shielding film is formed on one of a pair of substrates that sandwich a liquid crystal layer, the liquid crystal device is assembled, It is necessary to form a light shielding film in a predetermined region on one substrate in advance so that the light shielding film and the color filter provided on the other substrate do not overlap each other.

Here, even if a light-shielding film is formed in a region shifted from a predetermined region of one substrate, the light-shielding film and the color filter do not overlap each other when the pair of substrates are bonded to each other. Although it seems that the positioning between the pair of substrates may be performed with high accuracy, according to the positioning accuracy between the pair of substrates, it is technically difficult to correct the positional deviation of the light shielding film. In addition, even if the positional deviation of the light-shielding film can be corrected by the positioning accuracy between the pair of substrates, troubles required for the correction are generated.

In addition, when the substrate is annealed at a temperature equal to or higher than the strain point temperature of the substrate before the pattern portion is formed in order to suppress the shrinkage of the substrate that occurs after the pattern portion or the like is formed on the substrate. For example, a glass substrate needs to be annealed at a temperature of 600 ° C. or higher, which is a temperature higher than the strain point temperature of the substrate. Accordingly, a heat treatment apparatus capable of annealing at a high temperature is prepared, and the time required for raising the temperature in the manufacturing process of the substrate for a semiconductor device is extended. There arises a problem that leads to a decrease in the number.

Therefore, the present invention has been made in view of the above problems and the like. For example, the shrinkage of the substrate that may occur during the manufacturing process of the substrate for a semiconductor device is suppressed, and the positional deviation of the pattern portion to be formed is reduced. It is an object of the present invention to provide a method for manufacturing a substrate for a semiconductor device capable of reducing defects caused as a cause and suppressing an increase in manufacturing cost and a decrease in productivity, and a method for manufacturing an electro-optical device using the same. .

In order to solve the above problems, a method for manufacturing a substrate for a semiconductor device according to the present invention includes a first step of forming a silicon oxide film having a compressive stress of 170 MPa or more on a substrate, and a strain point temperature of the substrate or lower. And a second step of annealing the silicon oxide film under a temperature condition in which a processing temperature is set to an annealing temperature that is equal to or higher than an activation temperature of a semiconductor layer to be formed on the substrate. A third step of forming a pattern portion having a predetermined planar shape on the annealed silicon oxide film, and a compressive stress of 150 on the pattern portion.
A fourth step of forming a silicon nitride film that is equal to or higher than MPa, and the annealing temperature or lower;
And a fifth step of forming the semiconductor layer on the silicon nitride film under a temperature condition in which a processing temperature is set in a temperature range equal to or higher than the activation temperature.

According to the semiconductor device substrate manufacturing method of the present invention, in the first step, a silicon oxide film is formed on a substrate such as a glass substrate by using a general-purpose film forming method such as a CVD method. At this time, for example, various conditions such as a film formation condition of the silicon oxide film are adjusted so that the compressive stress in the silicon oxide film becomes 170 MPa or more.

In the second step, under a temperature condition in which a processing temperature is set to an annealing temperature that is equal to or lower than a strain point temperature of the substrate and is equal to or higher than an activation temperature of a semiconductor layer to be formed on the substrate, The silicon oxide film is annealed. Here, “the activation temperature of the semiconductor layer to be formed on the substrate” refers to the source region when doping an active layer of a semiconductor element such as a TFT formed on the substrate through a subsequent process. The temperature of the semiconductor layer is set so that the drain region can be formed by the doping. In addition, when using a glass substrate as a board | substrate, the strain point temperature of a board | substrate is about 500 degreeC.

In the third step, a pattern portion having a predetermined plane shape is formed on the annealed silicon oxide film. For example, the pattern portion is formed on a semiconductor layer formed in a later step.
It is a light-shielding film that shields the semiconductor layer so that incident light is not irradiated from the substrate side, or a wiring layer formed on the substrate.

In the fourth step, a silicon nitride film having a compressive stress of 150 MPa or more is formed on the pattern portion. The compressive stress in the silicon nitride film is set by adjusting film formation conditions when forming the silicon nitride film using a general-purpose film formation method such as a CVD method.

In the fifth step, the semiconductor layer is formed on the silicon nitride film under a temperature condition that is equal to or lower than the annealing temperature and a processing temperature set in a temperature range equal to or higher than the activation temperature. Here, the fifth step does not include only a step of forming a semiconductor layer on the silicon nitride film, but after forming the semiconductor layer, the semiconductor layer is doped with an impurity, so that the source region of the transistor and A series of steps until formation of regions to be the drain regions is included.

According to the method for manufacturing a substrate for a semiconductor device according to the present invention, the compressive stress in the silicon oxide film formed in the first process and the silicon oxide film in the second process becomes a base on which the pattern portion is formed. The set values of the annealing temperature to be applied and the compressive stress in the silicon nitride film formed on the pattern portion in the fourth step are set to mutually appropriate set values. More specifically, according to the semiconductor device manufacturing method of the present invention, the types of silicon oxide film and silicon nitride film formed as the base film and the interlayer insulating film on the substrate, respectively, and the compression acting on each of them. Compared with the case where the stress and the annealing temperature at which the silicon oxide film is annealed and the timing thereof are not set to appropriate set values, the size after the fifth step is based on the size of the substrate before the first step. The amount of change in the size of the substrate, in other words, the amount of shrinkage of the substrate based on the size of the substrate before the first step can be reduced.

Therefore, according to the method for manufacturing a substrate for a semiconductor device according to the present invention, it is possible to reduce a positional deviation in which the position of the pattern portion generated due to the contraction of the substrate deviates from the position based on the original design value.
Problems caused in the semiconductor device due to the misalignment can be reduced. More specifically, according to the method for manufacturing a semiconductor device according to the present invention, for example, when the pattern portion is a light shielding film, the semiconductor layer formed on the substrate is irradiated with light from the substrate side. Accordingly, it is possible to reduce malfunctions such as malfunction of the circuit portion due to light leakage current generated in the semiconductor layer. In addition, in the case where the pattern portion is a wiring portion, the semiconductor layer electrically connected to the wiring portion and a defect such as a connection failure that may occur due to the respective positions of the wiring portion being shifted from each other. Can be reduced. In addition, according to the method for manufacturing a substrate for a semiconductor device according to the present invention, not only the effect that the wiring part and the semiconductor layer can be electrically and reliably connected to each other, but also the wiring part and the same layer as the semiconductor layer, or Since each position with the circuit part including the conductive part provided in the upper layer can be accurately set as designed, so that the wiring part and the circuit part can be electrically connected,
It is also possible to form a contact portion between the wiring portion and the circuit portion.

Further, according to the method for manufacturing a substrate for a semiconductor device according to the present invention, each of the processing temperature for annealing the silicon oxide film and the processing temperature for forming the semiconductor layer on the silicon nitride film is determined on the substrate. It is possible to set the temperature below the strain point temperature. Therefore, according to the semiconductor device manufacturing method of the present invention, even if the processing temperature is not set to a temperature exceeding the strain point temperature of the substrate,
Since a silicon oxide film, a silicon nitride film, and a semiconductor layer can be formed and the amount of shrinkage of the substrate can be reduced, it is not necessary to prepare a heat treatment apparatus for performing an annealing process at a temperature higher than the strain point of the substrate. In addition, in the semiconductor device manufacturing process, it is not necessary to increase the processing temperature to a temperature equal to or higher than the strain point of the substrate, so that it is possible to reduce the time required to increase the processing temperature.

Therefore, according to the method for manufacturing a substrate for a semiconductor device according to the present invention, an increase in manufacturing cost required for a manufacturing apparatus used when manufacturing the substrate for a semiconductor device, and productivity when manufacturing a substrate for a semiconductor device are provided. Can be suppressed.

In order to solve the above problems, the method of manufacturing an electro-optical device according to the present invention includes a first step of forming a silicon oxide film having a compressive stress of 170 MPa or more on a substrate, and a strain point temperature of the substrate or lower. And a second step of subjecting the silicon oxide film to an annealing treatment under a temperature condition in which a treatment temperature is set to an annealing temperature that is a temperature equal to or higher than an activation temperature of a semiconductor layer to be formed on the substrate; A third step of forming a pattern portion having a predetermined planar shape on the annealed silicon oxide film; and a compressive stress of 150 MP on the pattern portion.
a fourth step of forming a silicon nitride film that is greater than or equal to a and an active layer of a pixel switching transistor under a temperature condition that is lower than the annealing temperature and a processing temperature is set in a temperature range equal to or higher than the activation temperature. And forming a semiconductor layer in the display region on the silicon nitride film.

According to the method for manufacturing an electro-optical device according to the present invention, an electro-optical device such as a liquid crystal device is manufactured through the first to fifth steps, similarly to the method for manufacturing a semiconductor device described above. According to the method for manufacturing an electro-optical device according to the invention, the semiconductor layer formed on the silicon nitride film is an active layer of a pixel switching transistor provided in a plurality of pixel regions constituting a display region on the silicon nitride film. It is.

According to the method for manufacturing an electro-optical device according to the present invention, as in the above-described method for manufacturing a semiconductor device, the position shift of the pattern portion caused by the contraction of the substrate deviates from the position based on the original design value. It is possible to reduce the problem that occurs in the electro-optical device due to the positional deviation. More specifically, for example, as in the above-described method for manufacturing a semiconductor device, a light leakage current generated in the semiconductor layer when the semiconductor layer that is an active layer of the pixel switching transistor is irradiated with light from the substrate side. Therefore, it is possible to manufacture an electro-optical device capable of displaying a high-quality image. In addition, in the case where the pattern portion is a wiring portion, the semiconductor layer electrically connected to the wiring portion and a defect such as a connection failure that may occur due to the respective positions of the wiring portion being shifted from each other. Can be reduced. In addition, according to the method of manufacturing the electro-optical device device according to the present invention, the wiring portion and the semiconductor layer are not limited to the effects that can be electrically and reliably connected to each other. Since each position with respect to the pixel portion including the conductive portion provided in the upper layer can be accurately set as designed, the wiring portion and the pixel portion can be electrically connected so that the wiring portion can be electrically connected. In addition, a contact portion can be formed between the pixel portions.

Further, according to the method of manufacturing the electro-optical device according to the present invention, each of the processing temperature for annealing the silicon oxide film and the processing temperature for forming the semiconductor layer on the silicon nitride film,
It is possible to set the temperature below the strain point temperature of the substrate. Therefore, according to the semiconductor device manufacturing method of the present invention, the silicon oxide film, the silicon nitride film, and the semiconductor layer can be formed without setting the processing temperature to a temperature exceeding the strain point temperature of the substrate, and Since the amount of shrinkage can be reduced, it is not necessary to prepare a heat treatment apparatus for performing an annealing process at a temperature higher than the strain point of the substrate. In addition, in the manufacturing process of the electro-optical device, it is not necessary to raise the processing temperature to a temperature equal to or higher than the strain point of the substrate, so that it is possible to shorten the time required to raise the processing temperature.

Therefore, according to the method for manufacturing an electro-optical device according to the present invention, an increase in manufacturing cost required for a manufacturing device used when manufacturing the electro-optical device and a decrease in productivity when manufacturing the electro-optical device are achieved. It can be suppressed.

Further, according to the method of manufacturing the electro-optical device according to the invention, after the fifth step, the counter substrate is disposed on the substrate so as to oppose the substrate via the electro-optical layer such as a liquid crystal layer. The electro-optical device is assembled. Here, when the pattern portion is a light shielding film that shields light applied to the semiconductor layer from the substrate side, the region where the light shielding film is formed on the substrate is:
This is a region that does not substantially contribute to image display. Therefore, the light shielding film should be formed so as to be shifted from the portion of the color filter provided on the counter substrate side that substantially overlaps the region contributing to image display.

However, when the position of the light-shielding film is shifted from the position based on the original design in accordance with the contraction of the substrate, the region that contributes substantially to the image display among the display regions on the substrate is narrowed.
The electro-optical device deteriorates display performance for displaying an image.

According to the method for manufacturing an electro-optical device according to the present invention, it is possible to reduce the amount of shrinkage of the substrate that occurs through the first to fifth steps. Therefore, a light shielding film that is an example of a pattern portion is as originally designed. In other words, the color filter provided on the counter substrate side is formed on the silicon oxide film so as to be shifted from a portion that substantially contributes to image display, thereby attaching a pair of substrates sandwiching the electro-optic layer. Without incurring the extra effort that occurs when matching,
The display performance of the electro-optical device can be improved.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

Hereinafter, embodiments of a method for manufacturing a substrate for a semiconductor device and a method for manufacturing an electro-optical device according to the present invention will be described with reference to the drawings.

<1: Manufacturing Method of Substrate for Semiconductor Device>
First, a method for manufacturing a semiconductor device substrate according to this embodiment will be described with reference to FIGS. 1 and 2 are process cross-sectional views sequentially showing main processes of the method for manufacturing a semiconductor device substrate according to the present embodiment. FIG. 3 is a list showing a list of various conditions of a sample that is an evaluation target of the evaluation performed by the present inventor. FIG. 4 is a graph showing the change in the amount of contraction of the substrate with respect to the position of the annealing furnace for each of the samples shown in FIG.

As shown in FIG. 1A, in a silicon oxide film forming process which is an example of the “first process” of the present invention, a general purpose method such as a CVD method is formed on a glass substrate 210 which is an example of the “substrate” of the present invention. The silicon oxide film 241a is formed by using this film forming method. At this time, the film forming conditions of the silicon oxide film 241a are adjusted so that the compressive stress of the silicon oxide film 241a is 170 MPa or more.

Next, as shown in FIG. 1B, in the annealing process which is an example of the “second process” of the present invention, the temperature is not higher than the strain point temperature of the glass substrate 210 and is formed on the glass substrate 210. The silicon oxide film 241a is annealed under a temperature condition in which the processing temperature is set to an annealing temperature that is equal to or higher than the activation temperature of the semiconductor layer to be processed. In the present embodiment, the strain point temperature of the glass substrate 210 is about 500 ° C. Therefore, the processing temperature at the time of annealing is set to 500 ° C. or lower. Here, the lower limit value of the processing temperature when the annealing process is performed is equal to or higher than the activation temperature of the semiconductor layer to be formed on the glass substrate 210. “Activation temperature of the semiconductor layer to be formed on the glass substrate 210” means an active layer of a semiconductor element such as a TFT formed on the glass substrate 210 through a later step (see FIG. 2E). The temperature of the semiconductor layer is set so that the source region and the drain region in the active layer can be formed by the doping when the impurity is doped.

Next, as shown in FIG. 1C, in the wiring portion forming process which is an example of the “third process” of the present invention, the silicon oxide film 241a is formed by annealing in the annealing process. On the silicon oxide film 241, the wiring part 211 which is an example of the “pattern part” of the present invention is formed. The wiring portion 211 is a semiconductor layer 201a (see FIG.
e) See. ) And a conductive layer patterned into a predetermined planar shape so as to constitute a circuit portion on the glass substrate 210. The wiring portion 211 includes a semiconductor layer 201 formed in a later process.
a (see FIG. 2E) may be formed as a light-shielding film that shields the semiconductor layer so that incident light is not irradiated from the glass substrate 210 side.

Next, as shown in FIG. 2D, in the silicon nitride film forming process as an example of the “fourth process” of the present invention, the silicon nitride film 24 having a compressive stress of 150 MPa or more on the wiring portion 211.
2 is formed. The compressive stress in the silicon nitride film 242 can be set by adjusting film formation conditions when forming the silicon nitride film 242 using a general-purpose film formation method such as a CVD method.

Next, as shown in FIG. 2E, in the active layer forming step which is an example of the “fifth step” of the present invention, the semiconductor layer is to be formed at a temperature lower than or equal to the annealing temperature in the annealing treatment step described above. The semiconductor layer 201a is formed on the silicon nitride film 242 under a temperature condition in which the processing temperature is set in a temperature range equal to or higher than the activation temperature of 201a. The semiconductor layer 201a is, for example, an amorphous silicon film. After the semiconductor layer 201a is formed, an insulating film 202 functioning as a gate insulating film is formed. A portion of the semiconductor layer 201a that overlaps with the gate electrode 203a2 is
It becomes a channel region of the TFT 230. After that, the source region 201s and the drain region 201d are formed in the semiconductor layer 201a by doping impurities into the semiconductor layer 201a from above the gate electrode 203a2 under temperature conditions equal to or higher than the activation temperature of the semiconductor layer 201a.
FT 230 is formed. Therefore, the semiconductor layer 201a constitutes an active layer of the TFT 230 formed on the glass substrate 210.

Next, as shown in FIG. 2F, the insulating film 202 and 243 are penetrated to form the source region 201.
Contact portions 281 and 283 electrically connected to the s and drain regions 201d, respectively.
By forming the circuit portion on the glass substrate 210, the semiconductor device substrate 20 is formed.
1 is manufactured. In the present embodiment, illustration of parts that can be constituent elements of circuit parts such as elements and wirings formed on the upper layer side of the contact parts 281 and 283 is omitted, but these constituent elements are the substrate for a semiconductor device. It may be formed on the insulating film 243 so as to constitute a necessary circuit portion according to the design of 201.

According to the method for manufacturing a substrate for a semiconductor device according to this embodiment including the above steps, the wiring portion 2
The silicon oxide film 2 is a base on which 11 is formed and is formed by a silicon oxide film process.
The compressive stress in 41a, the annealing treatment temperature applied to the silicon oxide film 241a in the annealing treatment, and the compressive stress in the silicon nitride film 242 formed on the wiring portion 211 in the silicon nitride film forming step, respectively. Are set to appropriate values. More specifically, according to the method for manufacturing a substrate for a semiconductor device according to the present embodiment, the types of insulating films formed as the base film and the interlayer insulating film on the glass substrate 210 and the compression acting on each of them. An active layer based on the size of the glass substrate 210 before the silicon oxide film process as compared with the stress and the annealing temperature at which the silicon oxide film is annealed and the timing thereof are not set to appropriate setting values. The amount of change in size of the glass substrate 210 after the forming process, in other words, the amount of shrinkage of the glass substrate 210 based on the size of the glass substrate 210 before the silicon oxide film forming process can be reduced.

Therefore, according to the method for manufacturing a substrate for a semiconductor device according to the present embodiment, the glass substrate 21
It is possible to reduce misalignment that occurs due to the contraction of 0 and the position of the wiring portion 211 deviates from the position based on the original design value, and it is possible to reduce problems caused in the semiconductor device 201 due to the misalignment. More specifically, according to the method for manufacturing a substrate for a semiconductor device according to the present embodiment, for example, when the wiring portion 211 is a light shielding film, the semiconductor layer 2 formed on the glass substrate 210.
Irradiation of light from 01a to the glass substrate 210 can reduce problems such as malfunction of the circuit portion due to light leakage current generated in the semiconductor layer 201a. In addition, it is possible to reduce problems such as poor connection that may occur when the positions of the semiconductor layer 201a electrically connected to the wiring portion 211 and the wiring portion 211 are shifted from each other.

In addition, according to the method for manufacturing a substrate for a semiconductor device according to the present embodiment, the wiring portion 211 and the semiconductor layer 201a are not limited to the effects that can be electrically and reliably connected to each other.
11 and the circuit portion including the conductive portion provided in the same layer as the semiconductor layer 201a or in the upper layer thereof can be accurately set as designed. Therefore, between the wiring portion 211 and the circuit portion, A contact portion can be formed between the wiring portion 211 and the circuit portion so that they can be electrically connected.

In addition, according to the method for manufacturing a semiconductor device substrate according to the present embodiment, the silicon oxide film 241.
Each of the processing temperature for annealing a and the processing temperature for forming the semiconductor layer 201 a on the silicon nitride film 242 can be set to a temperature equal to or lower than the strain point temperature of the glass substrate 210. Therefore, according to the semiconductor device substrate manufacturing method of the present embodiment, the glass substrate 2
The silicon oxide film 241, the silicon nitride film 242, and the semiconductor layer 201 a can be formed without setting the processing temperature to a temperature exceeding 10 strain point temperatures, and the glass substrate 210.
Therefore, it is not necessary to prepare a heat treatment apparatus for performing an annealing treatment at a temperature equal to or higher than the strain point of the glass substrate 210. In addition, in the manufacturing process of the semiconductor device substrate 201, the processing temperature does not have to be raised to a temperature equal to or higher than the strain point of the glass substrate 210. Therefore, it is possible to shorten the time required to raise the processing temperature. .

Therefore, according to the method for manufacturing a semiconductor device substrate according to the present embodiment, the semiconductor device substrate 2.
It is possible to suppress an increase in manufacturing cost required for a manufacturing apparatus used when manufacturing 01 and a decrease in productivity when manufacturing the semiconductor device substrate 201.

Next, with reference to FIG. 3 and FIG. 4, the inventor of the present application has performed in order to confirm that various specific conditions in the method for manufacturing a semiconductor device substrate according to the present embodiment are set to optimum values. A film structure specified by a compressive stress acting on each of the silicon oxide film 241a and the silicon nitride film 242 formed on the glass substrate 210 and a timing of annealing the silicon oxide film 241a, The evaluation result evaluated about the relationship with the board | substrate shrinkage amount of the glass substrate 210 is demonstrated.

As shown in FIG. 3, in this evaluation, the compressive stress acting on each of the silicon oxide film 241a and the silicon nitride film 242 formed on the glass substrate 210, and the silicon oxide film 24 are displayed.
The substrate shrinkage of the glass substrate 210 was measured for four samples (film structures 1 to 4 in the sample list of FIG. 3) that differ from each other in the timing of annealing treatment 1a. The substrate shrinkage amount of the glass substrate 210 is the substrate shrinkage amount generated when each sample passes through each of a plurality of positions (positions 0 to 22) in the annealing furnace for annealing the silicon oxide film 241a. It was measured. In this evaluation, the annealing temperature when annealing the silicon oxide film 241 a, that is, the processing temperature in the annealing furnace is 500 ° C. or less which is the strain point temperature of the glass substrate 210, and is on the glass substrate 210. Semiconductor layer 20 to be formed
The amount of shrinkage of the substrate is measured under a temperature condition unified to a temperature equal to or higher than the activation temperature of 1a.

As shown in FIG. 4, according to this evaluation, the film structure 4 has the smallest substrate shrinkage amount of the glass substrate 210 with respect to the position of the annealing furnace, and the variation with respect to the position in the furnace is also small. Therefore, according to this evaluation, after the silicon oxide film 241a is formed in a state where the compressive stress acting on the silicon oxide film 241a is 170 MPa or more and the compressive stress acting on the silicon nitride film 242 is 150 MPa or more, silicon oxide is formed. It was proved that the substrate shrinkage of the glass substrate 210 can be minimized by annealing the film 241a.

<2: Electro-optical device>
Next, the configuration of the liquid crystal device 1 which is an example of an electro-optical device that can be manufactured by the method of manufacturing the electro-optical device according to the present embodiment will be described with reference to FIGS.

<2-1: Overall configuration of electro-optical device>
The overall configuration of the liquid crystal device 1 manufactured by the method of manufacturing the electro-optical device according to the present embodiment will be described with reference to FIGS. FIG. 5 is a plan view of the liquid crystal device 1 manufactured by the method of manufacturing the electro-optical device according to this embodiment, and FIG. 6 is a cross-sectional view taken along the line VI-VI ′ of FIG.

1 and 2, in the liquid crystal device 1, a TFT array substrate 10 which is a glass substrate,
The counter substrate 20 is disposed to face the counter substrate 20. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are positioned around an image display region 10a that is a display region in which a plurality of pixel portions are provided. They are bonded to each other by a sealing material 52 provided in the sealing area.

The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and after being applied on the TFT array substrate 10 in the manufacturing process,
It is cured by heating or the like. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.

A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side. There is a peripheral area located around the image display area 10a. In other words, particularly in the present embodiment, when viewed from the center of the TFT array substrate 10, the distance from the frame light shielding film 53 is defined as the peripheral region.

A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, the image display area 10 is thus obtained.
In order to connect the two scanning line driving circuits 104 provided on both sides of a, the TFT array substrate 1
A plurality of wirings 105 are provided along one remaining side of 0 and so as to be covered with the frame light shielding film 53.

Vertical conductive members 106 functioning as vertical conductive terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. As a result, the TFT array substrate 1
Electrical conduction can be established between 0 and the counter substrate 20.

In FIG. 6, on the TFT array substrate 10, TFTs for pixel switching, scanning lines,
An alignment film is formed on the pixel electrode 9a after the wiring such as the data line is formed. On the other hand,
On the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed in the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

The data line driving circuit 1 is provided on the TFT array substrate 10 shown in FIGS.
01, a sampling circuit that samples the image signal on the image signal line and supplies it to the data line in addition to the driving circuit such as the scanning line driving circuit 104, and a precharge signal having a predetermined voltage level precedes the image signal to a plurality of data lines In addition, a precharge circuit to be supplied, an inspection circuit for inspecting quality, defects, and the like of the electro-optical device during manufacture or shipment may be formed.

<2-2: Configuration in Pixel Unit>
Next, the configuration of the pixel portion of the liquid crystal device 1 will be described in detail with reference to FIGS. FIG. 7 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms the image display region 10 a of the liquid crystal device 1. FIG. 8 is a plan view of a plurality of adjacent pixel portions of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. 9 is a cross-sectional view taken along the line IX-IX ′ of FIG. In FIG. 9, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

In FIG. 7, a pixel electrode 9 a and a TFT 30 are formed in each of a plurality of pixel areas arranged in a matrix that forms the image display area 10 a of the liquid crystal device 1. TFT30
Is electrically connected to the pixel electrode 9a and controls the switching of the pixel electrode 9a made of a transparent conductive film such as ITO when the liquid crystal device 1 operates. Data line 6 to which an image signal is supplied
a is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. May be.

The scanning line 3a is electrically connected to the gate of the TFT 30, and the liquid crystal device 1 sequentially applies the scanning signals G1, G2,..., Gm to the scanning line 3a in a pulse sequence in this order at a predetermined timing. It is comprised so that it may apply. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Supplied from the data line 6a is closed by closing the switch of the TFT 30 serving as a switching element for a certain period. Sn is written at a predetermined timing. A predetermined level of image signals S1, S2,..., Sn written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a is held for a certain period with the counter electrode formed on the counter substrate. The

The liquid crystal contained in the liquid crystal layer 50 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The transmittance with respect to light is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device 1 as a whole. The storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode in order to prevent the image signal from leaking.

Next, a specific configuration of the pixel portion will be described with reference to FIGS. In FIG. 8, on the TFT array substrate 10 of the liquid crystal device 1, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix in the X direction and the Y direction. A data line 6a and a scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a. T
Of the image display area 10a on the FT array substrate 10, the area where the opaque wiring such as the data lines 6a and the scanning lines 3a extending vertically and horizontally and the light shielding film shown in FIGS. 5 and 6 are formed is the image display area. 10a is a non-opening region where light is not substantially transmitted. The pixel switching TFT 30 is provided in each of the regions where the scanning line 3a and the data line 6a intersect each other.

Of the scanning line 3a, the portion of the semiconductor layer 1a that overlaps with the channel region 1c indicated by the diagonally upward slanting region in the semiconductor layer 1a is the gate electrode 3a2 of the TFT 30.

The data line 6a has a base film 4 formed using an insulating film 44 whose upper surface is planarized as a base.
The source region 1s of the TFT 30 is formed on the 4aa via the contact hole 81.
Is electrically connected. The data line 6a has a function of shielding the TFT 30 from light.
The inside of the data line 6a and the contact hole 81 is, for example, Al—Si—Cu, Al—Cu.
Al (aluminum) -containing material such as Al or a single layer of Al or a multilayer film of an Al layer and a TiN layer.

The storage capacitor 70 includes a dielectric layer 75 including a lower capacitor electrode 71 as a pixel potential side capacitor electrode connected to the drain region 1d and the pixel electrode 9a and a part of the upper capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. Lower capacitive electrode 71
Is formed on the insulating film 43.

As shown in FIGS. 8 and 9, the upper capacitor electrode 300 is provided on the upper side of the TFT 30 as an upper light shielding film (built-in light shielding film) containing, for example, a metal or an alloy. The upper capacitive electrode 300 is
It also functions as a fixed potential side capacitor electrode. The upper capacitor electrode 300 is, for example, Ti (titanium)
, Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), Pd
(Palladium), Al (comprising at least one of metals such as aluminum, a single metal, an alloy, a metal silicide, a polysilicide, a laminate of these, etc. The upper capacitor electrode 300 is made of, for example, conductive poly A multilayer structure in which a first film made of a silicon film or the like and a second film made of a metal silicide film containing a refractory metal or the like may be stacked.

The lower capacitor electrode 71 is, for example, a conductive polysilicon film or, for example, Ti, Cr, W, T
It consists of a single metal, an alloy, a metal silicide, a polysilicide, or a laminate of these, including at least one of metals such as a, Mo, Pd, and Al, and functions as a pixel potential side capacitor electrode. The lower capacitor electrode 71 has a function as a pixel potential side capacitor electrode that electrically relays between the pixel electrode 9 a and the drain region 1 d of the TFT 30, and also functions as an upper light shielding film that shields the TFT 30. Similarly to the upper capacitor electrode 300, the lower capacitor electrode 71 may be formed of a single layer film or a multilayer film containing a metal or an alloy.

The dielectric film 75 disposed between the lower capacitor electrode 71 as the capacitor electrode and the upper capacitor electrode 300 is, for example, an HTO (High Temperature Oxide) film or an LTO (Low Temperature Oxide).
) A silicon oxide film such as a film or a silicon nitride film.

The upper capacitor electrode 300 extends from the image display region 10a where the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential.

Below the TFT 30, the lower light shielding is provided on the TFT array substrate 10 in a grid pattern, separated from the TFT 30 through the insulating film 42 that is a silicon nitride film and with the insulating film 41 that is a silicon oxide film as a base. The film 11 is an example of the “pattern part” of the present invention, and shields the channel region 1c of the TFT 30 and its periphery from the return light incident on the TFT array substrate 10 into the device. The lower light-shielding film 11 is, for example, Ti, Cr, W, T, like the upper capacitor electrode 300.
It consists of a single metal, an alloy, a metal silicide, a polysilicide, a laminate of these, etc. containing at least one of refractory metals such as a, Mo and Pd.

In addition to the function of insulating the TFT 30 from the lower light-shielding film 11, the insulating layer 42 is formed on the entire surface of the TFT array substrate 10, thereby causing roughness during polishing of the surface of the TFT array substrate 10 and dirt remaining after cleaning. For example, the pixel switching TFT 30 has a function of preventing deterioration of characteristics.

As shown in FIGS. 8 and 9, the liquid crystal device 1 includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10.

A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. For example, the pixel electrode 9a
Is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film, and the alignment film 16 is made of an organic film such as a polyimide film.

The counter substrate 20 is provided with a counter electrode 21 over its entire surface, and below it,
An alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided. Counter electrode 21
Is made of a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

On the side of the counter substrate 20, the color filter 2 provided between the counter electrode 21 and the counter substrate 20.
6 is formed. The color filter 26 is accurately positioned so as to overlap the opening region 72a in each of the plurality of pixel regions constituting the image display region 10a, and the liquid crystal layer 5
Of the red light, green light, and blue light modulated by 0, the color light corresponding to the pixel portion is shown in FIG.
The light is transmitted on the counter substrate 20 inside. The TFT 30 is formed in the non-opening region 72b on the TFT array substrate 10.

The counter substrate 20 may be provided with a lattice-shaped or striped light-shielding film. By adopting such a configuration, the TF is combined with the upper light shielding film provided as the upper capacitor electrode 300.
It is possible to more reliably prevent the incident light from the T array substrate 10 side from entering the channel region 1c or its periphery.

TF configured as described above and arranged so that the pixel electrode 9a and the counter electrode 21 face each other.
A liquid crystal layer 50 is formed between the T array substrate 10 and the counter substrate 20. The liquid crystal layer 50 is
A predetermined alignment state is obtained by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

In FIG. 9, a pixel switching TFT 30 includes a gate electrode 3a2, a channel region 1c of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and a gate insulating film that insulates the scanning line 3a from the semiconductor layer 1a. Insulating film 2, source region 1s and drain region 1
d. The TFT 30 may have an LDD (Lightly Doped Drain) structure. According to the TF 30 having the LDD structure, the TFT 30 transistor can operate at high speed, and the display performance of the liquid crystal device 1 can be improved.

On the lower light shielding film 11, an insulating film 43 is formed in which a contact hole 81 leading to the source region 1s and a contact hole 83 leading to the drain region 1d are opened. According to the contact hole 83, it is possible to reliably supply the image signal to the pixel electrode 9a, and it is possible to display a high-quality image corresponding to the image signal by switching control of the pixel portion by the TFT 30.

A lower capacitor electrode 71 and an upper capacitor electrode 300 are formed on the insulating film 43, and an insulating film 44 in which contact holes 81 and 85 are respectively formed is formed thereon. An insulating film 45 formed on the insulating film 44 separates the data line 6a and the pixel electrode 9a from each other. The contact hole 85 penetrates the insulating films 44 and 45 and is electrically connected to the lower capacitor electrode 71.

<3: Manufacturing method of electro-optical device>
Next, a method for manufacturing the electro-optical device according to the present embodiment capable of manufacturing the above-described liquid crystal device 1 will be described with reference to FIGS. 10 and 11. 10 and 11 are process cross-sectional views sequentially showing main processes of the method for manufacturing the electro-optical device according to the present embodiment.

As shown in FIG. 10A, in the silicon oxide film forming process which is an example of the “first process” of the present invention, a CVD method or the like is formed on the TFT array substrate 10 which is an example of the “substrate” of the present invention. The insulating film 41a is formed using a general-purpose film forming method. At this time, the compressive stress in the insulating film 41a is 170M.
The film formation conditions of the insulating film 41a are adjusted so as to be at least Pa.

Next, as shown in FIG. 10B, in the annealing process which is an example of the “second process” of the present invention, the temperature is lower than the strain point temperature of the TFT array substrate 10, and on the TFT array substrate 10. The insulating film 41a is annealed under a temperature condition in which the processing temperature is set to an annealing temperature that is equal to or higher than the activation temperature of the semiconductor layer to be formed. In the present embodiment, the strain point temperature of the TFT array substrate 10 is about 500 ° C. Therefore, the processing temperature at the time of annealing is set to 500 ° C. or lower. Here, the lower limit value of the processing temperature when the annealing process is performed is equal to or higher than the activation temperature of the semiconductor layer to be formed on the TFT array substrate 10. “Activation temperature of the semiconductor layer to be formed on the TFT array substrate 10” refers to a later process (
Refer to FIG. ) Is set so that the source region and the drain region in the semiconductor layer 1a can be formed by the doping when the semiconductor layer 1a which is the active layer of the TFT 30 formed on the TFT array substrate 10 is doped with impurities. This is the temperature of the semiconductor layer 1a.

Next, as shown in FIG. 10C, in the light shielding film forming process which is an example of the “third process” of the present invention, the insulating film 41a is formed by annealing in the annealing process. On the insulating film 41, the light shielding film 11 which is an example of the “pattern part” of the present invention is formed.
The light shielding film 11 is a film part patterned in a predetermined planar shape so as to constitute a circuit part on the TFT array substrate 10 together with a semiconductor layer 1a (see FIG. 2E) formed in a later process. is there.

Next, as shown in FIG. 11D, in the silicon nitride film forming process which is an example of the “fourth process” of the present invention, the insulating film 42 having a compressive stress of 150 MPa or more is formed on the light shielding film 11. To do. The compressive stress in the insulating film 42 can be set by adjusting film forming conditions when the insulating film 42 is formed using a general-purpose film forming method such as a CVD method.

Next, as shown in FIG. 11E, in the active layer forming process which is an example of the “fifth process” of the present invention, the semiconductor layer which is equal to or lower than the annealing temperature in the annealing process described above and is to be formed. Under the temperature condition in which the processing temperature is set in the temperature range higher than the activation temperature of 1a, the insulating film 42
A semiconductor layer 1a is formed thereon. The semiconductor layer 1a is, for example, an amorphous silicon film. After forming the semiconductor layer 1a, the insulating film 2 functioning as a gate insulating film is formed. A portion of the semiconductor layer 1 a that overlaps the gate electrode 3 a 2 becomes a channel region 1 c of the TFT 30.
Subsequently, the source region 1s and the drain region 1d are formed in the semiconductor layer 1a by doping impurities into the semiconductor layer 1a from above the gate electrode 3a2 under a temperature condition equal to or higher than the activation temperature of the semiconductor layer 1a. After forming the TFT 30 among the components of the liquid crystal device 1
The liquid crystal device 1 is manufactured by sequentially forming the components formed above.

According to the method for manufacturing an electro-optical device according to the present embodiment including the above steps, in addition to the effects exhibited by the above-described method for manufacturing a substrate for a semiconductor device, the display performance of the liquid crystal device 1 can be improved. The effect becomes. More specifically, according to the manufacturing method of the electro-optical device according to the present embodiment, it is possible to reduce the substrate shrinkage amount of the TFT array substrate 10 generated through the silicon oxide film formation process or the active layer formation process. , According to the original design,
In other words, the color filter 26 provided on the counter substrate 20 side is formed on the silicon oxide film 41 so as to be substantially shifted from the portion that contributes to image display. Does not narrow the opening region through which the light passes. Therefore, by setting the position of the light shielding film 11 with respect to the color filter 26 as originally designed so that the portion of the color filter 26 overlapping the opening region and the light shielding film 11 do not overlap each other, the opening region is set. The display performance of the liquid crystal device 1 can be improved.

It is process sectional drawing (the 1) which showed the main process of the manufacturing method of the board | substrate for semiconductor devices which concerns on this embodiment in order. It is process sectional drawing (the 2) which showed the main process of the manufacturing method of the board | substrate for semiconductor devices which concerns on this embodiment in order. It is the list | surface which showed the list of the various conditions of the sample used as the evaluation object of evaluation which this inventor performed. It is the graph which showed the evaluation result of the evaluation which this inventor performed. 1 is a plan view showing an overall configuration of a liquid crystal device manufactured by a method for manufacturing an electro-optical device according to an embodiment. It is VI-VI 'sectional drawing of FIG. 3 is an equivalent circuit of various elements and wirings in a plurality of pixels formed in a matrix that forms an image display area of a liquid crystal device. FIG. 5 is a plan view of a plurality of adjacent pixel portions of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. It is IX-IX 'sectional drawing of FIG. FIG. 6 is a process cross-sectional view (part 1) illustrating the main processes of the method of manufacturing the electro-optical device according to the embodiment in order. FIG. 10 is a process cross-sectional view (part 2) illustrating the main processes of the method of manufacturing the electro-optical device according to the embodiment in order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 1a ... Semiconductor layer, 10 ... TFT array substrate, 11 ... Light-shielding film, 41, 42, 43, 44, 45 ... Insulating film, 201 ... Semiconductor device Substrate, 2
01a ... Semiconductor layer

Claims (2)

A first step of forming a silicon oxide film having a compressive stress of 170 MPa or more on the substrate;
The silicon oxide film is formed under a temperature condition in which a processing temperature is set to an annealing temperature that is equal to or lower than a strain point temperature of the substrate and is equal to or higher than an activation temperature of a semiconductor layer to be formed on the substrate. A second step of performing an annealing treatment;
A third step of forming a pattern portion having a predetermined planar shape on the annealed silicon oxide film;
A fourth step of forming a silicon nitride film having a compressive stress of 150 MPa or more on the pattern portion;
And a fifth step of forming the semiconductor layer on the silicon nitride film under a temperature condition that is lower than the annealing temperature and a processing temperature is set in a temperature range higher than the activation temperature. A method for manufacturing a semiconductor device substrate. A first step of forming a silicon oxide film having a compressive stress of 170 MPa or more on the substrate;
The silicon oxide film is formed under a temperature condition in which a processing temperature is set to an annealing temperature that is equal to or lower than a strain point temperature of the substrate and is equal to or higher than an activation temperature of a semiconductor layer to be formed on the substrate. A second step of performing an annealing treatment;
A third step of forming a pattern portion having a predetermined planar shape on the annealed silicon oxide film;
A fourth step of forming a silicon nitride film having a compressive stress of 150 MPa or more on the pattern portion;
The semiconductor layer serving as an active layer of the pixel switching transistor is formed in the display region on the silicon nitride film under a temperature condition that is lower than the annealing temperature and a processing temperature is set in a temperature range higher than the activation temperature. And a fifth step of forming the electro-optical device.

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