JP2010122556A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device that has a scanning electrode drive circuit having a function to perform simultaneous writing in an arbitrary sub-field and an arbitrary image display area by a relatively simple circuit configuration. <P>SOLUTION: A scanning pulse generating circuit includes shift registers 72a and 72b that have registers having the number equal to the N-number of a driving voltage waveforms and shift data of the registers; a selector 73 that selects one of the shift registers 72a and 72b; a latch 74 with an N-bit which holds an output from the shift register 72a or 72b selected by the selector 73 and generates the N-number of control pulses for generating a scanning pulse; and a switching section 78 that generates a scanning pulse on the basis of each of the N-number of control pulses. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other.

  A plurality of pairs of display electrodes, each consisting of a pair of scan electrodes and sustain electrodes, are formed in parallel on the front plate, and a plurality of parallel data electrodes are formed on the back plate. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  As a method for driving the panel, a subfield method is used in which one field is divided into a plurality of subfields and gradation display is performed by combining subfields that emit light. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In the address period, a scan pulse is sequentially applied to each of the scan electrodes and an address pulse is selectively applied to the data electrodes, so that an address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to the display electrode pairs, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light.

  In the above-mentioned subfield method, if the number of scan electrodes increases due to an increase in the screen size, resolution, etc., and the time required for the address period becomes longer, a sufficient sustain period for sustain discharge cannot be secured. There was a problem.

As one of the techniques for solving this problem, the write period is shortened by performing so-called simultaneous writing in which a scan pulse is simultaneously applied to a plurality of scan electrodes and a write pulse is selectively applied to data electrodes. A driving method that secures the maintenance time has been proposed (see, for example, Patent Document 1).
JP 2006-220902 A

  However, when simultaneous writing is performed in a specific subfield such as a subfield with a small luminance weight, a reduction in vertical resolution at the time of specific image display is recognized, and when simultaneous writing is performed in a specific image display area, a specific image is displayed. There has been a problem that a reduction in the vertical resolution of the display area is recognized and image display quality is deteriorated.

  In order to solve these problems, a scan electrode driving circuit having a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area in accordance with an image signal to be displayed is required.

  The present invention has been made in view of the above problems, and a plasma including a scan electrode driving circuit having a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area with a relatively simple circuit configuration. An object is to provide a display device.

  The present invention includes a panel having a plurality of N (N is a natural number of 2 or more) scan electrodes, and a scan pulse generating circuit that generates a scan pulse to be applied to each of the scan electrodes and outputs a plurality of N drive voltage waveforms. In the plasma display apparatus, the scan pulse generation circuit includes a plurality of shift register units that have a number of registers equal to the number N of drive voltage waveforms and shift data of the registers. A selector unit for selecting one, an N-bit latch unit for generating N control pulses for holding the output of the shift register unit selected by the selector unit and generating a scan pulse, And a switch section for generating a scanning pulse based on each of the switches. With this configuration, it is possible to provide a plasma display device including a scan electrode driving circuit having a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area with a relatively simple circuit configuration.

  Further, the scan pulse generating circuit of the plasma display device of the present invention is configured by using a plurality of integrated circuits having a plurality of n outputs (n is a natural number smaller than N), and each of the integrated circuits has a plurality of n registers. A plurality of shift register units for shifting the data of these registers are provided, a selector unit for selecting one from the plurality of shift register units, and an output of the shift register unit selected by the selector unit are generated to generate a scanning pulse. The configuration may include an n-bit latch unit that generates n control pulses and a switch unit that generates a scanning pulse based on each of the n control pulses. With this configuration, the circuit can be made compact and the mounting area can be reduced.

  According to another aspect of the present invention, there is provided a panel having a plurality of N (N is a natural number of 2 or more) scan electrodes, and a scan pulse generating circuit that generates a scan pulse to be applied to each of the scan electrodes and outputs a plurality of N drive voltage waveforms. The scan pulse generating circuit includes a shift register unit having a number of registers equal to the number N of drive voltage waveforms, and i (i = 2) of the shift register unit. 3,..., N) the N-th register data and (i−1) -th register data are operated and the result is output, and the output of the gate part is held. An N-bit latch unit for generating N control pulses for generating a scan pulse and a switch unit for generating a scan pulse based on each of the N control pulses are provided. To. Also with this configuration, it is possible to provide a plasma display device including a scan electrode driving circuit having a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area with a relatively simple circuit configuration.

  Further, the scan pulse generating circuit of the plasma display device of the present invention is configured by using a plurality of integrated circuits having a plurality of n outputs (n is a natural number smaller than N), and each of the integrated circuits has a plurality of n registers. The shift register unit that shifts the data of these registers, the i (i = 2, 3,..., N) th register data and the (i−1) th register data of the shift register unit are operated. An n-bit gate portion for outputting the result, an n-bit latch portion for generating n control pulses for holding the output of the gate portion and generating a scanning pulse, and each of the n control pulses It may be configured to include a switch unit that generates a scanning pulse based on the above. With this configuration, the circuit can be made compact and the mounting area can be reduced.

  According to the present invention, it is possible to provide a plasma display device having a scan electrode driving circuit having a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area with a relatively simple circuit configuration. It becomes.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in Embodiment 1 of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a discharge gas containing 10% xenon in a partial pressure ratio is enclosed. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the first exemplary embodiment of the present invention. In panel 10, N rows of scan electrodes SC1 to SCN (scan electrode 22 in FIG. 1) and N rows of sustain electrodes SU1 to SUN (sustain electrode 23 in FIG. 1) that are long in the row direction are arranged and long in the column direction. M rows of data electrodes D1 to DM (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to N) and sustain electrode SUi intersects one data electrode Dj (j = 1 to M), and the discharge cell is in the discharge space. M × N are formed. The number N of scan electrodes varies depending on the specifications of the panel 10, but for example, N = 768 for a high-vision type panel and N = 1080 for a full high-vision type panel.

  Next, the configuration and operation of the plasma display device in the present embodiment will be described.

  FIG. 3 is a circuit block diagram of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. The plasma display device 40 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 42 converts the image data into address pulses corresponding to the data electrodes D1 to DM, and applies them to the data electrodes D1 to DM.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit block. Although details will be described later, the timing generation circuit 45 controls the writing method (single writing or simultaneous writing) in the writing period.

  Scan electrode drive circuit 43 and sustain electrode drive circuit 44 create drive voltage waveforms based on the respective timing signals and apply them to scan electrodes SC1 to SCN and sustain electrodes SU1 to SUN.

  FIG. 4 is a circuit diagram showing details of scan electrode drive circuit 43 in the first embodiment of the present invention. Scan electrode driving circuit 43 includes scan pulse generating circuit 50, power source E50 of voltage Vsc superimposed on reference potential Vfl of scan pulse generating circuit 50, and voltage setting circuit 60 for setting reference potential Vfl to a predetermined voltage described later. And.

  Scan pulse generation circuit 50 includes a switch unit that generates a scan pulse to be applied to each of scan electrodes SC1 to SCN and a control circuit block thereof, and outputs a drive voltage waveform to each of scan electrodes SC1 to SCN. The switch unit includes switching elements QL1 to QLN and switching elements QH1 to QHN. Switching elements QL1 to QLN output a voltage on the low voltage side of power supply E50, that is, reference potential Vfl, and switching elements QH1 to QHN output a voltage on the high voltage side of power supply E50, that is, voltage Vsc superimposed on reference potential Vfl. FIG. 4 does not show control circuit blocks for switching elements QL1 to QLN and switching elements QH1 to QHN.

  The voltage setting circuit 60 includes a sustain pulse generator 62, a waveform generator 63, a waveform generator 64, and a clamp 65. Sustain pulse generator 62 generates a sustain pulse by outputting voltage Vsus or voltage 0 (V). The waveform generator 63 has a Miller integrating circuit connected to the power source of the voltage Vset, and generates a ramp waveform voltage that gradually increases toward the voltage Vset. The waveform generator 64 has a Miller integrating circuit connected to the power source of the negative voltage Vad, and generates a ramp waveform voltage that gently falls toward the voltage Vad. The clamp unit 65 clamps the reference potential Vfl of the scan pulse generation circuit 50 to the negative voltage Vad.

  Using the voltage setting circuit 60 configured as described above, the reference potential Vfl of the scan pulse generation circuit 50 is changed to a voltage Vad, a voltage Vsus, a voltage 0 (V), a rising ramp waveform voltage, a falling ramp waveform voltage, or the like. Can be set to voltage.

  Although not shown, a switching element for preventing a backflow of current, a diode for bypassing the current, and the like are provided as necessary.

  Next, a driving method for driving the panel 10 will be described. The panel 10 divides one field period into a plurality of subfields, and performs gradation display by a so-called subfield method in which light emission / non-light emission of each discharge cell is controlled for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In the address period, a scan pulse is applied to the scan electrode and an address pulse is selectively applied to the data electrode, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to the display electrode pairs, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light.

  FIG. 5 is a drive voltage waveform diagram applied to each electrode of panel 10 according to the first exemplary embodiment of the present invention, and shows drive voltage waveforms of two subfields.

  In the initialization period, voltage 0 (V) is first applied to data electrodes D1 to DM and sustain electrodes SU1 to SUN, respectively, in the first half. Then, using sustain pulse generating unit 62, reference potential Vfl is set to voltage 0 (V), switching elements QH1 to QHN of scan pulse generating circuit 50 are turned on, and voltage Vsc is applied to scan electrodes SC1 to SCN. Next, the waveform generator 63 is operated to apply a ramp waveform voltage that gradually increases toward the voltage Vset + Vsc to the scan electrodes SC1 to SCN. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCN, sustain electrodes SU1 to SUN, and data electrodes D1 to DM, and wall voltage is accumulated on each electrode. . Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 33 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.

  Next, in the second half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUN. Then, using sustain pulse generator 62, reference potential Vfl is set to voltage Vsus, switching elements QH1 to QHN are turned off, switching elements QL1 to QLN are turned on, and voltage Vsus is applied to scan electrodes SC1 to SCN. Thereafter, the waveform generator 63 is operated to apply a ramp waveform voltage that gently falls toward the voltage Vad to the scan electrodes SC1 to SCN. Then, a weak initializing discharge occurs again during this period, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  As the operation in the initialization period, as shown in the initialization period of the second subfield in FIG. 5, the second half of the initialization period, that is, the ramp waveform voltage that gradually falls is applied to the scan electrodes SC1 to SCN. It may be applied only to.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUN. Then, the reference potential Vfl is set to the negative voltage Vad using the clamp unit 65 and the switching elements QH1 to QHN are turned on to apply the voltage Vad + Vsc to the scan electrodes SC1 to SCN.

  Next, a scan pulse is applied to the scan electrode and an address pulse is selectively applied to the data electrode to selectively generate an address discharge in the discharge cells to form wall charges. Here, in the present embodiment, a scan pulse is not necessarily applied to each scan electrode SC1 to SCN for each scan electrode, but is applied to one scan electrode based on the control of the timing generation circuit 45. A scan pulse is applied, or a scan pulse is applied simultaneously to two scan electrodes. One example will be described below.

  First, for example, the switching element QH1 is turned off and the switching element QL1 is turned on, so that the scan pulse of the voltage Vad is applied to the scan electrode SC1 in the first row. Then, a positive address pulse voltage Vd is applied to the data electrode Dk (k = 1 to M) of the discharge cell that should emit light in the first row among the data electrodes D1 to DM. Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied. In this way, the write operation is selectively performed. Thereafter, switching element QH1 is turned on and switching element QL1 is turned off. This writing operation by applying a scanning pulse to one scanning electrode is referred to as “single writing”. The time required for the write operation during this period is hereinafter referred to as “write cycle”. The write cycle is 1.0 μs in this embodiment. However, it is desirable to set the address cycle optimally based on the discharge characteristics of the panel 10 and the like.

  Next, for example, switching element QH2 and switching element QH3 are turned off, switching element QL2 and switching element QL3 are turned on, and scan pulse voltage Vad is applied to scan electrode SC2 in the second row and scan electrode SC3 in the third row. Then, the address pulse voltage Vd is applied to the data electrodes Dk of the discharge cells that should emit light in the second and third rows of the data electrodes D1 to DM. Then, address discharge occurs selectively in the discharge cells in the second and third rows. Thereafter, switching element QH2 and switching element QH3 are turned on, and switching element QL2 and switching element QL3 are turned off. Such an address operation by simultaneously applying a scan pulse to a plurality of scan electrodes is referred to as “simultaneous writing”.

  When simultaneous writing is performed in this manner, the write operation for the two scan electrodes can be performed within the time of one write cycle, so that the time required for the write operation is reduced to ½. However, since the same address pulse is applied to the discharge cells sharing the data electrode Dk, the vertical resolution is lowered.

  Next, for example, switching element QH4 and switching element QH5 are turned off, switching element QL4 and switching element QL5 are turned on, and simultaneous writing is performed with scan electrode SC4 and scan electrode SC5. Thereafter, switching element QH4 and switching element QH5 are turned on, and switching element QL4 and switching element QL5 are turned off.

  Next, for example, the switching element QH6 is turned off and the switching element QL6 is turned on to perform single writing with the scan electrode SC6. Thereafter, switching element QH6 is turned on and switching element QL6 is turned off.

  Similarly, single writing is performed with scan electrode SCh (h = 1 to N), or simultaneous writing is performed with scan electrode SCh and scan electrode SCh + 1. The above address operation is performed up to the discharge cell in the Nth row.

  Thereafter, using sustain pulse generation unit 62, reference potential Vfl is set to voltage 0 (V), switching elements QL1 to QLN are turned on, and voltage 0 (V) is applied to scan electrodes SC1 to SCN.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrodes SU1 to SUN, and sustain pulse of voltage Vsus is applied to scan electrodes SC1 to SCN using sustain pulse generator 62. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred. Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCN, and a sustain pulse of voltage Vsus is applied to sustain electrodes SU1 to SUN. As a result, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred.

  Similarly, in the address period, the sustain electrodes of the number corresponding to the luminance weight are alternately applied to the scan electrodes SC1 to SCN and the sustain electrodes SU1 to SUN, and a potential difference is given between the electrodes of each display electrode pair. The sustain discharge is continuously performed in the discharge cell in which the address discharge has occurred.

  In the subsequent subfield and the subsequent subfields, operations similar to those described above are performed except for the number of sustain pulses, and thus description thereof is omitted.

  In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vset = 330 (V), voltage Vsus = 190 (V), voltage Vsc = 140 (V), voltage Vad = −180 (V). The voltage Ve1 = 160 (V), the voltage Ve2 = 170 (V), and the voltage Vd = 60 (V). However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device 40.

  As described above, in the present embodiment, a scan pulse is not necessarily applied to each scan electrode for each of scan electrodes SC1 to SCN, but a scan pulse is applied to each scan electrode. Apply a scan pulse to the two scan electrodes simultaneously.

  Next, details of the scan pulse generating circuit 50 that operates in this manner will be described. The scan pulse generation circuit 50 includes a switch unit and its control circuit block. As shown in FIG. 4, the switch unit includes switching elements QH1 to QHN and switching elements QL1 to QLN corresponding to scan electrodes SC1 to SCN. That is, switching element QH1, switching element QL1, and their control circuit block for scan electrode SC1, switching element QH2, switching element QL2, and their control circuit block for scan electrode SC2,. On the other hand, a switching element QHN, a switching element QLN, and a control circuit block thereof are provided.

  In this embodiment, the control circuit block of the switch unit includes a plurality of shift register units, a selector unit, a latch unit, and an output control unit.

  These N sets of switching elements QLi, QHi and their control circuit blocks are integrated into an integrated circuit by n sets. Hereinafter, this integrated circuit is referred to as a “scan IC”. In the present embodiment, n = 68 sets of switching elements and their control circuit blocks are combined into one scan IC, and 16 scan ICs having n = 68 outputs are used to form a scan pulse generation circuit 50. The scan pulse is supplied to each of N = 1080 scan electrodes SC1 to SC1080. In this way, by forming the scan pulse generating circuit 50 having a large number of outputs as an IC, the circuit can be made compact and the mounting area can be reduced.

  In the present embodiment, since scan pulse generation circuit 50 is composed of a plurality of scan ICs, the configuration of scan ICs that apply drive voltage waveforms to scan electrodes SC1 to SC68 will be described in detail. The configuration of the scan IC that applies the drive voltage waveform to scan electrodes SC69 to SC1080 is the same.

  FIG. 6 is a circuit block diagram showing details of the scan IC in the first embodiment of the present invention. Each of the scan ICs constituting the scan pulse generation circuit 50 includes a plurality of shift register units 72a and 72b, a selector unit 73, a latch unit 74, an output control unit 76, and a switch unit 78.

  Each of the shift register units 72a and 72b has a register with n outputs and shifts data in these registers. In the present embodiment, the shift register includes a 68-bit register in response to one scan IC generating scan pulses for 68 scan electrodes. The output of the shift register unit 72a is described as “Oa1, Oa2,..., Oa68” in order from the top, and the output of the shift register unit 72b is described as “Ob1, Ob2,.

  As will be described in detail later, one or two clocks CK1 are input to each clock input terminal of the shift register units 72a and 72b during one write cycle. The number of input clocks CK1 is controlled by a single write operation or a simultaneous write operation. The shift register unit 72a has a serial data input terminal DIa, and the shift register unit 72b has a serial data input terminal DIb.

  The selector unit 73 selects one from the plurality of shift register units 72a and 72b. In the present embodiment, based on the control signal SEL, either one of the outputs Oa1 to Oa68 of the shift register unit 72a or each of the outputs Ob1 to Ob68 of the shift register unit 72b is selected and “O1, O2,. .., O68 ". In the present embodiment, if the control signal SEL is at the “L” level, the outputs Oa1 to Oa68 of the shift register unit 72a are selected. If the control signal SEL is at the “H” level, the outputs Ob1 to Ob1 of the shift register unit 72b are selected. Select Ob68.

  The latch unit 74 holds the output of the shift register unit selected by the selector unit 73 and generates n control pulses for generating scan pulses. In this embodiment, it is a 68-bit latch that inputs the clock CK2 and latches the outputs “O1, O2,..., O68” of the selector unit 73. The clock CK2 is a clock having a cycle equal to the write cycle. Hereinafter, the 68-bit outputs of the latch unit 74 will be referred to as control pulses “L1, L2,..., L68”, respectively.

  The output control unit 76 inputs the two control signals OC1 and OC2 and the control pulse Li of the latch unit 74, and controls the switching elements QHi and QLi of the corresponding switch unit 78.

  The switch unit 78 generates a scanning pulse based on each of the control pulses. In the present embodiment, switching elements QH1 to QH68 that output a voltage on the high voltage side of power supply E50 and switching elements QL1 to QL68 that output a voltage on the low voltage side of power supply E50 are provided. Accordingly, the switching elements QH1 to QH68 and QL1 to QL68 are turned on / off to output one of the high impedance, the reference potential Vfl, and the voltage Vsc superimposed on the reference potential Vfl.

  FIG. 7 is a diagram illustrating the control of the output control unit 76 according to the first embodiment of the present invention, and the switching elements QH1 to QH1 of the switch unit 78 according to the two control signals OC1 and OC2 and the control pulses L1 to L68. QH68 and QL1 to QL68 are controlled as follows. When control signals OC1 and OC2 are both at "L" level, switching elements QH1 to QH68 and QL1 to QL68 are all turned off, and the output is set to a high impedance state. When the control signal OC1 is at the “L” level and the control signal OC2 is at the “H” level, the switching elements QHi and QLi are controlled according to the control pulse Li of the corresponding latch unit 74. In the present embodiment, if the i-th control pulse Li of the latch unit 74 is at “H” level, the switching element QHi is turned on, the switching element QLi is turned off, and the i-th control pulse Li of the latch unit 74 is “ If it is “L” level, the switching element QHi is turned off and the switching element QLi is turned on. When the control signal OC1 is “H” level and the control signal OC2 is “L” level, the switching elements QH1 to QH68 are turned off and the switching elements QL1 to QL68 are turned on regardless of the control pulse of the corresponding latch unit 74. A reference potential Vfl is output. When the control signals OC1 and OC2 are both at the “H” level, the switching elements QH1 to QH68 are turned on and the switching elements QL1 to QL68 are turned off regardless of the control pulse of the corresponding latch unit 74 to the reference potential Vfl. The superimposed voltage Vsc is output.

  Next, the operation of the scan pulse generation circuit 50 will be described. In the present embodiment, since scan pulse generation circuit 50 is composed of a plurality of scan ICs, the operation of scan ICs that apply drive voltage waveforms to scan electrodes SC1 to SC68 will be described in detail. The operation of the scan IC that applies the drive voltage waveform to scan electrodes SC69 to SC1080 is the same.

  FIG. 8 is a timing chart for explaining the operation of the scan IC according to the first embodiment of the present invention. In FIG. 8, the scan pulse is applied to the scan electrode SC1 in the first address period (time t1 to t3), and the scan pulse is simultaneously applied to the scan electrode SC2 and the scan electrode SC3 in the second address period (time t3 to t6). Are applied simultaneously to scan electrode SC4 and scan electrode SC5 in the third address period (time t6 to t9), and scan pulse is applied to scan electrode SC6 in the fourth address period (time t9 to t10). Is applied simultaneously to scan electrode SC7 and scan electrode SC8 in the fifth write cycle (time t10 to t11), and scan pulse is applied to scan electrode SC9 in the sixth write cycle (time t11 to t12). 4 shows a timing chart for an example in which the voltage is applied. Hereinafter, a description will be given in order along the timing chart.

  First, the input terminal DIa of the shift register unit 72a is set to the “L” level, the input terminal DIb of the shift register unit 72b is set to the “H” level, the clock CK1 is input at time t0, and then the input terminal DIa is set to the “H” level. The input terminal DIb is set to the “H” level and the clock CK1 is input at time t0 ′. In this way, the output “Oa1, Oa2, Oa3, Oa4, Oa5,..., Oa68” of the shift register unit 72a is changed to “L, H, H, H, H,. “Ob1, Ob2, Ob3, Ob4, Ob5,..., Ob68” is preset to “L, L, H, H, H,. In order to perform a single write in the first write cycle, the “L” level is input to the selector 73 as the control signal SEL, and the outputs Oa1 to Oa68 of the shift register 72a are selected and output. At time t1, the clock CK2 is input. Then, the control pulse L1 of the latch unit 74 becomes the “L” level, the control pulses L2 to L68 become the “H” level, and the scan pulse is applied to the scan electrode SC1 in the first address period.

  Next, CK1 is input at time t2. Then, the output of the shift register unit 72a becomes “H, L, H, H, H,..., H”, and the output of the shift register unit 72b becomes “H, L, L, H, H,. " In order to perform simultaneous writing in the second writing cycle, “H” level is input to the selector unit 73 as the control signal SEL, and the output of the shift register unit 72b is selected. At time t3, the clock CK2 is input. Then, the control pulse L2 and the output L3 of the latch unit 74 become “L” level, and the control pulses L1, L4 to L68 become “H” level, and the scan pulse is applied to the scan electrode SC2 and the scan electrode SC3 in the second address period. Is done. Thereafter, CK1 is input at time t4.

  Next, CK1 is input at time t5. Then, the output of the shift register 72a becomes “H, H, H, L, H, H,..., H”, and the output of the shift register 72b becomes “H, H, H, L, L, H,. .., H ". In order to perform simultaneous writing in the third writing cycle, “H” level is input as the control signal SEL to the selector unit 73, and the output of the shift register unit 72b is selected. At time t6, the clock CK2 is input. Then, the control pulse L4 and the output L5 of the latch unit 74 become the “L” level, and the control pulses L1 to L3 and L6 to L68 become the “H” level. Is applied. Thereafter, CK1 is input at time t7.

  Next, CK1 is input at time t8. Then, the output of the shift register unit 72a is “H, H, H, H, H, L, H, H,..., H”, and the output of the shift register unit 72b is “H, H, H, H, H”. , L, L, H,..., H ”. Since simultaneous writing is not performed in the fourth write cycle, “L” level is input to the selector unit 73 as the control signal SEL, and the output of the shift register unit 72a is selected. At time t9, the clock CK2 is input. Then, the control pulse L6 becomes “L” level, the control pulses L1 to L5 and L7 to L68 become “H” level, and the scan pulse is applied to the scan electrode SC6 in the sixth write cycle.

  Similarly, when performing single writing, one clock CK1 is input during the writing period to shift the shift register units 72a and 72b by one bit. Then, the control signal SEL of the selector unit 73 is set to the “L” level to select the output of the shift register unit 72a, the clock CK2 is input to the latch unit 74, and the output is latched.

  On the other hand, when the simultaneous writing is continued, one clock CK1 is input during the writing period to shift the shift register units 72a and 72b by one bit. Then, the control signal SEL of the selector unit 73 is set to “H” level to select the output of the shift register unit 72 b, the clock CK 2 is input to the latch unit 74, and the output is latched. After that, one clock CK1 is input to shift the shift register units 72a and 72b by one bit.

  By controlling the number of clocks CK1 input to the shift register units 72a and 72b and the control signal SEL of the selector unit 73 in this way, single writing or simultaneous writing is performed on any scan electrode in any subfield. It can be performed. Note that the timing at which the clock CK1 is input is not particularly limited as long as the circuit operates normally.

  Thus, in this embodiment, two shift register units 72a and 72b are provided, and the number of clocks CK1 input to the shift register units 72a and 72b and the control signal SEL of the selector unit 73 are controlled during the write cycle. Thus, either single writing or simultaneous writing can be performed on any scan electrode in any subfield.

  In this embodiment, in order to perform simultaneous writing with two adjacent scan electrodes, the output of the shift register unit 72a is changed to “L, H, H, H, H,. The output of the shift register 72b is preset to “L, L, H, H, H,... However, the present invention is not limited to this, and by the preset pattern of the output of the shift register unit 72b, simultaneous writing can be performed even with scan electrodes at distant positions, and more than two scan electrodes can be written. Can be written simultaneously.

  In the present embodiment, the configuration in which the two shift register units 72a and 72b are provided and the selector unit 73 selects one of the outputs from the two shift register units 72a and 72b has been described. It is not limited. There may be a configuration in which three or more shift register units are provided, and the selector unit selects an output of any of the plurality of shift register units.

  In the present embodiment, the case where the scan pulse generating circuit 50 is configured by using a plurality of scan ICs has been described in detail. Even when the scan pulse generation circuit has a configuration other than the above, the scan pulse generation circuit includes a plurality of shift register units that have a number of registers equal to the number N of drive voltage waveforms and shift the data of these registers. In addition, a selector unit for selecting one from a plurality of shift register units, and an N-bit latch for generating N control pulses for holding the output of the shift register unit selected by the selector unit and generating a scanning pulse The present invention can be applied by adopting a configuration including a switch section and a switch section that generates a scan pulse based on each of the N control pulses.

  In addition, as described in this embodiment, the circuit configuration can be simplified if only single writing or simultaneous writing with two adjacent scan electrodes is performed. The details will be described below as a second embodiment.

(Embodiment 2)
Scan pulse generation circuit 50 in the second embodiment includes a switch unit and a control circuit block thereof. As shown in FIG. 4, the switch unit includes switching elements QH1 to QHN and switching elements QL1 to QLN corresponding to scan electrodes SC1 to SCN. That is, switching element QH1, switching element QL1, and their control circuit block for scan electrode SC1, switching element QH2, switching element QL2, and their control circuit block for scan electrode SC2,. On the other hand, a switching element QHN, a switching element QLN, and a control circuit block thereof are provided.

  The control circuit block of the switch unit includes a shift register unit, a gate unit, a latch unit, and an output control unit.

  These N sets of switching elements QLi, QHi and their control circuit blocks are integrated into an integrated circuit by n sets. This integrated circuit is called a scan IC. In the present embodiment, n = 68 sets of switching elements and their control circuit blocks are combined into one scan IC, and 16 scan ICs having n = 68 outputs are used to form a scan pulse generation circuit 50. The scan pulse is supplied to each of N = 1080 scan electrodes SC1 to SC1080. In this way, by forming the scan pulse generating circuit 50 having a large number of outputs as an IC, the circuit can be made compact and the mounting area can be reduced.

  In the present embodiment, since scan pulse generation circuit 50 is composed of a plurality of scan ICs, the configuration of scan ICs that apply drive voltage waveforms to scan electrodes SC1 to SC68 will be described in detail. The configuration of the scan IC that applies the drive voltage waveform to scan electrodes SC69 to SC1080 is the same.

  FIG. 9 is a circuit block diagram showing details of the scan IC in the second embodiment of the present invention. The scan IC includes a shift register unit 72a, a gate unit 83, a latch unit 74, an output control unit 76, and a switch unit 78.

  Since the shift register unit 72a has the same configuration as the shift register unit 72a in the first embodiment, the same reference numerals are given and description thereof is omitted. The latch unit 74, the output control unit 76, and the switch unit 78 are the same as the latch unit 74, the output control unit 76, and the switch unit 78 in the first embodiment, respectively.

  The gate unit 83 calculates the data of the i (i = 2, 3,..., N) th register and the data of the (i−1) th register of the shift register unit 72a and outputs the result. . In the present embodiment, based on the control signal SEL, if the control signal SEL is at the “L” level, the outputs Oa1 to Oa68 of the shift register unit 72a are output as “O1, O2,. If the control signal SEL is “H” level, the logical product of the (i−1) -th output Oai−1 of the shift register unit 72a and the i-th output Oai of the shift register unit 72a is calculated, and the result is obtained as a gate unit. 83, i-th output Oi. However, the first output O1 of the shift register unit 72a is output as it is as the first output O1 of the gate unit 83.

  As described above, even when the scanning IC having the circuit configuration shown in FIG. 9 is used, the same operation as the timing chart shown in FIG. The reason is as follows.

  Consider a case where the i-th output Oai of the shift register unit 72a is at "L" level and the other outputs are at "H" level. In the scan IC of the second embodiment, if the control signal SEL is “L” level, the output of the gate unit 83 is equal to the output of the shift register unit 72a, and the i-th output Oai is “L” level. The output is “H” level. On the other hand, if the control signal SEL is at the “H” level, the output of the gate unit 83 is the “L” level for the i-th output Oi and the i + 1-th output Oi + 1, and the “H” level for the other outputs. In the first embodiment, when the control signal SEL is “L” level, the selector unit 73 selects the output of the shift register unit 72a, and when the control signal SEL is “H” level, the selector unit 73 shifts. The result is the same as when the output of the register unit 72b is selected.

  In this way, the circuit configuration can be simplified if only single writing or simultaneous writing with two adjacent scan electrodes is performed.

  In the present embodiment, the case where the scan pulse generation circuit 50 is configured using a plurality of scan ICs has been described in detail. Even if the scan pulse generating circuit has a configuration other than the above, the scan pulse generating circuit includes a shift register unit that has a number of registers equal to the number N of drive voltage waveforms, and shifts data in these registers. An N-bit gate unit that calculates data of the i (i = 2, 3,..., N) th register and (i−1) th register of the register unit and outputs the result; An N-bit latch unit that generates N control pulses for holding the output of the gate unit to generate a scan pulse and a switch unit that generates a scan pulse based on each of the N control pulses are provided. By adopting a configuration, the present invention can be applied.

  In the first and second embodiments of the present invention, the serial data input terminal is provided in the shift register unit and serial data is taken in to preset the shift register unit. However, the present invention is limited to this. It is not a thing. For example, a preset signal input terminal may be provided in the shift register unit, and the preset signal PR may be input at the beginning of the writing period to preset the shift register unit.

  The specific numerical values used in the first and second embodiments of the present invention are merely examples, and are appropriately set to optimum values in accordance with the panel characteristics, the specifications of the plasma display device, and the like. It is desirable to do.

  The present invention has a function capable of performing simultaneous writing in an arbitrary subfield and an arbitrary image display area with a relatively simple circuit configuration, and is useful as a plasma display device.

The exploded perspective view which shows the structure of the panel used for Embodiment 1 of this invention. Electrode arrangement diagram of panel used in Embodiment 1 of the present invention Circuit block diagram of plasma display device according to Embodiment 1 of the present invention The circuit diagram which shows the detail of the scanning electrode drive circuit in Embodiment 1 of this invention Drive voltage waveform diagram applied to each electrode of panel in embodiment 1 of the present invention FIG. 3 is a circuit block diagram showing details of the scan IC in the first embodiment of the present invention. The figure which shows control of the output control part in Embodiment 1 of this invention. Timing chart for explaining operation of scan IC in Embodiment 1 of the present invention The circuit block diagram which shows the detail of the scan IC in Embodiment 2 of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Scan pulse generation circuit 60 Voltage Setting circuit 62 Sustain pulse generation unit 63, 64 Waveform generation unit 65 Clamp unit 72a, 72b Shift register unit 73 Selector unit 74 Latch unit 76 Output control unit 78 Switch unit 83 Gate unit QH1 to QHN, QL1 to QLN Switching element

Claims (4)

A plasma display panel having a plurality of N (N is a natural number of 2 or more) scan electrodes, and a scan pulse generating circuit that generates a scan pulse to be applied to each of the scan electrodes and outputs a plurality of N drive voltage waveforms. A plasma display device,
The scan pulse generation circuit includes:
A plurality of shift register units having a number of registers equal to the number N of the drive voltage waveforms and shifting data of the registers;
A selector unit for selecting one of the shift register units;
An N-bit latch unit for generating N control pulses for holding the output of the shift register unit selected by the selector unit and generating the scan pulse;
A plasma display apparatus comprising: a switch unit that generates the scan pulse based on each of the N control pulses. The scan pulse generation circuit is configured using a plurality of integrated circuits having a plurality of n outputs (n is a natural number smaller than N),
Each of the integrated circuits
A plurality of shift registers that have a plurality of n registers and shift the data of these registers,
A selector unit for selecting one of the shift register units;
An n-bit latch unit for generating n control pulses for holding the output of the shift register unit selected by the selector unit and generating the scan pulse;
The plasma display apparatus according to claim 1, further comprising a switch unit that generates the scan pulse based on each of the n control pulses. A plasma display panel having a plurality of N (N is a natural number of 2 or more) scan electrodes, and a scan pulse generating circuit that generates a scan pulse to be applied to each of the scan electrodes and outputs a plurality of N drive voltage waveforms. A plasma display device,
The scan pulse generation circuit includes:
A shift register unit having a number of registers equal to the number N of the drive voltage waveforms, and shifting data of the registers;
An N-bit gate unit for calculating the data of the i (i = 2, 3,..., N) th register and the data of the (i-1) th register and outputting the result. When,
An N-bit latch for generating N control pulses for holding the output of the gate and generating the scan pulse;
A plasma display apparatus comprising: a switch unit that generates the scan pulse based on each of the N control pulses. The scan pulse generation circuit is configured using a plurality of integrated circuits having a plurality of n outputs (n is a natural number smaller than N),
Each of the integrated circuits
A shift register unit having a plurality of n registers and shifting data of the registers;
An n-bit gate unit for calculating the data of the i (i = 2, 3,..., N) th register and the data of the (i-1) th register and outputting the result of the shift register unit. When,
An n-bit latch unit for generating n control pulses for holding the output of the gate unit and generating the scan pulse;
4. The plasma display apparatus according to claim 3, further comprising a switch unit that generates the scan pulse based on each of the n control pulses.

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