KR100647709B1 - Apparatus of driving plasma display panel - Google Patents

Abstract

A driving device of a display panel is provided to restrict scanning malfunction by operating a scan driving IC(Integrated Circuit) by dummy clocks without inputting driving data, during the periods of the clocks over the number of scan lines before starting a first subfield after initial starting of the display panel. A driving device(3) of a display panel having discharge cells formed in regions where X and Y electrode lines(X1~X3,Y1~Y3) and address electrode lines(AR1,AG1,AB1) cross each other includes a control unit(31) generating a scan data signal, a reset/sustain data signal, an address data signal, and an X data signal by processing image data input from the outside; a reset/sustain circuit unit(34) applying a reset/sustain driving signal corresponding to the reset and sustain data signals, to the Y electrode lines; an address driving unit(32) applying an address driving signal corresponding to the address data signal, to the address electrode lines; an X driving unit(33) applying a common driving signal corresponding to the X data signal, to the X electrode lines; and a scan driving unit(35) applying a scan driving signal corresponding to the scan data signal, to the Y electrode lines according to a clock signal. The scan driving unit is driven while restricting the scan driving signal from being generated more than the number of the clocks corresponding to the number of the Y electrode lines, right before a first subfield in an initial starting step.

Description

Apparatus of driving plasma display panel

1 is a perspective view showing an internal structure of a three-electrode surface discharge plasma display panel to which a driving device of a display panel according to the present invention is applied.

2 is a timing diagram illustrating a method of driving a plasma display panel in which a unit frame is configured by driving a plurality of subfields.

3 is a timing diagram illustrating driving signals applied to respective electrode lines with respect to a subfield as a driving method of a plasma display panel driving apparatus according to the present invention.

4 is a block diagram showing a driving apparatus of a plasma display panel as a preferred embodiment of the present invention.

FIG. 5 is a block diagram schematically illustrating an embodiment of a scan driving IC included in a scan driver of the driving apparatus of the plasma display panel of FIG. 4.

6 is a block diagram schematically illustrating a plurality of scan driver ICs of FIG. 5 connected in series as a preferred embodiment of the present invention.

7 is a timing diagram of pulse signals applied to Y electrode lines in an address period by a scan driver of a driving apparatus of a plasma display panel according to the present invention.

<Explanation of symbols for main parts of the drawings>

1: plasma display panel,

3: driving device of plasma display panel,

31: control unit, 32: address driver,

33: X driver, 34: reset / hold circuit,

35: scan driver, 4: scan driver IC,

42: shift register, 43: latch,

45: logic control unit.

The present invention relates to a driving device of a display panel, and more particularly, to select a discharge cell to be displayed by a sequential scan operation of each scan electrode, and to enable sustain discharge to occur only in the selected discharge cell, It relates to a driving device of the display panel for driving the.

As flat panel display devices, plasma display panels (PDPs), which are easy to manufacture large panels, have attracted attention. A plasma display panel is a display device that displays an image by using a discharge phenomenon. In general, a plasma display panel can be classified into a direct current type and an alternating current type according to the type of driving voltage. Due to the disadvantages, a lot of development of the AC plasma display panel.

An AC plasma display panel includes a three-electrode AC surface discharge type plasma display panel having three electrodes and driven by an AC voltage. A typical three-electrode surface discharge type plasma display panel is composed of a multi-layered plate, which is spatially advantageous because it can provide a thinner, lighter, and wider screen than a conventional cathode ray tube (CRT).

The plasma display panel includes a plurality of display cells formed in a region where the sustain electrode and the address electrode cross each other, and one display cell includes three discharge cells (red, green, and blue), and discharges the discharge cells. The gray level of the image is expressed by adjusting the state.

In order to express the gray scale of the plasma display panel, one frame applied to the plasma display panel may be configured with eight subfields having different emission counts to express 256 gray scales. That is, in the case where the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. There is a reset period, an address period, and a sustain discharge period in each of the sub-fields to drive the plasma display panel.

In the reset cycle, all discharge cells are initialized. In the next address period, scan pulses are sequentially applied to each of the Y electrodes, and data pulses synchronized with the scan pulses are applied to the address electrodes corresponding to the discharge cells to be displayed among the discharge cells, thereby displaying the discharges. Select the cell. In the subsequent sustain discharge cycle, sustain pulses are applied to the X electrode and the Y electrode so that the sustain discharge can occur only in the discharge cells to be displayed, thereby expressing the image.

In a conventional plasma display panel driving apparatus, a scan driving IC (Integrated Circuit) is used to sequentially apply scan pulses to the respective sustain electrode lines in the address period. In addition, an initial startup time for charging the respective power supplies and charging the gate voltage of the switches is required at the initial startup of the plasma display panel.

However, due to such unwanted noise generated during the initial startup time, incorrect data may be input to the scan driver IC to cause a scan malfunction in the scan period of the address period of the first subfield after the panel is started. In addition, there is a problem that the scan driver IC is burned out or an unintended image is output.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the scan driving IC is operated by a dummy clock greater than or equal to the scan player just before the start of the first subfield after the initial startup of the display panel, thereby preventing a scan malfunction due to incorrect data. An object of the present invention is to provide a driving device for a display panel.

The display panel driving apparatus according to the present invention for achieving the above object is to drive a display panel in which discharge cells are formed in an area where the X electrode, the Y electrode lines and the address electrode lines intersect. A controller which processes the image data to generate a scan data signal, a reset / hold data signal, an address data signal, and an X data signal; A reset / maintenance circuit unit for applying a reset / maintenance driving signal according to the reset and sustain data signals to the Y electrode lines; An address driver for applying an address driving signal corresponding to the address data signal to the address electrode lines; An X driver configured to apply a common driving signal according to the X data signal to X electrode lines; And applying a scan driving signal according to the scan data signal to the Y electrode lines according to a clock signal, wherein the scan driving signal is equal to or greater than the number of clocks corresponding to the number of the Y electrode lines immediately before the first subfield at initial startup. And a scan driver that is driven while not being generated.

Preferably, the scan data signal includes a data signal and a clock signal, and the scan driver includes a shift register configured to shift and output the data signal in synchronization with the clock signal.

The scan data signal includes a data signal, an output enable signal, and a clock signal, and the scan driver temporarily stores an output of the shift register to enable an output according to an output enable signal input from the controller. It is preferable to further include a latch.

The scan data signal includes a data signal, an output enable signal, and a clock signal, and a scan driver IC temporarily shifts and outputs the data signal in synchronization with the clock signal, and temporarily outputs the shift register. And a latch configured to enable an output according to an output enable signal input from the controller, wherein the scan driver is formed by serial connection of at least one scan driver IC.

Preferably, the scan driver includes a first scan driver IC that receives the data signal from the controller, and a second scan driver IC that receives a data signal from the first scan driver IC.

Preferably, the shift register outputs the data signal to the next scan driver IC connected in series when the data signal is shifted to the last bit.

According to another aspect of the present invention, a display panel driving apparatus sequentially applies a scan pulse to the scan electrode lines with respect to a display panel in which discharge cells are formed in an area where scan electrode lines and address electrode lines cross each other. Shifts for selecting discharge cells to be displayed by applying address pulses to the address electrode lines forming discharge cells to be displayed with respect to the scan pulses, and shifting and outputting data signals for scan driving in synchronization with a clock signal Driven by a scan driver having a register, a latch for temporarily storing and outputting the output of the shift register, and a power output unit for outputting the scan pulse in accordance with the output of the latch, wherein the scan driver is initially operated at initial startup. The number of scan electrode lines immediately before a subfield More than the number of clocks being characterized in that the drive, while the scan pulse is not to be generated.

According to the present invention, immediately before the start of the first subfield after the initial startup of the display panel, the scan driving IC is operated by a dummy clock equal to or greater than the scanning line, thereby preventing scan malfunction due to erroneous data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the surface discharge plasma display panel 1, the address electrode lines A _{R1 to} A _Bm , the dielectric layers 11 and 15, and the Y electrode line (Y ₁ to Y _n ), X electrode lines (X ₁ to X _n ), fluorescent layer 16, partition wall 17, and magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _{R1 to} A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _{R1 to} A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _{R1 to} A _Bm . The partition walls 17 function to partition the discharge area of each discharge cell 14 and to prevent optical cross talk between the discharge cells 14. The fluorescent layer 16 is formed on the inner surface of the space formed between the lower dielectric layer 15 and the partition walls 17 formed on the rear glass substrate 13.

The X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n have a constant pattern on the rear side of the front glass substrate 10 to be orthogonal to the address electrode lines A _{R1 to} A _Bm . Is formed. Each intersection sets a corresponding discharge cell 14. Each X electrode line (X _{1 to} X _n ) and each Y electrode line (Y _{1 to} Y _n ) are combined with a transparent electrode line made of a transparent conductive material such as indium tin oxide (ITO) and a metal electrode line for increasing conductivity. Is formed. Here, the X electrode lines X ₁ to X _n become sustain electrodes in the respective discharge cells 14, and the Y electrode lines Y ₁ to Y _n correspond to scan electrodes in the respective discharge cells 14. And become an address electrode in the discharge cell 14 of each of the address electrode lines A _{R1 to} A _Bm .

In this case, it is preferable that the scan electrodes are sequentially applied with scan pulses to select the discharge cells to be displayed on the Y electrode lines.

2 is a timing diagram illustrating a method of driving a plasma display panel in which a unit frame is configured by driving a plurality of subfields.

Referring to the drawing, the unit frame FR is divided into eight subfields SF1 to SF8 to realize time division gray scale display. Each subfield SF1 to SF8 is divided into reset periods R1 to R8, address periods A1 to A8, and sustain discharge periods S1 to S8.

The luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1 to S8 occupied in the unit frame. The length of the sustain discharge cycles S1 to S8 in the unit frame is 255T (T is the unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any of the subfields.

3 is a timing diagram illustrating driving signals applied to respective electrode lines with respect to a subfield as a driving method of a display panel driving apparatus according to the present invention.

In FIG. 3, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 to A _Bm of FIG. 1), and S _{X1 ..Xn} denotes X electrode lines (X ₁ to X of FIG. 1). _n ), and S _Y1 to S _Yn indicate a drive signal applied to each Y electrode line (Y ₁ to Y _{n in} FIG. 1).

Referring to the drawings, in the reset period PR of the unit sub-field SF, first, the voltage applied to the X electrode lines X ₁ to X _n is converted from the ground voltage V _G to the second voltage V _S. For example, it continuously increases to 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ to Y _n and the address electrode lines A _R1 to A _Bm . Accordingly, between the X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n , and the X electrode lines X ₁ to X _n and the address electrode lines A ₁ to A _A weak discharge occurs between _m ) and negative wall charges are formed around the X electrode lines X ₁ to X _n .

The Next, Y electrode lines (Y ₁ ~ Y _n) voltage to the second voltage applied to the (V _S), for example, the third voltage (V _SET than the second voltage (V _S) from 155 volt (V) The maximum voltage (V _SET + V _S ), which is as high as), continues to rise to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ to X _n and the address electrode lines A _R1 to A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n , while the Y electrode lines Y ₁ to Y _n and the address electrode lines are formed. Weak discharge occurs between (A _R1 and A _Bm ).

Next, while the voltage applied to the X electrode lines X ₁ to X _n is maintained at the second voltage V _S , the voltage applied to the Y electrode lines Y ₁ to Y _n is second. It continues to fall from voltage V _S to ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 to A _Bm .

Leads in the address period (PA), the address is applied to a display data signal of the address pulse to the electrode line, the second voltage (V _S) lower fourth voltage (V _SCAN) to bias the Y-electrode line than the (Y ₁ As the scan signals of the scan pulses of the ground voltage V _G are sequentially applied to ˜Y _n ), smooth addressing may be performed.

At this time, the display data signal applied to each of the address electrode lines A _R1 to A _{Bm is} supplied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. In addition, the second voltage V _S is applied to the X electrode lines X ₁ to X _{n for} more accurate and efficient address discharge.

In the sustain discharge period PS, the display sustain pulse of the second voltage V _S is alternately applied to all the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n . In the corresponding address period PA, a discharge for maintaining the display occurs in discharge cells in which wall charges are formed.

4 is a block diagram showing a driving apparatus of a plasma display panel as a preferred embodiment of the present invention. FIG. 5 is a block diagram schematically illustrating an embodiment of a scan driving IC included in a scan driver of the driving apparatus of the plasma display panel of FIG. 4. 6 is a block diagram schematically illustrating a plurality of scan driver ICs of FIG. 5 connected in series as a preferred embodiment of the present invention.

Referring to the drawings, the driving device 3 of the plasma display panel displays a screen on the plasma display panel 1, and the controller 31, the address driver 32, the X driver 33, and the reset / hold The circuit unit 34 and the scan driver 35 are provided.

The controller 31 processes image data input from the outside, and generates a scan data signal, a reset / hold data signal, an address data signal, and an X data signal. The address driver 32 applies an address driving signal corresponding to the address data signal to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm .

The X driver 33 applies an X driving signal corresponding to the X data signal to the X electrode lines X ₁ ,..., X _n . In addition, the reset / hold circuit unit 34 applies a reset / maintenance driving signal corresponding to the reset and sustain data signals to the Y electrode lines Y ₁ ,..., Y _n .

That is, the scan driver 35 applies a scan driving signal according to the scan data signal to the Y electrode lines Y ₁ ,..., Y _n in accordance with a clock signal. The scan driving signal is driven not to be generated more than the number of clocks corresponding to the number n of the Y electrode lines immediately before.

In this case, the X driver 33 applying the voltage (V _S of FIG. 3) to the X electrode lines may apply the voltage to all X electrodes in common, as shown in the drawing. The voltages (V _S of FIG. 3) applied to the X electrode lines may be applied separately without being common.

In the driving by the driving apparatus of the plasma display panel according to the present invention, the unit driving period is composed of a reset period, an address period, and a sustain period. In selecting the discharge cells to be displayed in the address section, a scan pulse (V _G ) is sequentially applied to the Y electrode lines while the Y electrode line is biased to a predetermined voltage (V _{SCAN in} FIG. 3), Voltage pulses (V _A of FIG. 3) are applied to address electrode lines corresponding to cells to be displayed of each Y electrode line.

In this case, the scan data signal for sequentially applying a scan pulse to the Y electrode lines may include a data signal, an output enable signal, and a clock signal.

The scan driver 35 may include at least one scan driver IC 4 connected in series. Each of the scan driver ICs 4 includes a shift register 42, a latch 43, and a logic controller 45. ), And at least one power output unit OUT1, ..., OUT65.

The shift register 42 is initialized according to the initialization signal, shifts the data signal to the latch 43 in synchronization with the clock signal, and the latch 43 outputs the shift register 42. The data is temporarily stored to enable the output according to the output enable signal input from the controller 31 to enable the output.

The scan driver IC 4 includes a clock signal input unit CLK, a data signal input unit SIN, an output enable signal input unit STB, a data signal output unit SOUT, a power output unit OUT1, ... , OUT65 may be further provided, and each input / output unit preferably includes input / output pins having respective functions.

The clock signal input unit CLK receives a clock signal from the control unit 31, and the data signal input unit SIN receives a data signal from the control unit 31 or a previous scan driver integrated circuit. The enable signal input unit STB receives an output enable signal from the controller 31, and the data signal output unit SOUT outputs a data signal to the next scan driver integrated circuit when the data signal is shifted to the last bit. The power output units OUT1, ..., OUT65 apply a power pulse to the Y electrode line according to the output of the shift register 42 to drive the Y electrode line.

The scan driver integrated circuit 4 is preferably configured to include all the logic circuits and power circuits necessary for driving the Y electrode lines of the plasma display panel.

In addition, for the various operations of the scan driver integrated circuit, a predetermined power supply unit VCC, VSSSUB, VSSP, VSSLOG, VPP is provided in the scan driver integrated circuit, and a terminal SEL for selecting the number of power outputs. A terminal F / R for selecting a shift direction of the shift register 42, a terminal BLK for blanking control of a power output, and high impedance control of a power output. The terminal HIZ may be provided.

In addition, a predetermined logic control section 45 for power output represented by logic gates in the drawing is preferably provided.

In this case, V _CC is a voltage supply terminal for the logic controller 45 of 5V, V _PP is a high voltage supply terminal for power output, V _SSP is a ground terminal for power output, and V _SSLOG is a logic controller. Is the ground terminal for 45, and V _SSSUB is the ground terminal for the substrate.

The terminal SEL for selecting the number of power outputs selects the number of power outputs by the shift register 42. In the present embodiment, one of 64 and 65 can be selected. In this case, the terminal F / R for selecting the shift direction of the shift register and the terminal SEL for selecting the number of the power outputs are connected to the shift register through a switch SWITCH.

In this case, the scan driver 35 may be formed by sequentially connecting at least one or more of the scan driving ICs A, B, C, and D as shown in FIG. 6. In this embodiment, since one scan driver integrated circuit can have 64 power output terminals, and one power output terminal applies scan voltage pulses to one Y electrode line, the plasma display all have 256 Y electrode lines. In the case of the panel 1, four scan driver ICs A, B, C, and D may be connected to form one scan driver 35.

In addition, the scan driver 35 may be formed by connecting at least two scan driver ICs in series. In this case, the scan driver integrated into the initialization signal output unit 44 of the scan driver integrated circuit 4 may be integrated into the next scan driver. The signal line may be connected to the initialization signal input unit 41 of the circuit. Therefore, the signal is easier to maintain its value than one signal line is long input to the plurality of scan driver integrated circuits.

The clock signal input unit CLK, the data signal input unit SIN, the data signal output unit SOUT, and the outputtable signal input unit STB each have signals generated by a Schmidt trigger circuit. A clean square wave can be input and output to the shift register 42 or the latch 43.

In this case, the shifted data is transferred from the shift register to the latch and temporarily stored, so that the latch 43 is enabled by a strobe signal input through the output enable signal input unit STB. When the shifted data is output from the latch, a scan pulse voltage is output to the corresponding Y electrode line.

7 is a timing diagram of pulse signals applied to Y electrode lines in an address period by a scan driver of a driving apparatus of a plasma display panel according to the present invention.

Referring to the drawing, the scan driver is driven while the scan drive signal is not generated more than the number of clocks corresponding to the number of the Y electrode lines immediately before the first subfield at the initial startup. That is, the scan driving IC is operated while the power for the scan driving is not applied for the clock number t1,..., Tn over the number n of the Y electrode lines.

That is, the scan driving IC is operated by the dummy clock immediately before the first subfield at the initial startup, so that erroneous data remaining after the initialization period of the plasma display panel at the initial startup is input to the scan driving IC so that the erroneous data is clocked. Even if the output is shifted according to the above, power is not output through the power output unit.

Therefore, the occurrence of a malfunction of the scan driver IC due to the wrong data remaining after the initializing period of the plasma display panel during the initial startup is prevented, thereby preventing the scan driver IC from being burned out by the noise that may be generated during the initial startup. Can be.

The plasma display panel, its driving device, and the driving method shown in FIGS. 1 to 4 are just one embodiment to which the driving method of the plasma display panel according to the present invention can be applied, and various other plasma display panels and its driving method. Applicable to the device and the driving method.

According to the display panel driving apparatus according to the present invention, the scan driving IC is operated by a dummy clock without input of driving data for a period of the clock number equal to or greater than the scanning player just before the start of the first subfield after the initial startup of the display panel. In addition, scan malfunction due to incorrect data can be prevented.

In addition, malfunction of the scan driver IC can be prevented, and burnout of the scan driver IC can be prevented.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (10)

Driving the display panel in which discharge cells are formed in an area where the X electrode and Y electrode lines and the address electrode lines cross each other. A controller which processes the image data input from the outside and generates a scan data signal, a reset / hold data signal, an address data signal, and an X data signal; A reset / maintenance circuit unit for applying a reset / maintenance driving signal according to the reset and sustain data signals to the Y electrode lines; An address driver for applying an address driving signal corresponding to the address data signal to the address electrode lines; An X driver configured to apply a common driving signal according to the X data signal to X electrode lines; And The scan driving signal according to the scan data signal is applied to the Y electrode lines according to the clock signal, and the scan driving signal is generated more than the number of clocks corresponding to the number of the Y electrode lines immediately before the first subfield at initial startup. And a scan driver which is driven while not being provided. The method of claim 1, The scan data signal includes a data signal and a clock signal, And the scan driver includes a shift register configured to shift and output the data signal in synchronization with the clock signal. The method of claim 2, The scan data signal includes a data signal, an output enable signal, and a clock signal. And the scan driver further includes a latch configured to temporarily store an output of the shift register to enable an output according to an output enable signal input from the controller. The method of claim 1, The scan data signal includes a data signal, an output enable signal, and a clock signal. A scan driver IC temporarily shifts and outputs the data signal in synchronization with the clock signal, and temporarily stores an output of the shift register to enable an output according to an output enable signal input from the controller. With a latch, And the scan driver is formed by serial connection of at least one of the scan driver ICs. The method according to claim 3 or 4, And the scan driver further comprises a power output unit configured to output the scan pulse according to the output of the latch. The method of claim 4, wherein The scan drive unit, And a second scan driver IC receiving the data signal from the controller and a second scan driver IC receiving the data signal from the first scan driver IC. The method of claim 4, wherein And the shift register outputs the data signal to a next scan driver IC connected in series when the data signal is shifted to the last bit. For a display panel in which discharge cells are formed in a region where scan electrode lines and address electrode lines intersect, scan pulses are sequentially applied to the scan electrode lines, and a discharge cell to be displayed for the scan pulses is formed. Select discharge cells to be displayed by applying an address pulse to the address electrode lines, A shift register for shifting and outputting a data signal for scanning driving in synchronization with a clock signal, a latch for temporarily storing and outputting the output of the shift register, and a power output unit for outputting the scan pulse in accordance with the output of the latch; Driven by the scan driver, And the scan driver is driven while no scan pulse is generated for at least a clock number corresponding to the number of scan electrode lines immediately before the first subfield at initial startup. The method of claim 8, The scan driver IC shifts and outputs a data signal for scan driving in synchronization with a clock signal, a latch for temporarily storing and outputting the output of the shift register, and outputting the scan pulse in accordance with the output of the latch. With a power output, And the scan driver is formed by serial connection of at least one of the scan driver ICs. The method of claim 8, And the shift register outputs the data signal to a next scan driver IC connected in series when the data signal is shifted to the last bit.

Images