JP2010118526A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2010118526A
JP2010118526A JP2008291099A JP2008291099A JP2010118526A JP 2010118526 A JP2010118526 A JP 2010118526A JP 2008291099 A JP2008291099 A JP 2008291099A JP 2008291099 A JP2008291099 A JP 2008291099A JP 2010118526 A JP2010118526 A JP 2010118526A
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Japan
Prior art keywords
wire
semiconductor device
pad
electrode
manufacturing
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JP2008291099A
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Japanese (ja)
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Hideyuki Shinkawa
秀之 新川
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2008291099A priority Critical patent/JP2010118526A/en
Priority to US12/608,712 priority patent/US7943433B2/en
Publication of JP2010118526A publication Critical patent/JP2010118526A/en
Withdrawn legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which can prevent an electrical short circuit between wires by preventing contact between the wires occurring in running in a liquid resin. <P>SOLUTION: A rectangular principal surface of a semiconductor chip CH includes first and second vertexes A1, A2 located on a diagonal line, and first and second sides L1, L2 connecting the first and second vertexes A1, A2 to each other. Wires WR are formed between electrodes IL and pads PD of the semiconductor chip CH. The wires WR are housed in a cavity CV of a die ML. A liquid resin is run into the cavity CV to advance from the first vertex A1 to the second vertex A2 along the first and second sides L1, L2. A resin part is formed by curing the liquid resin. The formation of the wire WR is carried out by forming the wire WR to pass through a distant side from the first vertex A1 with respect to the line connecting the pad PD to the electrode IL. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、特に、ワイヤを封止する樹脂部を有する半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a resin portion for sealing a wire.

半導体パッケージを封止構造的に見ると、気密封止パッケージと、非気密封止パッケージとの２つに分けることができる。特に非気密封止パッケージの中でも、トランスファ・モールド・タイプのプラスチック・パッケージが現在主流となっている。   When the semiconductor package is viewed from a sealing structure, it can be divided into two, an airtight sealed package and a non-airtight sealed package. Among non-hermetic sealed packages, transfer mold type plastic packages are currently the mainstream.

トランスファ・モールド・タイプのプラスチック・パッケージの技術は、たとえば特開２００２−３１４００３号公報（特許文献１）に開示されている。この技術によれば、半導体装置の製造方法は以下の工程を有する。   The technology of the transfer mold type plastic package is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-314003 (Patent Document 1). According to this technique, the method for manufacturing a semiconductor device includes the following steps.

樹脂フレーム上にダイボンド材によりＩＣチップが固定される。ワイヤボンディングによりＩＣチップ上のボンディングパッドと、樹脂フレームのランドとが電気的に接続される。モールド金型を使用してトランスファ・モールドを行なうことにより、ＩＣチップが樹脂封止される。
特開２００２−３１４００３号公報 An IC chip is fixed on the resin frame by a die bond material. The bonding pad on the IC chip and the land of the resin frame are electrically connected by wire bonding. The IC chip is resin-sealed by performing transfer molding using a mold.
JP 2002-314003 A

ＳｏＣ(System on Chip)などのように多数の密集したボンディングパッドを有するチップを用いた場合、各ボンディングパッドに接続されるワイヤも密集して形成される。これらのワイヤは、トランスファ・モールド工程において、流体であるモールド樹脂によって流れ方向にある程度押し流される。この際に特定のワイヤが特に大きく押し流されて下流側のワイヤと接触することで、ワイヤ間の電気的短絡が生じてしまうという問題があった。   When a chip having a large number of dense bonding pads such as SoC (System on Chip) is used, wires connected to the bonding pads are also formed densely. These wires are pushed to some extent in the flow direction by the molding resin that is a fluid in the transfer molding process. At this time, there is a problem that an electrical short circuit between the wires is caused when the specific wire is swept away particularly greatly and comes into contact with the wire on the downstream side.

本発明は、上記の課題に鑑みてなされたものであり、その目的は、液状樹脂の流し込みの際に生じるワイヤ間の接触を防止することにより、ワイヤ間の電気的短絡を防止することができる半導体装置の製造方法を提供することである。   This invention is made | formed in view of said subject, The objective can prevent the electrical short circuit between wires by preventing the contact between the wires which arises in the case of pouring of liquid resin. A method for manufacturing a semiconductor device is provided.

本実施の形態の半導体装置の製造方法は、互いに対角線上にある第１および第２の頂点とこの第１および第２の頂点をつなぐ第１および第２の辺とを有する長方形状の主面を有し、かつ主面上に第１のパッドを有する半導体チップと、電極と、第１のパッドと電極とを接続するワイヤと、このワイヤを封止する樹脂部とを含む半導体装置の製造方法であって、以下の工程を有する。   The semiconductor device manufacturing method of the present embodiment includes a rectangular main surface having first and second vertices that are diagonal to each other and first and second sides that connect the first and second vertices. And a semiconductor chip having a first pad on the main surface, an electrode, a wire connecting the first pad and the electrode, and a resin portion for sealing the wire A method comprising the following steps.

第１のパッドと電極との間にワイヤが形成される。金型のキャビティ内にワイヤが収められる。第１の頂点から第１および第２の辺に沿って第２の頂点に向かうようにキャビティ内に液状樹脂が流し込まれる。液状樹脂を硬化することによって樹脂部が形成される。ワイヤの形成は、平面視において、第１のパッドと電極とを結んだ直線に対して第１の頂点から遠い側を通るようにワイヤを形成することにより行なわれる。   A wire is formed between the first pad and the electrode. A wire is contained in the cavity of the mold. Liquid resin is poured into the cavity from the first vertex toward the second vertex along the first and second sides. The resin portion is formed by curing the liquid resin. The wire is formed by forming the wire so as to pass through a side far from the first vertex with respect to a straight line connecting the first pad and the electrode in plan view.

本実施の形態の半導体装置の製造方法によれば、第１のパッドと電極とを結んだ直線に対して、半導体チップの第１の頂点から遠い側、すなわち液状樹脂の流れの下流側を通るようにワイヤが形成される。これにより、液状樹脂によってワイヤが上流側から下流側に押し流される程度のワイヤ間ばらつきが抑制される。よって、特定のワイヤが大きく押し流されて他のワイヤに接触することが防止されるので、ワイヤ間の電気的短絡を防止することができる。   According to the method for manufacturing a semiconductor device of the present embodiment, the straight line connecting the first pad and the electrode passes the side far from the first apex of the semiconductor chip, that is, the downstream side of the flow of the liquid resin. Thus, a wire is formed. Thereby, the dispersion | variation between wires of the grade by which a wire is pushed away from the upstream to the downstream by liquid resin is suppressed. Therefore, it is possible to prevent a specific wire from being greatly swept away and contact with another wire, so that an electrical short circuit between the wires can be prevented.

以下、本発明の実施の形態について図に基づいて説明する。
（実施の形態１）
図１は、本発明の実施の形態１における半導体装置の構成を概略的に示す斜視図である。図１を参照して、本実施の形態の半導体装置は、トランスファ・モールド・タイプのプラスチック・パッケージＱＰであり、たとえばＱＦＰ（Quad Flat Package）である。このタイプのパッケージＱＰは、半導体チップＣＨを封止する樹脂部ＭＲの外周の四辺の各々から突き出したアウターリード部ＯＬを有する。また半導体チップＣＨは、長方形状の主面（図中の上面）を有する。この主面は、第１および第２の頂点Ａ１、Ａ２と、第１および第２の辺Ｌ１、Ｌ２とを有する。第１および第２の頂点Ａ１、Ａ２は、互いに対角線上に位置している。また第１および第２の辺Ｌ１、Ｌ２は、第１および第２の頂点Ａ１、Ａ２を繋いでいる。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a perspective view schematically showing a configuration of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device of the present embodiment is a transfer mold type plastic package QP, for example, a QFP (Quad Flat Package). This type of package QP has an outer lead portion OL protruding from each of the four outer peripheral sides of the resin portion MR that seals the semiconductor chip CH. The semiconductor chip CH has a rectangular main surface (the upper surface in the drawing). The main surface has first and second vertices A1 and A2, and first and second sides L1 and L2. The first and second vertices A1 and A2 are located diagonally to each other. The first and second sides L1 and L2 connect the first and second vertices A1 and A2.

図２は、図１の線ＩＩ−ＩＩに沿った概略断面図である。また図３は、図１の樹脂部内部における構成を概略的に示す平面図である。また図４は、図３のボンディングワイヤのうち半導体チップの外周ボンディングパッドに接続されたものの配置を説明するための平面図である。また図５は、図３のボンディングワイヤのうち半導体チップの内周ボンディングパッドに接続されたものの配置を説明するための平面図である。   FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. FIG. 3 is a plan view schematically showing a configuration inside the resin portion of FIG. FIG. 4 is a plan view for explaining the arrangement of the bonding wires of FIG. 3 connected to the outer peripheral bonding pads of the semiconductor chip. FIG. 5 is a plan view for explaining the arrangement of the bonding wires of FIG. 3 connected to the inner peripheral bonding pads of the semiconductor chip.

図２〜図５を参照して、樹脂部ＭＲ内部には、上述した半導体チップＣＨと、リードフレームＬＦと、ボンディングワイヤＷＲとが配置されている。   2-5, the above-described semiconductor chip CH, lead frame LF, and bonding wire WR are arranged inside the resin portion MR.

半導体チップＣＨは主面上にボンディングパッドＰＤを有する。ボンディングパッドＰＤは、この主面の内周側に位置する内周ボンディングパッドＰＤ１（第１のパッド）と、この主面の外周側に位置する外周ボンディングパッドＰＤ２（第２のパッド）とを有する。この主面の外縁と外周ボンディングパッドＰＤ２との間隔は、この外縁と内周ボンディングパッドＰＤ１との間隔に比して小さい。   The semiconductor chip CH has a bonding pad PD on the main surface. Bonding pad PD has an inner peripheral bonding pad PD1 (first pad) located on the inner peripheral side of the main surface and an outer peripheral bonding pad PD2 (second pad) located on the outer peripheral side of the main surface. . The distance between the outer edge of the main surface and the outer peripheral bonding pad PD2 is smaller than the distance between the outer edge and the inner peripheral bonding pad PD1.

ボンディングワイヤＷＲは、内周ボンディングワイヤＷＲ１と、外周ボンディングワイヤＷＲ２とを有する。内周ボンディングワイヤＷＲ１は、内周ボンディングパッドＰＤ１とリードフレームＬＦとを接続している。また外周ボンディングワイヤＷＲ２は、外周ボンディングパッドＰＤ２とリードフレームＬＦとを接続している。図２に示すように、内周ボンディングワイヤＷＲ１は、外周ボンディングワイヤＷＲ２を飛び越えるように設けられている。このため内周ボンディングワイヤＷＲ１の高さは、外周ボンディングワイヤＷＲ２の高さよりも高くされている。   The bonding wire WR has an inner peripheral bonding wire WR1 and an outer peripheral bonding wire WR2. The inner peripheral bonding wire WR1 connects the inner peripheral bonding pad PD1 and the lead frame LF. The outer peripheral bonding wire WR2 connects the outer peripheral bonding pad PD2 and the lead frame LF. As shown in FIG. 2, the inner peripheral bonding wire WR1 is provided so as to jump over the outer peripheral bonding wire WR2. For this reason, the height of the inner peripheral bonding wire WR1 is set higher than the height of the outer peripheral bonding wire WR2.

リードフレームＬＦは、樹脂部ＭＲ内部において、ダイパッドＤＰと、複数本のインナーリード部ＩＬ（電極）と、バスバーＢＢと、接地リングＧＲと、接続部ＣＰと、吊リードＳＬとを有し、また樹脂部ＭＲ外部においてアウターリード部ＯＬ（電極）を有する。   The lead frame LF includes a die pad DP, a plurality of inner lead portions IL (electrodes), a bus bar BB, a grounding ring GR, a connection portion CP, and a suspension lead SL inside the resin portion MR. The outer lead part OL (electrode) is provided outside the resin part MR.

ダイパッドＤＰは、リードフレームＬＦのほぼ中央に位置している。またダイパッドＤＰ上に接着剤を介して半導体チップＣＨが搭載されている。   The die pad DP is located approximately at the center of the lead frame LF. A semiconductor chip CH is mounted on the die pad DP via an adhesive.

複数本のインナーリード部ＩＬは、半導体チップＣＨとの間で入出力信号をやり取りする部分であり、たとえば半導体チップＣＨを中心とした放射線状に配置されている。複数本のインナーリード部ＩＬの各々の先端は、平面視においてダイパッドＤＰおよび半導体チップＣＨの各々の外縁よりも外周側に位置している。   The plurality of inner lead portions IL are portions that exchange input / output signals with the semiconductor chip CH, and are arranged in a radial pattern with the semiconductor chip CH at the center, for example. The tips of the plurality of inner lead portions IL are located on the outer peripheral side of the outer edges of the die pad DP and the semiconductor chip CH in plan view.

バスバーＢＢは、たとえば半導体チップＣＨに電源電位を供給するためのものである。またバスバーＢＢは屈曲部ＳＴを有する。   The bus bar BB is for supplying a power supply potential to the semiconductor chip CH, for example. The bus bar BB has a bent portion ST.

接地リングＧＲは、半導体チップＣＨに接地電位を供給するためのものである。この接地リングＧＲは、平面視においてダイパッドＤＰの外縁よりも外周側に位置し、バスバーＢＢの張り出し部よりも内周側に位置している。この接地リングＧＲはダイパッドＤＰの外周全周を取囲むように配置されている。また接地リングＧＲとダイパッドＤＰとの間には、接地リングＧＲの上面に対してダイパッドＤＰの上面が低くなるように屈曲された屈曲部ＳＴ１が形成されている。また接地リングＧＲと吊リードＳＬとの間には、吊リードＳＬの上面に対して接地リングＧＲの上面が低くなるように屈曲された屈曲部ＳＴ２が形成されている。   The ground ring GR is for supplying a ground potential to the semiconductor chip CH. The ground ring GR is located on the outer peripheral side with respect to the outer edge of the die pad DP in a plan view, and is located on the inner peripheral side with respect to the protruding portion of the bus bar BB. The ground ring GR is disposed so as to surround the entire outer periphery of the die pad DP. In addition, a bent portion ST1 is formed between the ground ring GR and the die pad DP, which is bent so that the upper surface of the die pad DP is lower than the upper surface of the ground ring GR. In addition, a bent portion ST2 is formed between the ground ring GR and the suspension lead SL, which is bent so that the upper surface of the ground ring GR is lower than the upper surface of the suspension lead SL.

接続部ＣＰは、ダイパッドＤＰと接地リングＧＲとを繋ぐためのものであり、平面視においてダイパッドＤＰの一辺にたとえば２つずつ設けられている。吊リードＳＬは、接地リングＧＲの４つの角部の各々に接続されており、かつ接地リングＧＲとの接続部から外周側へ延びている。   The connecting portion CP is for connecting the die pad DP and the ground ring GR, and is provided, for example, two on each side of the die pad DP in plan view. The suspension lead SL is connected to each of the four corners of the ground ring GR, and extends from the connection portion with the ground ring GR to the outer peripheral side.

外周ボンディングパッドＰＤ２のいくつかは、バスバーＢＢの張り出し部に外周ボンディングワイヤＷＲ２により電気的に接続されている。外周ボンディングパッドＰＤ２の残りのいくつかは、接地リングＧＲに外周ボンディングワイヤＷＲ２により電気的に接続されている。   Some of the outer peripheral bonding pads PD2 are electrically connected to the protruding portion of the bus bar BB by an outer peripheral bonding wire WR2. The remaining some of the outer peripheral bonding pads PD2 are electrically connected to the ground ring GR by outer peripheral bonding wires WR2.

内周ボンディングパッドＰＤ１のいくつかは、インナーリード部ＩＬに内周ボンディングワイヤＷＲ１により電気的に接続されている。内周ボンディングパッドＰＤ１のたとえば１つは、バスバーＢＢの並走部に内周ボンディングワイヤＷＲ１により電気的に接続されている。   Some of the inner peripheral bonding pads PD1 are electrically connected to the inner lead portion IL by an inner peripheral bonding wire WR1. For example, one of the inner peripheral bonding pads PD1 is electrically connected to the parallel running portion of the bus bar BB by an inner peripheral bonding wire WR1.

次に、本実施の形態の半導体装置の製造方法について説明する。
図６は、本発明の実施の形態１における半導体装置の製造方法の第１工程を概略的に示す部分断面図である。また図７は、図６のボンディングワイヤの形状を説明するための概略的な部分断面図である。また図８は、図７の線ＶＩＩＩ−ＶＩＩＩに沿った概略的な部分断面図である。また図９は、図７の矢印ＩＸから見た概略的な部分平面図である。また図１０は、図７の矢印Ｘから見た概略的な部分斜視図である。 Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 6 is a partial cross sectional view schematically showing a first step of the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 7 is a schematic partial cross-sectional view for explaining the shape of the bonding wire of FIG. FIG. 8 is a schematic partial sectional view taken along line VIII-VIII in FIG. FIG. 9 is a schematic partial plan view seen from the arrow IX in FIG. FIG. 10 is a schematic partial perspective view seen from the arrow X in FIG.

主に図６〜図１０を参照して、まずリードフレームＬＦが準備される。次にリードフレームＬＦのダイパッドＤＰ上に半導体チップＣＨが接着剤などを介して接着される。   Referring mainly to FIGS. 6 to 10, first, a lead frame LF is prepared. Next, the semiconductor chip CH is bonded onto the die pad DP of the lead frame LF via an adhesive or the like.

次にボンディングパッドＰＤからリードフレームＬＦへボンディングワイヤＷＲが形成されることにより、ボンディングパッドＰＤとリードフレームＬＦとのワイヤボンディングが行なわれる。より具体的には、まず外周ボンディングパッドＰＤ２からリードフレームＬＦへ外周ボンディングワイヤＷＲ２が形成され、次に内周ボンディングパッドＰＤ１からリードフレームＬＦへ内周ボンディングワイヤＷＲ１が形成される。   Next, a bonding wire WR is formed from the bonding pad PD to the lead frame LF, whereby wire bonding between the bonding pad PD and the lead frame LF is performed. More specifically, the outer peripheral bonding wire WR2 is first formed from the outer peripheral bonding pad PD2 to the lead frame LF, and then the inner peripheral bonding wire WR1 is formed from the inner peripheral bonding pad PD1 to the lead frame LF.

ボンディングワイヤＷＲの形成は、平面視において、ボンディングパッドＰＤとリードフレームＬＦとを結んだ直線（図９および図１０の破線）に対して第１の頂点Ａ１（図１）から遠い側（図中、矢印Ｍが向かう側）を通るようにボンディングワイヤＷＲを形成することにより行なわれる。この矢印Ｍは、後述する液状樹脂の流れ方向に対応している。   The bonding wire WR is formed on the side (in the drawing) farther from the first vertex A1 (FIG. 1) than the straight line (broken line in FIGS. 9 and 10) connecting the bonding pad PD and the lead frame LF in plan view. The bonding wire WR is formed so as to pass through (the side to which the arrow M is directed). This arrow M corresponds to the flow direction of the liquid resin described later.

ボンディングワイヤＷＲは、部分Ｗａ〜Ｗｃを有する。部分ＷａはボンディングパッドＰＤからほぼ垂直に立上がっている。部分Ｗｂは、部分Ｗａと部分Ｗｃを繋いでいる。部分Ｗｃは、部分Ｗｂと、インナーリード部ＩＬなどのリードフレームＬＦとを繋いでいる。部分Ｗｂと部分Ｗｃとの間にはワイヤボンディングの際に屈曲点Ｆが形成される。   The bonding wire WR has portions Wa to Wc. The portion Wa rises substantially vertically from the bonding pad PD. The part Wb connects the part Wa and the part Wc. The portion Wc connects the portion Wb and the lead frame LF such as the inner lead portion IL. A bending point F is formed between the part Wb and the part Wc during wire bonding.

屈曲点Ｆは、平面視において、ボンディングパッドＰＤとリードフレームＬＦとを結んだ直線（図９および図１０の破線）に対して第１の頂点Ａ１（図１）から遠い側（図９の上側、図１０の右側）を通るように形成される。またボンディングワイヤＷＲは、図８に示すように、屈曲点Ｆ近傍において半導体チップＣＨの主面に対して角度ＴＨだけ傾いた面に沿って延びている。角度ＴＨは、たとえば２０度とされる。   The bending point F is a side farther from the first vertex A1 (FIG. 1) than the straight line (dashed line in FIGS. 9 and 10) connecting the bonding pad PD and the lead frame LF in plan view (upper side in FIG. 9). , Right side of FIG. 10). Further, as shown in FIG. 8, the bonding wire WR extends along a surface inclined by an angle TH with respect to the main surface of the semiconductor chip CH in the vicinity of the bending point F. The angle TH is, for example, 20 degrees.

図１１は、本発明の実施の形態１における半導体装置の製造方法の第２工程を概略的に示す部分平面図である。また図１２は、図１１の線ＸＩＩ−ＸＩＩに沿った概略的な部分断面図である。また図１３は、図１２の線ＸＩＩＩ−ＸＩＩＩに沿った概略的な部分断面図である。   FIG. 11 is a partial plan view schematically showing a second step of the method for manufacturing the semiconductor device in the first embodiment of the present invention. FIG. 12 is a schematic partial sectional view taken along line XII-XII in FIG. FIG. 13 is a schematic partial sectional view taken along line XIII-XIII in FIG.

図１１〜図１３を参照して、トランスファ・モールド用の金型ＭＬが準備される。金型ＭＬは上金型ＭＬａと、下金型ＭＬｂとを有する。上金型ＭＬａおよび下金型ＭＬｂは、互いに対向することによりキャビティＣＶが形成されるような形状を有する。   Referring to FIGS. 11 to 13, a mold ML for transfer molding is prepared. The mold ML has an upper mold MLa and a lower mold MLb. The upper mold MLa and the lower mold MLb have such a shape that the cavity CV is formed by facing each other.

次にアウターリード部ＯＬが上金型ＭＬａと下金型ＭＬｂとの間に挟み込まれる。これによりボンディングワイヤＷＲはキャビティＣＶ内に収められる。   Next, the outer lead part OL is sandwiched between the upper mold MLa and the lower mold MLb. As a result, the bonding wire WR is accommodated in the cavity CV.

次に、矢印Ｍ（図１１および図１３）に示すように、第１の頂点Ａ１（図１３）から第１および第２の辺Ｌ１、Ｌ２に沿って第２の頂点Ａ２に向かうように、キャビティＣＶ内に液状樹脂が流し込まれる。この液状樹脂の流し込みによって、角度ＴＨ（図８）は、たとえば２０度から１０±５度だけ増大して３０±５度となる。すなわち角度ＴＨの増大の程度は、各ボンディングワイヤＷＲ間で、±５度程度のばらつきを有する。   Next, as shown by an arrow M (FIGS. 11 and 13), from the first vertex A1 (FIG. 13) to the second vertex A2 along the first and second sides L1 and L2, Liquid resin is poured into the cavity CV. By flowing the liquid resin, the angle TH (FIG. 8) is increased from 20 degrees to 10 ± 5 degrees, for example, to 30 ± 5 degrees. That is, the degree of increase in the angle TH has a variation of about ± 5 degrees between the bonding wires WR.

上記の液状樹脂が硬化されることによって樹脂部ＭＲ（図１）が形成される。次にアウターリード部ＯＬ（図１）の切断および曲げ加工が行なわれる。これにより、本実施の形態の半導体装置が製造される。   The liquid resin is cured to form a resin portion MR (FIG. 1). Next, the outer lead OL (FIG. 1) is cut and bent. Thereby, the semiconductor device of the present embodiment is manufactured.

次に、本実施の形態の比較例について説明する。
図１４および図１５のそれぞれは、比較例における半導体装置の製造方法の第１工程を概略的に示す部分断面図であり、本実施の形態の図８および図１３に対応する図である。本比較例のボンディングワイヤＷＺは、本実施の形態のボンディングワイヤＷＲ（図８）と異なり、液状樹脂が流し込まれる前においては半導体チップＣＨの主面に対する傾斜（図８の角度ＴＨに示す傾斜）を有していない。これによりボンディングワイヤＷＺは、図１５に示すように、平面視においては直線的な形状を有する。 Next, a comparative example of the present embodiment will be described.
FIG. 14 and FIG. 15 are partial cross-sectional views schematically showing a first step of the semiconductor device manufacturing method in the comparative example, and correspond to FIG. 8 and FIG. 13 of the present embodiment. Unlike the bonding wire WR (FIG. 8) of the present embodiment, the bonding wire WZ of this comparative example is inclined with respect to the main surface of the semiconductor chip CH (inclination indicated by an angle TH in FIG. 8) before the liquid resin is poured. Does not have. As a result, the bonding wire WZ has a linear shape in plan view as shown in FIG.

図１６および図１７のそれぞれは、比較例における半導体装置の製造方法の第２工程を概略的に示す部分平面図および部分断面図である。
このボンディングワイヤＷＺに対して液状樹脂が矢印Ｍの方向に流し込まれると、図１６に示すように、ボンディングワイヤＷＺは平面視において矢印Ｍの方向に湾曲するように押し流される。この結果、ボンディングワイヤＷＺは、図８に示す形状に近い形状を有するようになるが、角度ＴＨ（図８）のボンディングワイヤＷＺ間でのばらつきは、本実施の形態に比して大きくなる。すなわち液状樹脂が流し込まれた後のボンディングワイヤＷＺの角度ＴＨ（図８）は、たとえば３０±２０度となり、本実施の形態における角度ＴＨ＝３０±５度と比して、角度ＴＨのばらつきが大きくなる。 FIG. 16 and FIG. 17 are a partial plan view and a partial cross-sectional view schematically showing a second step of the semiconductor device manufacturing method in the comparative example.
When the liquid resin is poured into the bonding wire WZ in the direction of the arrow M, the bonding wire WZ is pushed so as to bend in the direction of the arrow M in plan view as shown in FIG. As a result, the bonding wire WZ has a shape close to the shape shown in FIG. 8, but the variation in the angle TH (FIG. 8) between the bonding wires WZ is larger than that in the present embodiment. That is, the angle TH (FIG. 8) of the bonding wire WZ after the liquid resin is poured is, for example, 30 ± 20 degrees, and the variation in the angle TH is smaller than the angle TH = 30 ± 5 degrees in the present embodiment. growing.

このようにボンディングワイヤＷＺ間で液状樹脂に押し流される程度のばらつきが大きいことから、図１７に示すように、ボンディングワイヤＷＺ間での接触による短絡ＳＣが発生しやすくなる。この短絡ＳＣは、半導体装置の故障の原因となる。   As described above, since the dispersion to the extent that the bonding wire WZ is pushed away by the liquid resin is large, as shown in FIG. 17, a short circuit SC due to contact between the bonding wires WZ is likely to occur. This short circuit SC causes a failure of the semiconductor device.

本実施の形態の半導体装置の製造方法によれば、ボンディングパッドＰＤと、リードフレームＬＦのたとえばインナーリード部ＩＬとを結んだ直線（図９および図１０の破線）に対して、半導体チップＣＨの第１の頂点Ａ１から遠い側、すなわち液状樹脂の流れ（矢印Ｍ）の下流側を通るようにボンディングワイヤＷＲが形成される。これにより、液状樹脂によってボンディングワイヤＷＲが上流側から下流側に押し流される程度のボンディングワイヤＷＲ間でのばらつきが抑制される。よって、特定のボンディングワイヤＷＲが大きく押し流されて他のボンディングワイヤＷＲに接触することが防止されるので、ボンディングワイヤＷＲ間の電気的短絡ＳＣ（図１７）を防止することができる。   According to the manufacturing method of the semiconductor device of the present embodiment, the semiconductor chip CH has a straight line (broken line in FIGS. 9 and 10) connecting the bonding pad PD and, for example, the inner lead part IL of the lead frame LF. The bonding wire WR is formed so as to pass through the side far from the first vertex A1, that is, the downstream side of the liquid resin flow (arrow M). Thereby, the variation between the bonding wires WR to the extent that the bonding wires WR are swept away from the upstream side by the liquid resin is suppressed. Therefore, the specific bonding wire WR is prevented from being greatly washed away and coming into contact with other bonding wires WR, so that an electrical short circuit SC (FIG. 17) between the bonding wires WR can be prevented.

また本実施の形態によれば、外周ボンディングワイヤＷＲ２の高さよりも高い内周ボンディングワイヤＷＲ１が形成される。このように高さが高いことで液状樹脂に押し流されやすい内周ボンディングワイヤＷＲ１の短絡を、本実施の形態により防止することができる。   Further, according to the present embodiment, the inner peripheral bonding wire WR1 higher than the height of the outer peripheral bonding wire WR2 is formed. The short circuit of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to such a high height can be prevented by the present embodiment.

また本実施の形態によれば、図５に示すように、一部の内周ボンディングワイヤＷＲ１は、接地リングＧＲを超えることができるだけの長さに渡って設けられる。このように長さが長いことで液状樹脂に押し流されやすい内周ボンディングワイヤＷＲ１の短絡を、本実施の形態により防止することができる。   Further, according to the present embodiment, as shown in FIG. 5, some inner peripheral bonding wires WR1 are provided over a length that can exceed the ground ring GR. In this way, short-circuiting of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to the long length can be prevented by the present embodiment.

また本実施の形態によれば、図５に示すように、一部の内周ボンディングワイヤＷＲ１は、バスバーＢＢを超えることができるだけの長さに渡って設けられる。このように長さが長いことで液状樹脂に押し流されやすい内周ボンディングワイヤＷＲ１の短絡を、本実施の形態により防止することができる。   Further, according to the present embodiment, as shown in FIG. 5, some of the inner peripheral bonding wires WR1 are provided over a length that can exceed the bus bar BB. In this way, short-circuiting of the inner peripheral bonding wire WR1 that is easy to be washed away by the liquid resin due to the long length can be prevented by the present embodiment.

また本実施の形態によれば、リードフレームＬＦは、アウターリード部ＯＬを有する。これにより、たとえばＱＦＰなどの、樹脂部ＭＲから突き出た外部電極を有するパッケージを形成することができる。   According to the present embodiment, the lead frame LF has the outer lead portion OL. Thereby, a package having an external electrode protruding from the resin portion MR, such as QFP, can be formed.

（実施の形態２）
図１８は、本発明の実施の形態２における半導体装置の構成を概略的に示す断面図である。また図１９は、図１８の樹脂部内部における構成を概略的に示す平面図である。また図２０は、図１９の破線部ＸＸの概略拡大図である。 (Embodiment 2)
FIG. 18 is a cross sectional view schematically showing a configuration of the semiconductor device in the second embodiment of the present invention. FIG. 19 is a plan view schematically showing the configuration inside the resin portion of FIG. FIG. 20 is a schematic enlarged view of a broken line portion XX in FIG.

図１８〜図２０を参照して、本実施の形態の半導体装置は、ＢＧＡ（Ball Grid Array）タイプのプラスチック・パッケージＢＰである。パッケージＢＰは、リードフレームＬＦ（実施の形態１）の代わりに、電極ＥＬと、回路基板ＣＢと、はんだボールＢＬとを有する。また樹脂部ＭＲ（実施の形態１）の代わりに樹脂部ＭＲｂを有する。   Referring to FIGS. 18 to 20, the semiconductor device of the present embodiment is a BGA (Ball Grid Array) type plastic package BP. The package BP has an electrode EL, a circuit board CB, and a solder ball BL instead of the lead frame LF (Embodiment 1). Moreover, it has resin part MRb instead of resin part MR (Embodiment 1).

電極ＥＬは、ボンディングワイヤＷＲによって半導体チップＣＨと接続されている。また半導体チップＣＨおよび電極ＥＬの各々は回路基板ＣＢに支持されている。また樹脂部ＭＲｂは、ボンディングワイヤＷＲおよび半導体チップＣＨを封止している。   The electrode EL is connected to the semiconductor chip CH by a bonding wire WR. Each of the semiconductor chip CH and the electrode EL is supported by the circuit board CB. Resin portion MRb seals bonding wire WR and semiconductor chip CH.

なお、上記以外の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰返さない。   Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

本実施の形態によっても、実施の形態１と同様の効果を得ることができる。
また本実施の形態によれば、パッケージＢＰは、半導体チップＣＨおよび電極ＥＬの各々を支持する回路基板ＣＢを有する。これにより、回路基板ＣＢを有するＢＧＡパッケージを形成することができる。 Also in the present embodiment, the same effect as in the first embodiment can be obtained.
Further, according to the present embodiment, the package BP includes the circuit board CB that supports each of the semiconductor chip CH and the electrode EL. Thereby, a BGA package having the circuit board CB can be formed.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

本発明は、ワイヤを封止する樹脂部を有する半導体装置の製造方法に特に有利に適用され得る。   The present invention can be particularly advantageously applied to a method for manufacturing a semiconductor device having a resin portion for sealing a wire.

本発明の実施の形態１における半導体装置の構成を概略的に示す斜視図である。1 is a perspective view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 図１の線ＩＩ−ＩＩに沿った概略断面図である。It is a schematic sectional drawing in alignment with line II-II of FIG. 図１の樹脂部内部における構成を概略的に示す平面図である。It is a top view which shows schematically the structure in the inside of the resin part of FIG. 図３のボンディングワイヤのうち半導体チップの外周ボンディングパッドに接続されたものの配置を説明するための平面図である。It is a top view for demonstrating arrangement | positioning of what was connected to the outer periphery bonding pad of the semiconductor chip among the bonding wires of FIG. 図３のボンディングワイヤのうち半導体チップの内周ボンディングパッドに接続されたものの配置を説明するための平面図である。It is a top view for demonstrating arrangement | positioning of what was connected to the inner periphery bonding pad of the semiconductor chip among the bonding wires of FIG. 本発明の実施の形態１における半導体装置の製造方法の第１工程を概略的に示す部分断面図である。It is a fragmentary sectional view which shows schematically the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. 図６のボンディングワイヤの形状を説明するための概略的な部分断面図である。It is a schematic fragmentary sectional view for demonstrating the shape of the bonding wire of FIG. 図７の線ＶＩＩＩ−ＶＩＩＩに沿った概略的な部分断面図である。FIG. 8 is a schematic partial sectional view taken along line VIII-VIII in FIG. 7. 図７の矢印ＩＸから見た概略的な部分平面図である。FIG. 8 is a schematic partial plan view seen from an arrow IX in FIG. 7. 図７の矢印Ｘから見た概略的な部分斜視図である。FIG. 8 is a schematic partial perspective view seen from an arrow X in FIG. 7. 本発明の実施の形態１における半導体装置の製造方法の第２工程を概略的に示す部分平面図である。It is a fragmentary top view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. 図１１の線ＸＩＩ−ＸＩＩに沿った概略的な部分断面図である。FIG. 12 is a schematic partial cross-sectional view taken along line XII-XII in FIG. 11. 図１２の線ＸＩＩＩ−ＸＩＩＩに沿った概略的な部分断面図である。FIG. 13 is a schematic partial sectional view taken along line XIII-XIII in FIG. 12. 比較例における半導体装置の製造方法の第１工程を概略的に示す部分断面図であり、本実施の形態の図８に対応する図である。It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in a comparative example, and is a figure corresponding to FIG. 8 of this Embodiment. 比較例における半導体装置の製造方法の第１工程を概略的に示す部分断面図であり、本実施の形態の図１３に対応する図である。It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in a comparative example, and is a figure corresponding to FIG. 13 of this Embodiment. 比較例における半導体装置の製造方法の第２工程を概略的に示す部分平面図である。It is a fragmentary top view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in a comparative example. 比較例における半導体装置の製造方法の第２工程を概略的に示す部分断面図である。It is a fragmentary sectional view showing roughly the 2nd process of a manufacturing method of a semiconductor device in a comparative example. 本発明の実施の形態２における半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. 図１８の樹脂部内部における構成を概略的に示す平面図である。It is a top view which shows schematically the structure in the inside of the resin part of FIG. 図１９の破線部ＸＸの概略拡大図である。It is a schematic enlarged view of the broken line part XX of FIG.

符号の説明Explanation of symbols

Ａ１ 第１の頂点、Ａ２ 第２の頂点、ＢＢ バスバー、ＢＬ はんだボール、ＢＰ，ＱＰ パッケージ、ＣＢ 回路基板、ＣＨ 半導体チップ、ＣＰ 接続部、ＣＶ キャビティ、ＤＰ ダイパッド、ＥＬ 電極、Ｆ 屈曲点、ＧＲ 接地リング、ＩＬ インナーリード部（電極）、Ｌ１ 第１の辺、Ｌ２ 第２の辺、ＬＦ リードフレーム、ＭＬ 金型、ＭＬａ 上金型、ＭＬｂ 下金型、ＭＲ，ＭＲｂ 樹脂部、ＯＬ アウターリード部（電極）、ＰＤ ボンディングパッド、ＰＤ１ 内周ボンディングパッド、ＰＤ２ 外周ボンディングパッド、ＳＬ 吊リード、ＳＴ，ＳＴ１，ＳＴ２ 屈曲部、ＷＲ ボンディングワイヤ、ＷＲ１ 内周ボンディングワイヤ、ＷＲ２ 外周ボンディングワイヤ、ＷＺ ボンディングワイヤ。   A1 first vertex, A2 second vertex, BB bus bar, BL solder ball, BP, QP package, CB circuit board, CH semiconductor chip, CP connection, CV cavity, DP die pad, EL electrode, F bending point, GR Ground ring, IL inner lead part (electrode), L1 first side, L2 second side, LF lead frame, ML mold, MLa upper mold, MLb lower mold, MR, MRb resin part, OL outer lead Part (electrode), PD bonding pad, PD1 inner periphery bonding pad, PD2 outer periphery bonding pad, SL suspension lead, ST, ST1, ST2 bent portion, WR bonding wire, WR1 inner periphery bonding wire, WR2 outer periphery bonding wire, WZ bonding wire .

Claims (4)

互いに対角線上にある第１および第２の頂点と前記第１および第２の頂点を繋ぐ第１および第２の辺とを有する長方形状の主面を有し、かつ前記主面上に第１のパッドを有する半導体チップと、電極と、前記第１のパッドと前記電極とを接続するワイヤと、前記ワイヤを封止する樹脂部とを含む半導体装置の製造方法であって、
前記第１のパッドと前記電極との間に前記ワイヤを形成する工程と、
金型のキャビティ内に前記ワイヤを収める工程と、
前記第１の頂点から前記第１および第２の辺に沿って前記第２の頂点に向かうように前記キャビティ内に液状樹脂を流し込む工程と、
前記液状樹脂を硬化することによって前記樹脂部を形成する工程とを備え、
前記ワイヤを形成する工程は、平面視において、前記第１のパッドと前記電極とを結んだ直線に対して前記第１の頂点から遠い側を通るように前記ワイヤを形成することにより行なわれる、半導体装置の製造方法。 A rectangular main surface having first and second vertices that are diagonal to each other and first and second sides connecting the first and second vertices; and a first on the main surface A method of manufacturing a semiconductor device, comprising: a semiconductor chip having a plurality of pads; an electrode; a wire connecting the first pad and the electrode; and a resin portion for sealing the wire.
Forming the wire between the first pad and the electrode;
Placing the wire in a mold cavity;
Pouring a liquid resin into the cavity from the first vertex toward the second vertex along the first and second sides;
Forming the resin part by curing the liquid resin,
The step of forming the wire is performed by forming the wire so as to pass through a side farther from the first vertex with respect to a straight line connecting the first pad and the electrode in a plan view. A method for manufacturing a semiconductor device. 前記半導体チップは前記主面上に設けられた第２のパッドを含み、前記第２のパッドと前記主面の外縁との間隔は前記第１のパッドと前記外縁との間隔に比して小さい、請求項１に記載の半導体装置の製造方法。   The semiconductor chip includes a second pad provided on the main surface, and a distance between the second pad and the outer edge of the main surface is smaller than a distance between the first pad and the outer edge. A method for manufacturing a semiconductor device according to claim 1. 前記電極は、前記樹脂部から突出した部分を有する、請求項１または２に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the electrode has a portion protruding from the resin portion. 前記半導体装置は、前記半導体チップおよび前記電極の各々を支持する回路基板を含む、請求項１または２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a circuit board that supports each of the semiconductor chip and the electrode.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013197426A (en) * 2012-03-22 2013-09-30 Renesas Electronics Corp Manufacturing method of semiconductor device and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013197426A (en) * 2012-03-22 2013-09-30 Renesas Electronics Corp Manufacturing method of semiconductor device and semiconductor device

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