JP2010114401A - リードフレームの内部接続構造、及び、その接続方法 - Google Patents
リードフレームの内部接続構造、及び、その接続方法 Download PDFInfo
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- JP2010114401A JP2010114401A JP2008318106A JP2008318106A JP2010114401A JP 2010114401 A JP2010114401 A JP 2010114401A JP 2008318106 A JP2008318106 A JP 2008318106A JP 2008318106 A JP2008318106 A JP 2008318106A JP 2010114401 A JP2010114401 A JP 2010114401A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000010409 thin film Substances 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000009434 installation Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 4
- 239000010408 film Substances 0.000 abstract 2
- 239000003086 colorant Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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Abstract
【解決手段】リードフレームの内部接続構造は、複数のリード10、10’と、一部のリードの第一表面に設置される絶縁薄膜20と、絶縁薄膜上に設置されて、一部のリードの第一表面を露出する複数の開口22と、絶縁薄膜を露出するリードに選択的に電気的接続される少なくとも一つの導電素子30と、からなる。リードフレームの内部接続方法は、絶縁薄膜により、導電素子とリードフレームを隔離して、リードフレームの接続を行う。
【選択図】図1
Description
20 絶縁薄膜
22 開口
30 導電素子
40 チップ
Claims (10)
- リードフレームの内部接続構造であって、
複数のリードと、
一部の前記リードの第一表面に設置される絶縁薄膜と、
前記絶縁薄膜上に設置されて、一部の前記リードの前記第一表面を露出する複数の開口と、
前記絶縁薄膜を露出する前記リードに選択的に電気的接続される少なくとも一つの導電素子と、
からなることを特徴とするリードフレームの内部接続構造。 - 前記絶縁薄膜は絶縁テープであることを特徴とする請求項1に記載のリードフレームの内部接続構造。
- 前記導電素子は金属線と金属ペーストであることを特徴とする請求項1または請求項2に記載のリードフレームの内部接続構造。
- 前記リードの長さは異なっていてもよいことを特徴とする請求項1から請求項3の何れかに記載のリードフレームの内部接続構造。
- 前記第一表面は前記リードの上表面か下表面であることを特徴とする請求項1から請求項4の何れかに記載のリードフレームの内部接続構造。
- リードフレームの内部接続方法であって、
複数のリードを有するリードフレームを提供する工程と、
絶縁薄膜を一部の前記リードの第一表面に設置し、前記絶縁薄膜上に複数の開口を有して、一部の前記リードの前記第一表面を露出する工程と、
少なくとも一つの導電素子を形成し、前記絶縁薄膜を露出する前記リードを選択的に電気的接続する工程と、
からなることを特徴とするリードフレームの内部接続方法。 - 前記開口は前記絶縁薄膜製作時に一緒に形成することを特徴とする請求項6に記載のリードフレームの内部接続方法。
- 前記絶縁薄膜設置工程後、更に、開孔工程を有し、前記開口を前記絶縁薄膜上に形成することを特徴とする請求項6または請求項7に記載のリードフレームの内部接続方法。
- 前記第一表面は前記リードの上表面か下表面であることを特徴とする請求項6から請求項8の何れかに記載のリードフレームの内部接続方法。
- 前記導電素子の形成方法はワイヤーボンディングと塗布方法があることを特徴とする請求項6から請求項9の何れかに記載のリードフレームの内部接続方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097142571 | 2008-11-04 | ||
TW097142571A TW201019450A (en) | 2008-11-04 | 2008-11-04 | Inner-connecting structure of lead frame and its connecting method |
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JP2010114401A true JP2010114401A (ja) | 2010-05-20 |
JP5240610B2 JP5240610B2 (ja) | 2013-07-17 |
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JP2008318106A Active JP5240610B2 (ja) | 2008-11-04 | 2008-12-15 | リードフレームのインナーリード同士の接続構造 |
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US (1) | US8040690B2 (ja) |
JP (1) | JP5240610B2 (ja) |
TW (1) | TW201019450A (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US8580675B2 (en) * | 2011-03-02 | 2013-11-12 | Texas Instruments Incorporated | Two-track cross-connect in double-patterned structure using rectangular via |
ITTO20150231A1 (it) | 2015-04-24 | 2016-10-24 | St Microelectronics Srl | Procedimento per produrre lead frame per componenti elettronici, componente e prodotto informatico corrispondenti |
JP6352876B2 (ja) * | 2015-09-15 | 2018-07-04 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
Citations (7)
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JPH02177354A (ja) * | 1988-12-27 | 1990-07-10 | Matsushita Electric Ind Co Ltd | 半導体素子 |
JPH03238854A (ja) * | 1990-02-15 | 1991-10-24 | Ibiden Co Ltd | 半導体装置 |
JPH0474461A (ja) * | 1990-07-17 | 1992-03-09 | Shinko Electric Ind Co Ltd | リードフレーム |
JPH0529159U (ja) * | 1991-09-24 | 1993-04-16 | ローム株式会社 | 電子部品用リードフレームの構造 |
JPH11289043A (ja) * | 1998-04-01 | 1999-10-19 | Nec Corp | 半導体集積回路装置 |
JP2001024136A (ja) * | 2000-01-01 | 2001-01-26 | Seiko Epson Corp | 半導体集積装置 |
JP2004158753A (ja) * | 2002-11-08 | 2004-06-03 | Sony Corp | リードフレーム材及びその製造方法、並びに半導体装置及びその製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5036380A (en) * | 1988-03-28 | 1991-07-30 | Digital Equipment Corp. | Burn-in pads for tab interconnects |
US5337216A (en) * | 1992-05-18 | 1994-08-09 | Square D Company | Multichip semiconductor small outline integrated circuit package structure |
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- 2008-12-15 JP JP2008318106A patent/JP5240610B2/ja active Active
- 2008-12-22 US US12/341,334 patent/US8040690B2/en active Active
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US20100110654A1 (en) | 2010-05-06 |
JP5240610B2 (ja) | 2013-07-17 |
TW201019450A (en) | 2010-05-16 |
US8040690B2 (en) | 2011-10-18 |
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