JP2010087502A - メモリデバイスを実現する積層チップパッケージ - Google Patents
メモリデバイスを実現する積層チップパッケージ Download PDFInfo
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- JP2010087502A JP2010087502A JP2009207677A JP2009207677A JP2010087502A JP 2010087502 A JP2010087502 A JP 2010087502A JP 2009207677 A JP2009207677 A JP 2009207677A JP 2009207677 A JP2009207677 A JP 2009207677A JP 2010087502 A JP2010087502 A JP 2010087502A
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Abstract
【解決手段】積層チップパッケージ1は、本体2と、本体2の側面に配置された配線3A,3Bとを備えている。本体2は、それぞれ第1の種類の半導体チップを含む複数の第1の種類の階層部分12〜18と、第2の種類の半導体チップを含む第2の種類の階層部分11とを含んでいる。第1の種類の半導体チップは、複数のメモリセルを含んでいる。第2の種類の半導体チップは、複数の第1の種類の階層部分に含まれる複数のメモリセルに対する書き込みと読み出しを制御する回路を含んでいる。各階層部分は、半導体チップの少なくとも1つの側面を覆う絶縁部と、半導体チップに接続された複数の電極とを含んでいる。各電極の端面は、本体2の側面に配置され、配線3A,3Bに接続されている。
【選択図】図1
Description
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1を参照して、本発明の第1の実施の形態に係る積層チップパッケージの構成について説明する。図1は、本実施の形態に係る積層チップパッケージの斜視図である。図1に示したように、本実施の形態に係る積層チップパッケージ1は、直方体形状の本体2を備えている。本体2は、上面2a、下面2b、互いに反対側を向いた第1の側面2cおよび第2の側面2d、ならびに互いに反対側を向いた第3の側面2eおよび第4の側面2fを有している。
次に、本発明の第2の実施の形態について説明する。本実施の形態に係る積層チップパッケージ1では、本体2の4つの側面2c〜2fは、配線3が配置された少なくとも1つの第1の種類の側面と、配線3が配置されていない少なくとも1つの第2の種類の側面とを含んでいる。本実施の形態に係る積層チップパッケージ1の外観は、例えば、第1の実施の形態と同様に、図1に示したようになる。この例では、本体2の4つの側面2c〜2fのうち、側面2c,2dが第1の種類の側面であり、側面2e,2fが第2の種類の側面である。
次に、本発明の第3の実施の形態について説明する。始めに、図36を参照して、本実施の形態に係る電子部品の構成について説明する。図36は、本実施の形態に係る電子部品の斜視図である。図37は、図36に示した電子部品の分解斜視図である。本実施の形態に係る電子部品は、フラッシュメモリ、DRAM、SRAM、MRAM、PROM、FeRAM等のメモリデバイスを実現するものである。
次に、図40および図41を参照して、本発明の第4の実施の形態について説明する。図40は、本実施の形態に係る積層チップパッケージの斜視図である。図41は、下面側から見た図40の積層チップパッケージを示す斜視図である。
次に、図42および図43を参照して、本発明の第5の実施の形態について説明する。図42は、本実施の形態に係る電子部品の一態様を示す斜視図である。図43は、本実施の形態に係る電子部品の他の態様を示す斜視図である。本実施の形態に係る電子部品は、フラッシュメモリ、DRAM、SRAM、MRAM、PROM、FeRAM等のメモリデバイスを実現するものである。
Claims (12)
- 上面、下面および4つの側面を有する本体と、
前記本体の少なくとも1つの側面に配置された配線とを備え、
前記本体は、積層された複数の階層部分を含み、
前記複数の階層部分は、それぞれ第1の種類の半導体チップを含む複数の第1の種類の階層部分と、第2の種類の半導体チップを含む第2の種類の階層部分とを含み、
前記第1の種類の半導体チップは、複数のメモリセルを含み、
前記第2の種類の半導体チップは、前記複数の第1の種類の階層部分に含まれる複数のメモリセルに対する書き込みと読み出しを制御する回路を含み、
前記第1の種類の半導体チップと前記第2の種類の半導体チップは、いずれも、上面、下面および4つの側面を有し、
前記複数の階層部分の各々は、前記第1の種類または第2の種類の半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部と、前記第1の種類または第2の種類の半導体チップに接続された複数の電極とを含み、
前記絶縁部は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有し、
前記複数の電極の各々は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置され且つ前記絶縁部によって囲まれた端面を有し、
前記配線は、前記複数の階層部分における複数の電極の端面に接続されていることを特徴とする積層チップパッケージ。 - 前記第1の種類の半導体チップは、更に、そこに含まれる複数のメモリセルのみに関係する回路を含むことを特徴とする請求項1記載の積層チップパッケージ。
- 更に、前記本体の上面と下面の少なくとも一方に配置され、前記配線に接続された複数の端子を備えたことを特徴とする請求項1記載の積層チップパッケージ。
- 前記本体の4つの側面は、前記配線が配置された少なくとも1つの第1の種類の側面と、前記配線が配置されていない少なくとも1つの第2の種類の側面とを含み、
前記第1の種類または第2の種類の半導体チップの4つの側面は、前記本体の前記少なくとも1つの第1の種類の側面との間に前記絶縁部が配置された少なくとも1つの第1の種類の側面と、前記本体の前記少なくとも1つの第2の種類の側面に配置された少なくとも1つの第2の種類の側面とを含むことを特徴とする請求項1記載の積層チップパッケージ。 - 積層チップパッケージと、前記積層チップパッケージに接合された回路層とを備えた電子部品であって、
前記積層チップパッケージは、上面、下面および4つの側面を有する本体と、前記本体の少なくとも1つの側面に配置された配線とを備え、
前記本体は、積層された複数の階層部分を含み、
前記複数の階層部分の各々は、上面、下面および4つの側面を有すると共に複数のメモリセルを含む半導体チップと、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部と、前記半導体チップに接続された複数の電極とを含み、
前記絶縁部は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有し、
前記複数の電極の各々は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置され且つ前記絶縁部によって囲まれた端面を有し、
前記配線は、前記複数の階層部分における複数の電極の端面に接続され、
前記回路層は、前記積層チップパッケージの前記配線に接続されて、前記複数の階層部分に含まれる複数のメモリセルに対する書き込みと読み出しを制御する回路を含むことを特徴とする電子部品。 - 前記半導体チップは、更に、そこに含まれる複数のメモリセルのみに関係する回路を含むことを特徴とする請求項5記載の電子部品。
- 前記積層チップパッケージは、更に、前記本体の上面と下面の少なくとも一方に配置され、前記配線に接続された複数の端子を備え、前記回路層は、前記複数の端子に接続されていることを特徴とする請求項5記載の電子部品。
- 前記本体の4つの側面は、前記配線が配置された少なくとも1つの第1の種類の側面と、前記配線が配置されていない少なくとも1つの第2の種類の側面とを含み、
前記半導体チップの4つの側面は、前記本体の前記少なくとも1つの第1の種類の側面との間に前記絶縁部が配置された少なくとも1つの第1の種類の側面と、前記本体の前記少なくとも1つの第2の種類の側面に配置された少なくとも1つの第2の種類の側面とを含むことを特徴とする請求項5記載の電子部品。 - 積層された複数の積層チップパッケージと、前記複数の積層チップパッケージのうちの1つに接合され且つ電気的に接続された回路層とを備えた電子部品であって、
上下に隣接する2つの積層チップパッケージは、互いに電気的に接続され、
前記複数の積層チップパッケージの各々は、上面、下面および4つの側面を有する本体と、前記本体の少なくとも1つの側面に配置された配線とを備え、
前記本体は、積層された複数の階層部分を含み、
前記複数の階層部分の各々は、上面、下面および4つの側面を有すると共に複数のメモリセルを含む半導体チップと、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部と、前記半導体チップに接続された複数の電極とを含み、
前記絶縁部は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有し、
前記複数の電極の各々は、前記配線が配置された前記本体の前記少なくとも1つの側面に配置され且つ前記絶縁部によって囲まれた端面を有し、
前記配線は、前記複数の階層部分における複数の電極の端面に接続され、
前記回路層は、複数の前記積層チップパッケージに含まれる複数のメモリセルに対する書き込みと読み出しを制御する回路を含むことを特徴とする電子部品。 - 前記半導体チップは、更に、そこに含まれる複数のメモリセルのみに関係する回路を含むことを特徴とする請求項9記載の電子部品。
- 前記複数の積層チップパッケージの各々は、更に、前記本体の上面に配置され、前記配線に接続された複数の第1の端子と、前記本体の下面に配置され、前記配線に接続された複数の第2の端子とを備え、
前記上下に隣接する2つの積層チップパッケージにおいて、下側の積層チップパッケージの複数の第1の端子と上側の積層チップパッケージの複数の第2の端子とが電気的に接続されていることを特徴とする請求項9記載の電子部品。 - 前記本体の4つの側面は、前記配線が配置された少なくとも1つの第1の種類の側面と、前記配線が配置されていない少なくとも1つの第2の種類の側面とを含み、
前記半導体チップの4つの側面は、前記本体の前記少なくとも1つの第1の種類の側面との間に前記絶縁部が配置された少なくとも1つの第1の種類の側面と、前記本体の前記少なくとも1つの第2の種類の側面に配置された少なくとも1つの第2の種類の側面とを含むことを特徴とする請求項9記載の電子部品。
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