JP2010067130A - Watchdog timer circuit and electronic control device of gas stove - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a watchdog timer circuit for preventing any malfunction from occurring even when both of a positive noise pulse and a negative noise pulse are imposed on an input clock signal, and any noise bursts in the middle of a circuit. <P>SOLUTION: The pre-stage of a watchdog logic (15) includes: a first delay sensitive circuit (11) having an insensitive time at the rising of an input signal to which a clock signal with a prescribed frequency is input; a second delay sensitive circuit (12) having an insensitive time at the falling of the input signal to which the output signal of the first delay sensitive circuit is input; and a matching detection circuit (13) for detecting the logic matching of the output signal of the second delay sensitive circuit and the clock signal, and for, when the logic matching is detected, outputting a prescribed logic signal, wherein the insensitive time Td2 of the second delay sensitive circuit (12) is set to be longer than the insensitive time Td1 of the first delay sensitive circuit (11). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a watchdog timer circuit for monitoring a clock signal, and more particularly to a watchdog timer circuit suitable for application to an electronic control device of a device that generates relatively large electromagnetic noise such as a gas stove.

  2. Description of the Related Art Conventionally, in an electronic control system using a microcomputer, a watchdog timer circuit is provided to monitor the operation of the microcomputer and activate a fail-safe function when an abnormality occurs. Under normal conditions, the watchdog timer circuit is reset repeatedly by a program with a cycle shorter than the monitoring period. However, if a malfunction occurs in the microcomputer due to a program runaway, an alarm (alarm signal) ).

An example of an electronic control system equipped with such a watchdog timer circuit is a gas stove control device. This is because the gas stove has an ignition circuit (igniter), and a relatively large electromagnetic noise is generated at the time of discharge by the igniter, thereby possibly causing the microcomputer program to run out of control and preventing it. In a watchdog timer circuit provided in a gas stove control device, there is an invention described in Patent Document 1 as an invention devised so as not to cause a malfunction even if noise is included in an input signal (clock signal).
JP 2000-276378 A

  The watchdog timer circuit described in Patent Document 1 is configured to monitor a periodic clock signal supplied from a microcomputer, and malfunctions when a noise pulse is applied to the input clock signal. An integration circuit for removing noise is provided so as not to cause noise. However, the above circuit can remove noise when a positive noise pulse is present in the clock signal. However, when a negative noise pulse is present when the input signal is high level, It has been found that there is a problem that malfunction cannot be prevented when noise enters.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is when the input clock signal has a positive noise pulse or a negative noise pulse. Another object is to provide a watchdog timer circuit that does not cause malfunction.

  Another object of the present invention is to provide a watchdog timer circuit which does not cause a malfunction even if noise jumps in the middle of the circuit.

  In order to achieve the above object, the present invention has a first delay sensitive circuit that has a dead time at the rising edge of an input signal and receives a clock signal having a predetermined period, and has a dead time at the falling edge of the input signal. The second delay sensitive circuit to which the output signal of the first delay sensitive circuit is input, and the logic coincidence of the output signal of the second delay sensitive circuit and the clock signal are detected. A coincidence detection circuit that outputs a signal of the above logic, and a watchdog logic that periodically resets the interior by a periodic input and outputs an alarm signal when the periodic input disappears, and the second delay The insensitive time of the sensitive circuit is set longer than the insensitive time of the first delay sensitive circuit, and a signal corresponding to the output of the coincidence detecting circuit is supplied to the watchdog logic as a periodic input. It is those that you have configured.

  According to the above configuration, when a positive noise pulse is present on the input clock signal, the noise is removed by the first delay sensitive circuit having the insensitive time at the rising edge, and the input clock signal is negative. When a noise pulse is present, the noise is removed by the second delay sensitive circuit having a dead time at the falling edge, and the noise does not appear in the output signal.

  Preferably, a noise removal circuit for removing noise from the output of the coincidence detection circuit is provided at a subsequent stage of the coincidence detection circuit, and the output of the coincidence detection circuit is input to the watchdog logic through the noise removal circuit. Configure as follows. Thereby, noise jumping in the middle of the circuit can be removed.

  Further preferably, the second delay sensitive circuit has the same configuration as the inverter that inverts the output of the first delay sensitive circuit and the first delay sensitive circuit that has a dead time at the rising edge of the input signal. And a circuit to which the output of the inverter is input. This facilitates circuit design.

  The delay sensitive circuit includes an inverter that inverts an input signal, a constant current source and a capacitor connected in series between a power supply voltage terminal and a ground point, and an output signal of the inverter received at a base terminal. And a grounded-emitter transistor, and a circuit in which a collector of the transistor is coupled to a connection node between the constant current source and the capacitor is used. Thereby, it is possible to realize a delay sensitive circuit having a dead time with a relatively simple circuit.

  According to the present invention, there is provided a watchdog timer circuit that does not cause a malfunction even when both a positive noise pulse and a negative noise pulse are present on the input clock signal or when noise jumps in the middle of the circuit. There is an effect that it can be realized.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment of a watchdog timer circuit according to the present invention.

  The watchdog timer circuit of the present embodiment includes a first delay sensitive circuit 11 in which a periodic clock signal CLK such as 1 kHz supplied from a microcomputer or the like is input to an input terminal IN, and a first delay sensitive circuit. A logic match between the second delay sensitive circuit 12 to which the output signal of the circuit 11 is input and the output signal of the second delay sensitive circuit 12 and the clock signal CLK input to the input terminal IN are detected and matched. In this case, it is composed of a coincidence detection circuit 13 that outputs a signal of a predetermined logic, a noise removal circuit 14, and a watchdog logic 15. Although not particularly limited, each of these circuits is formed as a semiconductor integrated circuit on one semiconductor chip.

  The first delay sensitive circuit 11 is configured to be immediately sensitive to the falling edge of the input signal and to be sensitive to the rising edge of the input signal with a delay of a predetermined time Td1 (for example, 100 μs). The second delay sensitive circuit 12 immediately responds to the rising edge of the input signal (output of the first delay sensitive circuit) and senses the falling edge of the input signal with a delay of a predetermined time Td2 (for example, 200 μs). This is a circuit configured as described above. In the present embodiment, the insensitive delay times Td1 and Td2 are set so that Td2> Td1. By interposing an inverter between the first delay sensitive circuit 11 and the second delay sensitive circuit 12, the first delay sensitive circuit is sensitive to the second delay sensitive circuit 12 with a delay from the rising of the input signal. 11 can be used.

  FIG. 2 shows a specific circuit configuration example of the watchdog timer circuit of the above embodiment.

  As shown in FIG. 2, the first delay sensitive circuit 11 includes an inverter INV1 that inverts an input signal (clock signal CLK), and an emitter-grounded bipolar in which an output of the inverter INV1 is input to a base terminal. A transistor Q1, a constant current source CS1 and a capacitor C1 connected in series between the power supply voltage terminal VCC and the ground point, and a collector node of the transistor Q1 is a connection node N1 between the constant current source CS1 and the capacitor C1. Is bound to. The delay time Td1 is determined by the current value of the constant current source CS1 and the capacitance value of the capacitor C1.

  The second delay sensitive circuit 12 includes inverters INV2 and INV3 that invert the output signal of the first delay sensitive circuit 11, and an emitter-grounded npn bipolar transistor Q2 whose output is input to the base terminal. A constant current source CS2 and a capacitor C2 connected in series between the power supply voltage terminal VCC and the ground point, and a collector terminal of the transistor Q2 is coupled to a connection node N2 between the constant current source CS2 and the capacitor C2. Yes. The circuit portion including the inverter INV3, the bipolar transistor Q2, the constant current source CS2, and the capacitor C2 has the same configuration as that of the first delay sensitive circuit 11.

  As described above, the inverter INV2 is provided in the preceding stage of the circuit having the same configuration as the first delay sensitive circuit 11 that is sensitive to the rise of the input signal, thereby providing the second delay sensitive that is sensitive to the fall of the input signal. Circuit 12 is implemented. Instead of providing the inverter INV2, a second delay sensitive circuit that has a configuration in which the first delay sensitive circuit 11 is turned upside down and uses a pnp transistor instead of the npn transistor is sensitive to the falling edge of the input signal. It may be used as a circuit.

  The insensitive time Td2 of the second delay sensitive circuit 12 is determined by the current value of the constant current source CS2 and the capacitance value of the capacitor C2. Therefore, the condition of Td2> Td1 can be satisfied by appropriately setting one or both of the current value of the constant current source and the capacitance value of the capacitor. For example, when C1 = C2, I1> I2 is set, and when I1 = I2, C1 <C2 is set.

  The coincidence detection circuit 13 is composed of, for example, a NOR logic gate circuit, and the noise removal circuit 14 is composed of a capacitive element C3. As a logic gate circuit using a bipolar transistor as a transistor, for example, as shown in FIG. 3, a circuit composed of differential transistors Q3 and Q4, an output transistor Q5, a constant current source CS3, and the like can be used.

  As shown in FIG. 4, the watchdog logic 15 includes a D-type flip-flop FF1, an npn bipolar transistor Q6 having a grounded emitter and an output of the FF1 input to the base terminal, a power supply voltage terminal VCC, and a ground point. A constant current source CS5 and a capacitor C4 connected in series, and a comparator CMP to which a potential V3 of a connection node N3 between the constant current source CS5 and the capacitor C4 is input, and between the node N3 and the ground point A resistor R1 and a transistor Q6 are connected in series.

  The comparator CMP has two comparison values Vth1 and Vth2 (Vth1 <Vth2). When the input voltage falls below Vth1, the comparator CMP outputs a signal for resetting the flip-flop FF1, and when the input voltage exceeds Vth2, an alarm is issued. The signal ALM is configured to be output.

  Next, the operation of the circuit of FIG. 2 will be described.

  As shown in FIG. 5A, when a square-wave clock signal CLK is input as an input signal, the potential V1 of the node N1 in the first delay sensitive circuit 11 is changed to a clock as shown in FIG. Almost in phase with CLK, the falling edge changes sharply and the rising edge changes slowly. On the other hand, the potential V2 of the node N2 in the second delay sensitive circuit 12 has a phase opposite to that of the clock CLK, as shown in FIG. 5C, and falls sharply with a delay of Td1 from the rise of CKL. When falling, it changes so as to rise more gently than the rising of V1.

  As a result, the output of the logic gate circuit 13 becomes a high level only during the period T3 when the clock CLK and the potential V2 of the node N2 overlap, the flip-flop FF1 is set, Q6 is turned on, and the potential V3 of the node N3 starts to decrease. When the value becomes lower than the comparison value Vth1 of the comparator CMP, the flip-flop FF1 is reset. Then, Q6 is turned off and the potential V3 of the node N3 starts to rise (period T4).

  If the cycle of the clock CLK is normal, the output of the logic gate circuit 13 (FIG. 3D) becomes high level and the potential V3 of the node N3 decreases before V3 reaches the comparison value Vth2 of the comparator CMP. When the clock CLK does not enter, the potential V3 of the node N3 continues to rise and reaches the comparison value Vth2 as indicated by a broken line in FIG. Then, the comparator CMP outputs an alarm signal ALM to reset the microcomputer, or in the control of the gas stove, the actuator for opening and closing the gas control valve is turned off, and the valve is closed by the return force of the spring, etc. Works to work.

  When a positive noise pulse is present on the input signal clock CLK (at low level) as shown in FIG. 6A, the noise pulse width is the sensitive delay time of the first delay sensitive circuit 11. If it is smaller than Td1, as shown in FIG. 6B, the potential V1 of the node N1 in the first delay sensitive circuit 11 is not affected by noise. Therefore, as shown in FIG. 6D, the output of the logic gate circuit 13 is not affected by noise, so that the watchdog logic 15 in the subsequent stage does not malfunction.

  Further, when a negative noise pulse is applied to the input signal clock CLK (at the high level) as shown in FIG. 7A, the noise is amplified by the first delay sensitive circuit 11. When the pulse width is smaller than the sensitive delay time Td2 of the second delay sensitive circuit 12, the second delay sensitive circuit 12 is transmitted to the second delay sensitive circuit 12 as shown in FIG. The potential V2 of the node N2 is not affected by noise. Therefore, as shown in FIG. 7D, the output of the logic gate circuit 13 is not affected by noise, so that the subsequent watchdog logic 15 does not malfunction. Further, since Td1 <td2 is set, the negative pulse noise amplified without being removed by the first delay sensitive circuit 11 is removed by the second delay sensitive circuit 12, so that the positive delay included in the input is included. The sensitivity to pulse noise and negative pulse noise does not differ greatly.

  Further, in the case where noise jumps into the base of the transistor Q2 in the second delay sensitive circuit 12 as shown in FIG. 8B during the period when the clock CLK that is the input signal is low level, as shown in FIG. 8C. The increased noise appears in the potential V2 of the node N2 in the second delay sensitive circuit 12, but the noise is absorbed because the subsequent logic gate circuit 13 takes the logical product of V2 and the input signal. As shown in (D), the influence of the noise does not appear in the output of the logic gate circuit 13.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments. For example, in the above-described embodiment, the noise removal circuit 14 is provided after the coincidence detection circuit 13, but the noise removal circuit 14 may be omitted. This is because noise that jumps in the middle of a circuit can be blocked by providing, for example, an electromagnetic shield around the circuit, whereas noise on an input signal is difficult to sufficiently block by an electromagnetic shield. .

  In the above description, the case where the invention made mainly by the present inventor is applied to the watchdog timer provided in the electronic control device of the gas stove which is the field of use which has been the background has been described. However, the present invention is not limited thereto. In addition, the present invention can be used for a control system of an electronic device in which noise is likely to be generated such as a cooking range of food, an in-vehicle engine control system, and the like.

It is a block diagram which shows schematic structure of one Embodiment of the watchdog timer circuit based on this invention. It is a circuit diagram which shows the specific circuit structural example of the watchdog timer circuit of embodiment. It is a circuit diagram which shows the specific example of the logic gate circuit as a coincidence detection circuit. It is a circuit block diagram which shows the specific example of watchdog logic. 5 is a time chart showing a change in potential of a node inside a watchdog timer circuit when a square wave clock signal is inputted as an input signal. It is a time chart which shows the change of the electric potential of the node in a watchdog timer circuit in case the positive noise has carried in the input signal. It is a time chart which shows the change of the electric potential of the node inside a watchdog timer circuit when the negative noise is carried in the input signal. It is a time chart which shows the change of the electric potential of the node inside a watchdog timer circuit when noise jumps into the 2nd delay sensitive circuit.

Explanation of symbols

11 first delay sensitive circuit 12 second delay sensitive circuit 13 coincidence detection circuit (logic gate circuit)
14 Noise reduction circuit 15 Watchdog logic

Claims (5)

A first delay sensitive circuit having a dead time at the rising edge of the input signal and receiving a clock signal having a predetermined period;
A second delay sensitive circuit having a dead time at the falling edge of the input signal and receiving the output signal of the first delay sensitive circuit;
A coincidence detection circuit that detects a logic match between the output signal of the second delay sensitive circuit and the clock signal, and outputs a signal of a predetermined logic when they match,
A watchdog logic that periodically resets the interior by periodic input and outputs an alarm signal when there is no periodic input;
The delay insensitive time of the second delay sensitive circuit is set longer than the insensitive time of the first delay sensitive circuit, and a signal corresponding to the output of the coincidence detection circuit is periodically sent to the watchdog logic. Watchdog timer circuit, characterized in that it is supplied as a simple input.   A noise removal circuit for removing noise from the output of the coincidence detection circuit is provided at a subsequent stage of the coincidence detection circuit, and the output of the coincidence detection circuit is input to the watchdog logic through the noise removal circuit. The watchdog timer circuit according to claim 1.   The second delay sensitive circuit has the same configuration as the inverter that inverts the output of the first delay sensitive circuit and the first delay sensitive circuit that has a dead time at the rising edge of the input signal. 3. The watch dog timer circuit according to claim 1, further comprising a circuit to which an output is input.   The delay sensitive circuit includes an inverter that inverts an input signal, a constant current source and a capacitive element connected in series between a power supply voltage terminal and a ground point, and a grounded emitter that receives an output signal of the inverter at a base terminal. The watchdog timer circuit according to claim 1, further comprising a transistor, wherein a collector of the transistor is coupled to a connection node between the constant current source and the capacitor.   5. A gas control system comprising: the watchdog timer circuit according to claim 1; and a microcomputer that supplies the clock signal to the watchdog timer circuit, and the output of the watchdog timer circuit is not in a predetermined state. An electronic control device for a gas stove characterized by a fail-safe function for closing a valve.

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