KR960025734A - Refresh control method of semiconductor device and device therefor - Google Patents

Refresh control method of semiconductor device and device therefor Download PDF

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Publication number
KR960025734A
KR960025734A KR1019940032626A KR19940032626A KR960025734A KR 960025734 A KR960025734 A KR 960025734A KR 1019940032626 A KR1019940032626 A KR 1019940032626A KR 19940032626 A KR19940032626 A KR 19940032626A KR 960025734 A KR960025734 A KR 960025734A
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KR
South Korea
Prior art keywords
signal
standby state
semiconductor device
dram
ras
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KR1019940032626A
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Korean (ko)
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KR0138700B1 (en
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황용
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김주용
현대전자산업 주식회사
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Priority to KR1019940032626A priority Critical patent/KR0138700B1/en
Publication of KR960025734A publication Critical patent/KR960025734A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 반도체 장치의 리프레쉬 제어방법 및 그 장치에 관한 것으로, 상기 디램의 대기상태가 오래 지속될 경우 정상적인 리플레쉬 동작이 수행되는데 이로 인하여 전류소모가 리플레쉬 사이클에 따라 발생하게 되는 것을 방지하기 위하여 상기 디램이 장시간동안 대기상태를 유지할 경우에 상기 디램의 대기상태를 검출하여 리플레쉬 사이클 주기를 조절함으로써, 전류소모를 줄이도록 한 반도체 장치의 리프레쉬 제어방법 및 그 장치에 관한 것이다.The present invention relates to a method for controlling a refresh of a semiconductor device and a device thereof, in which a normal refresh operation is performed when the standby state of the DRAM continues for a long time, thereby preventing current consumption from occurring according to a refresh cycle. The present invention relates to a method for controlling a refresh of a semiconductor device which reduces current consumption by detecting a standby state of the DRAM and adjusting a refresh cycle period when the DRAM maintains a standby state for a long time.

Description

반도체 장치의 리프레쉬 제어방법 및 그 장치Refresh control method of semiconductor device and device therefor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 리프레쉬 제어장치를 도시한 회로도1 is a circuit diagram showing a refresh control device according to the present invention.

Claims (8)

반도체 장치의 디램의 대기상태를 감지하여 리프레쉬 주기를 조절하는 방법에 있어서, 카스신호(/CAS)및 라스신호(/RAS)를 입력단자로 입력하는 과정과 상기 입력단자로부터 입력된 신호에 의해 디램의 액티브 상태 및 대기상태를 감지하는 과정과, 상기 디램이 대기상태인 경우 일정한 주기를 갖는 클럭 신호를 발생시키는 과정과, 상기 클럭 신호를 카운트하여 리프레쉬 모드를 지정하는 신호를 발생시키는 과정을 포함하는 것을 특징으로 하는 반도체 장치의 리프레쉬 제어방법.A method of adjusting a refresh period by sensing a standby state of a DRAM of a semiconductor device, the method comprising: inputting a cas signal (/ CAS) and a ras signal (/ RAS) to an input terminal and a DRAM by a signal input from the input terminal. Detecting an active state and a standby state of the memory, generating a clock signal having a predetermined period when the DRAM is in a standby state, and generating a signal specifying a refresh mode by counting the clock signal; The refresh control method of the semiconductor device characterized by the above-mentioned. 제1항에 있어서, 상기 카운트 수단의 출력신호 및 상기 감지수단의 출력신호를 입력으로하여 상기 감지수단으로부터 디램이 대기상태에 있을 경우 대기상태가 시작된후 일정시간 뒤에 상기 대기상태를 검출하는 신호를 출력하는 과정을 추가로 포함하는 것을 특징으로 하는 반도체 장치의 리프레쉬 제어방법The method of claim 1, wherein the output signal of the counting means and the output signal of the sensing means are inputted, and when the DRAM is in the standby state from the sensing means, a signal for detecting the waiting state after a predetermined time after the standby state starts. The refresh control method of the semiconductor device, characterized in that further comprising the step of outputting 제1항에 있어서, 상기 대기상태 검출신호는 상기 라스신호(/RAS)가 폴링(falling)되면 라이징(rising)되고, 상기 라스신호(/RAS) 및 카스신호(/CAS)중 늦게 라이징되는 신호로부터 일정신간 후에 폴링되도록 하는 것을 특징으로 하는 반도체 장치의 리프레쉬 제어방법.The signal of claim 1, wherein the standby state detection signal is raised when the ras signal / RAS falls, and is raised later than the ras signal / RAS and cas signal. Refreshing control method of a semiconductor device, characterized in that to be polled after a certain time from. 반도체 장치에서 디램의 대기상태를 감지하여 리프레쉬 주기를 조절하는 장치에 있어서, 카스신호(/CAS) 및 라스신호(/RAS)를 입력하는 입력단자와, 상기 입력단자로부터 입력된 신호에 의해 디램의 액티브상태 및 대기상태를 감지하기 위한 감지수단과, 상기 감지수단으로브터 디램이 대기상태인경우 일정한 주기를 갖는 신호를 발생시키기 위한 링 오실레이터 수단과, 상기 링 오실레이터 수단으로부터 발생된 클럭 신호를 카운트하여 리프레쉬 모드를 지정하는 신호를 발생하는 카운트 수단을 구비하는 것을 특징으로하는 반도체 장치의 리프레쉬 제어장치.A device for adjusting a refresh period by sensing a standby state of a DRAM in a semiconductor device, the apparatus comprising: an input terminal for inputting a cas signal (/ CAS) and a ras signal (/ RAS); and a signal input from the input terminal by a signal input from the input terminal. A sensing means for sensing an active state and a standby state, a ring oscillator means for generating a signal having a predetermined period when the sensor DRAM is in the standby state, and a clock signal generated by the ring oscillator means And a counting means for generating a signal specifying a refresh mode. 제4항에 있어서, 상기 카운트 수단의 출력신호 및 상기 감지수단의 출력신호를 입력으로하여 상기 감지수단으로부터 디램이 대기상태에 있을 경우 대기상태가 시작된후 일정시간 뒤에 상기 대기상태를 검출하는 신호를 출력하기 위한 대기상태 검출신호 발생수단을 추가로 구비하는 것을 특징으로 하는 반도체 장치의 리프레쉬 제어장치.The method of claim 4, wherein the output signal of the counting means and the output signal of the sensing means are inputted, and when the DRAM is in the standby state from the sensing means, a signal for detecting the waiting state after a predetermined time after the standby state starts. And a standby state detecting signal generating means for outputting. 제4항에 있어서, 상기 감지수단이 NAND게이트로 구성된 것을 특징으로 하는 반도체 장치의 리프레쉬 제어장치.5. The refresh control apparatus for a semiconductor device according to claim 4, wherein said sensing means comprises a NAND gate. 제4항에 있어서, 상기 링 오실레이터 수단은 노드(N4) 및 노드(N3) 사이에 직렬접속된 인버터(G3 및 G4)와, 상기 감지수단의 출력노드(N1) 및 상기 노드(N3)을 입력으로 하는 NOR게이트(G5)와, 상기 NOR게이트(G5)의 출력노드(N4)로 구성된 것을 특징으로 하는 반도체 장치의 리프레쉬 제어장치.5. The ring oscillator means according to claim 4, wherein the ring oscillator means inputs inverters G3 and G4 connected in series between a node N4 and a node N3, an output node N1 of the sensing means and the node N3. And a NOR gate (G5) and an output node (N4) of the NOR gate (G5). 제5항에 있어서, 상기 대기상태 검출신호 발생수단이 랫치회로로 구성된 것을 특징으로 하는 반도체 장치의 리프레쉬 제어장치.6. The refresh control apparatus for a semiconductor device according to claim 5, wherein said standby state detection signal generating means comprises a latch circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032626A 1994-12-02 1994-12-02 Refresh control method of semiconductor KR0138700B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476891B1 (en) * 2002-04-18 2005-03-17 삼성전자주식회사 Refresh circuit having variable restore time according to semiconductor operating mode and the method of refresh
KR100816050B1 (en) * 2005-04-28 2008-03-24 인피니언 테크놀로지스 아게 Methods and apparatus for implementing standby mode in a random access memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171605B1 (en) 2012-12-21 2015-10-27 Samsung Electronics Co., Ltd. Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476891B1 (en) * 2002-04-18 2005-03-17 삼성전자주식회사 Refresh circuit having variable restore time according to semiconductor operating mode and the method of refresh
KR100816050B1 (en) * 2005-04-28 2008-03-24 인피니언 테크놀로지스 아게 Methods and apparatus for implementing standby mode in a random access memory

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