KR100990142B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a process of continuously generating a column selection signal through a burst operation mode in a semiconductor memory device, the column selection signal generator for generating a column selection signal in response to a column command signal and a burst command signal, and A burst command signal generator for periodically activating the burst command signal in response to a system clock and forcibly deactivating the burst command signal in response to a burst termination command signal in a burst operation mode that enters in response to a column command signal. A semiconductor memory device comprising: activating a column selection signal and a burst operation mode entry signal in response to a column command signal; and a burst command in response to a system clock in an activation period of the burst operation mode entry signal. Periodically activating a signal, maintaining a burst command signal in an inactive state in response to a burst termination command signal in an activation section of the burst operation mode entry signal, and responsive to activation of the burst command signal A method of operating a semiconductor memory device includes activating a selection signal.

Burst Operation Mode, Burst Command Signal, Burst Termination Operation

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor design technology, and more particularly, to a process of generating a column selection signal in a semiconductor memory device, and more particularly, to a process of continuously generating a column selection signal through a burst operation mode in a semiconductor memory device. It is about.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

BACKGROUND OF THE INVENTION As the operating speed of a system composed of semiconductor devices becomes faster and technology related to semiconductor integrated circuits develops, semiconductor memory devices have been required to output or store data at a higher speed. In order for a semiconductor memory device to operate safely at a higher speed, several circuits in the semiconductor memory device must be able to operate at a high speed, and also a signal or data can be transferred at a high speed.

In order to speed up the operation of the semiconductor memory device, a plurality of internal operations that occur internally may be executed faster, or signals may be input / output faster. In an example, a double data rate (DDR) semiconductor memory device outputs data in synchronization with a rising edge as well as a falling edge of a system clock in order to output data faster. Since two data can be input and output at one cycle of the system clock from one input / output stage of the semiconductor memory device, the input / output speed of the data is faster than that of the conventional semiconductor memory device. A semiconductor memory device capable of inputting and outputting four data has been proposed.

As described above, the concept of burst length (BL) may be a very important factor in outputting data at a high speed in a semiconductor memory device. The concept of burst length BL is briefly described as an input to a semiconductor memory device. It is a numerical value representing the number of times data must be continuously output or input in response to one read command or write command.

For example, when the burst BL value of the semiconductor memory device is '4' and the data input / output bandwidth is '8X', eight data in parallel in response to one read command are sequentially semiconductors four times. Eight data, which are output from the memory device and formed in parallel with one write command, are sequentially input to the semiconductor memory device four times. In this case, the term continuous means that eight data in parallel are synchronized or inputted or outputted at each rising edge of the system clock in a single data rate (SDR) semiconductor memory device. In the semiconductor memory device, not only the rising edge of the system clock but also eight data in parallel for each falling edge are input or output in synchronization.

As described above, in order to complete the operation of the semiconductor memory device according to the burst length BL value, a plurality of column address values are provided through one column address value input to the semiconductor memory device together with one write command or one read command. It is necessary to move the game.

In other words, if the burst length BL is '4', data must be input or output four times in succession. However, since the data can be input or output in correspondence to one column address value only once, It is necessary to infer four column address values using one column address value.

In this case, the most common method of inferring a plurality of column address values using one column address value is, when the first column address value is determined at the first rising edge of the system clock, the second rising edge of the system clock is determined. Inferring the second column address value adjacent to the first column address value at the rising edge and inferring the second column address value adjacent to the second column address value at the third rising edge of the system clock This can be For reference, there may be several cases in which the first column address value and the second column address value are adjacent and the second column address value and the third column address value are adjacent. The most common method is simply the first column address value. Through the counting method, the second column address value becomes 1 greater than the first column address value, and the third column address value becomes 2 greater than the first column address value. This is how the value is determined.

1 is a block diagram illustrating a semiconductor memory device supporting burst mode operation according to the prior art.

Referring to FIG. 1, in the semiconductor memory device supporting burst mode operation according to the related art, the column command signal CASP6RD is generated in response to a plurality of command signals / CAS, / RAS, / CS, and / WE applied from the outside. , The column command signal generation unit 100 for generating the CASP6WR and a plurality of command signals (/ CAS, / RAS, /) applied from the outside in the burst operation mode entering in response to the column command signals CASP6RD and CASP6WR. A burst command signal generator 120 for periodically activating the burst command signal ICASP_BUST in response to the CS, / WE and the system clock CLK, and a plurality of externally applied command signals (/ CAS, / RAS) In response to the burst termination command signal generation unit 140 for generating the burst termination command signal (BUST_TERMINATE), the column command signals CASP6RD and CASP6WR, and the burst command signal ICASP_BUST in response to / CS, / WE). The column select signal AYP10 may be generated, and the column select signal generator 160 may be configured to forcibly deactivate the column select signal AYP10 in response to a burst termination command signal BUST_TERMINATE.

Here, the column selection signal generation unit 160 may include a logic combination unit 162 for outputting a signal CASP which is activated in response to the column command signals CASP6RD and CASP6WR being activated or the burst command signal ICASP_BUST being activated. ), The activation section length adjusting unit 164 for adjusting and outputting the activation section length of the signal CASP output from the logic combination unit 162, and the activation section length of the burst termination command signal BUST_TERMINATE. Activation section expansion unit 166 for extending and outputting the output signal (TERMINATION_CON_SIG) by one cycle (1tck) of the system clock CLK, and output signal ACTCON_CASP and activation of the activation section length adjusting unit 164. And a column select signal output unit 168 for outputting a column select signal AYP10 in which an activation period is determined in response to the signal TERMINATION_CON_SIG output from the section extension unit 166.

Here, the column selection signal output unit 168 responds to the activation of the output signal ACTCON_CASP of the activation section length control unit 164 within the deactivation section of the signal TERMINATION_CON_SIG output from the activation section expansion unit 166. Activates the column select signal AYP10, and in response to the output signal ACTCON_CASP of the activation section length adjusting unit 164 being deactivated, the column select signal AYP10 is deactivated and outputted, and the activation section extension 166 is activated. The column selection signal AYP10 is deactivated and output regardless of the output signal ACTCON_CASP of the activation section length control unit 164 within the activation section of the signal TERMINATION_CON_SIG.

FIG. 2 is a circuit diagram illustrating in detail a burst termination command signal generation unit among components of a semiconductor memory device that supports a burst mode operation according to the related art shown in FIG. 1.

Referring to FIG. 2, among the components of a semiconductor memory device supporting a burst mode operation according to the related art, the burst termination command signal generator 140 may include a plurality of command signals (/ CAS, / RAS, / Activation section of the burst termination operation signal generation unit 142 for generating the burst termination operation signals BST_CON and BS_CONb that are activated when CS, / WE) meets a predetermined condition, and the burst termination operation signals BST_CON and BS_CONb. The burst termination command signal output unit 144 is configured to activate the burst termination command signal BUST_TERMINATE in response to an edge of the system clock CLK.

Here, the burst termination operation signal generator 142 may be configured to generate a '/ CAS' command signal and a '/ RAS' command signal among a plurality of command signals (/ CAS, / RAS, / CS, / WE) that are externally applied. When 'Low' is activated and '/ CS' command signal and '/ WE' command signal are deactivated as logic 'high', the burst termination operation signal (BST_CON, BS_CONb) is activated and output. In this case, the burst termination operation signals BST_CON and BS_CONb are deactivated and output.

The burst termination command signal output unit 144 has a 'BST_CON' signal as logic 'high' and a 'BST_CONb' signal as logic 'low' among the burst termination operation signals BST_CON and BS_CONb. When the BST_CONb is activated, the burst termination command signal (BUST_TERMINATE) is activated by logic 'high' and is outputted. Otherwise, the burst termination command signal (BUST_TERMINATE) is disabled by logic 'Low' and output. .

FIG. 3 is a circuit diagram illustrating in detail a burst command signal generation unit among components of a semiconductor memory device supporting a burst mode operation according to the related art illustrated in FIG. 1.

Referring to FIG. 3, the burst command signal generator 120 of the components of the semiconductor memory device supporting the burst mode operation according to the related art is activated in response to entering the burst operation mode, and escapes from the burst operation mode. The burst operation signal generator 122 for generating the burst operation signals ICASP_BST_CON and ICASP_BST_CONb that are deactivated in response to the operation, and the activation period of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb periodically. A burst command signal output unit 124 for outputting a burst command signal ICASP_BUST having a predetermined activation interval is provided.

Here, the burst operation signal generator 122 enters the burst operation mode when the column command signals CASP6RD and CASP6WR are deactivated while the burst operation mode entry signal BUST_MODE_ENTRY is activated with logic 'high'. In this case, the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated and output, and in other cases, the burst operation signals are escaped and the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated and output.

At this time, the case in which the column command signals CASP6RD and CASP6WR are inactivated can be divided into two cases. First, the read column command signal CASP6RD among the column command signals CASP6RD and CASP6WR is inactivated. Multiple command signals (/ CAS, / RAS, / CS, / WE) that are applied in the '/ RAS' command signal and '/ WE' command signal, which are predetermined conditions, are activated as logic 'Low' and '/ It can be regarded as the same state as when the CAS 'command signal and the' / CS 'command signal are deactivated to logic' high '.

In addition, when the write column command signal CASP6WR is inactivated among the column command signals CASP6RD and CASP6WR, the signal CASWTb defined in the mode register set MRS is logic 'low' in FIG. 3. The same state as when activated with).

For reference, in FIG. 3, it can be seen that the signal 'BUST_LEN2' must be deactivated to logic 'low' in order to enter the burst operation mode and activate the burst operation signals ICASP_BST_CON and ICASP_BST_CONb. At this time, the signal 'BUST_LEN2' is a signal defined in the mode register set (MRS) and is a signal inactivated by logic 'low' when the value of the burst length BL of the semiconductor memory device exceeds '2'. The signal BUST_LEN2 'is not a signal used to enter the burst operation mode in the mode semiconductor memory device. In the case of FIG. 3, it is assumed that the illustrated semiconductor memory device is a DRAM (DDR) semiconductor memory device. That is, a signal corresponding to a minimum burst BL value may be input instead according to the type of semiconductor memory device. For example, when the semiconductor memory device is an SDR semiconductor memory device, the signal 'BUST_LEN2' may be eliminated in FIG. 3, or when the semiconductor memory device is a DDR2 semiconductor memory device. There should be a signal 'BUST_LEN4' instead of 'BUST_LEN2'.

The burst command signal output unit 124 has a 'ICASP_BST_CON' signal as logic 'high' and a 'ICASP_BST_CONb' signal as logic 'low' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb. When is activated, the burst command signal ICASP_BUST is activated by a logic 'high' and output, and in the opposite case, the burst command signal ICASP_BUST is deactivated and output by a logic 'low'.

FIG. 4 is a timing diagram illustrating an operation waveform of a semiconductor memory device supporting burst mode operation according to the related art shown in FIG. 1.

Referring to FIG. 4, a semiconductor memory device supporting a burst mode operation according to the prior art may perform a read operation through a plurality of command signals / CAS, / RAS, / CS, and / WE applied from the outside. When the read column command signal CASP6RD is activated at the first edge of the system clock CLK, it can be seen that the burst command signal ICASP_BUST is activated at the second and third edges of the system clock CLK in response. have.

Further, it can be seen that the column selection signal AYP10 is not only activated in response to the read column command signal CASP6RD but also activated in response to the burst command signal ICASP_BUST.

Further, even when the burst command signal ICASP_BUST is activated, when the burst termination command signal BUST_TERMINATE is activated, the column selection signal AYP10 may not be activated.

Specifically, the read column command signal CASP6RD for performing the read operation through the plurality of command signals / CAS, / RAS, / CS, and / WE applied from the outside is first raised of the system clock CLK. When activated at the edge, the burst operation mode entry signal BUST_MODE_ENTRY is activated in response, and the burst command signal ICASP_BUST is activated within the activation period of the burst operation mode entry signal BUST_MODE_ENTRY. It can be seen that it is activated periodically in response to the second rising edge and the third rising edge.

Thus, the column command signal CASP6RD and the burst command signal ICASP_BUST, which are activated, are input from the activation section length adjusting unit 164 to adjust the length of the activation section and output the result (ACTCON_CASP). At this time, the signal ACTCON_CASP output from the activation section length adjusting unit 164 is delayed by a predetermined time rather than being accurately synchronized to the rising edge of the system clock CLK due to the operation according to the activation section length adjustment. It can be seen that the state.

On the other hand, the burst termination command signal (BUST_TERMINATE) for performing the burst termination operation through a plurality of command signals (/ CAS, / RAS, / CS, / WE) applied from the outside rises third of the system clock (CLK) Activated at the rising edge, the operation to be achieved by activating the burst termination command signal (BUST_TERMINATE) at the third rising edge of the system clock (CLK) is the third rising edge of the system clock (CLK). This is to prevent the column selection signal AYP10 from being activated in response to the burst command signal ICASP_BUST activated at the rising edge.

However, the length of the activation interval of the burst termination command signal BUST_TERMINATE that is activated at the third rising edge of the system clock CLK is the burst that is activated at the third rising edge of the system clock CLK. Burst that is activated at the third rising edge of the system clock CLK because it is shorter than the length of the activation section of the signal ACTCON_CASP output from the activation section length controller 164 in response to the command signal ICASP_BUST. It is difficult to completely prevent the column selection signal AYP10 from being activated in response to the signal ACTCON_CASP output from the activation section length adjusting unit 164 in response to the command signal ICASP_BUST.

Therefore, the activation section extension unit 166 receives the burst termination command signal BUST_TERMINATE which is activated at the third rising edge of the system clock CLK, and the activation section length is one cycle of the system clock CLK. By extending the output (TERMINATION_CON_SIG) corresponding to (1tck), the length of the activation section is adjusted in response to the burst command signal ICASP_BUST whose length is activated at the third rising edge of the system clock CLK. It is longer than the signal ACTCON_CASP output from the unit 164. At this time, due to the operation of extending the activation section, the signal TERMINATION_CON_SIG output from the activation section expansion unit 166 is delayed by a predetermined time rather than being accurately synchronized to the rising edge of the system clock CLK. It can be seen that.

Through this process, the signal ACTCON_CASP output from the activation section length controller 164 in response to the burst command signal ICASP_BUST activated at the third rising edge of the system clock CLK is the system clock. The column selection signal AYP10 is not activated by the signal TERMINATION_CON_SIG output from the activation section extension 166 in response to the burst termination command signal BUST_TERMINATE activated at the third rising edge of CLK. I can see that I can not.

That is, even if the signal ACTCON_CASP output from the activation section length controller 164 is activated with logic 'High', the signal TERMINATION_CON_SIG output from the activation section extension 166 is logic 'low' ( Low), the column select signal output unit 168 does not activate the column select signal AYP10, and thus responds to the burst command signal ICASP_BUST that is activated at the third rising edge of the system clock CLK. The column selection signal AYP10 may not be activated according to the signal ACTCON_CASP output from the activation section length adjusting unit 164.

However, when the signal ACTCON_CASP output from the activation section length adjusting unit 164 and the signal TERMINATION_CON_SIG output from the activation section extension unit 166 are exactly the same as shown in FIG. If the signal TERMINATION_CON_SIG output from the activation section extension 166 is activated before the signal ACTCON_CASP output from the activation section length adjusting section 164 to prevent the column selection signal AYP10 from being activated, there is no problem. However, the signal (ACTCON_CASP) output from the activation section length adjusting unit 164 is activated before the signal (TERMINATION_CON_SIG) output from the activation section extension unit 166 due to the change in PVT (Process, Voltage, Temperature). In this case, a problem may occur in that the column selection signal AYP10 is not properly prevented from being activated.

That is, the signal ACTCON_CASP output from the activation section length adjusting unit 164 is a signal that is delayed by a predetermined time and not synchronized to the edge of the system clock CLK, and is output from the activation section extension section 166. (TERMINATION_CON_SIG) is also a signal that is not synchronized to the edge of the system clock CLK and is delayed by a predetermined time. At this time, the signal ACTCON_CASP output from the activation section length control unit 164 is delayed than the system clock CLK. The predetermined time is a value that can be changed according to the circuit configuration of the activation section length adjustment unit 164, the predetermined time that the signal (TERMINATION_CON_SIG) output from the activation section extension unit 166 is delayed than the system clock (CLK) is Since it is a value that can be changed according to the circuit configuration of the activation section extension 166, the value is different and the signal outputted from the activation section extension 166 through the design (TERMINATION_CON_SIG). Even if the starting point of the activation section is exactly the same or the signal TERMINATION_CON_SIG output from the activation section extension 166 is activated before the signal ACTCON_CASP output from the activation section length adjusting section 164, the actual process In the semiconductor memory device generated through the operation, the signal ACTCON_CASP output from the activation section length adjusting unit 164 is greater than the signal TERMINATION_CON_SIG output from the activation section extension 166 due to PVT (Process, Voltage, Temperature) variation. First, it may be activated to prevent the column selection signal AYP10 from being properly activated.

As a result, even if the signal TERMINATION_CON_SIG output from the activation section extension 166 is activated, if the column selection signal AYP10 is not properly prevented from being activated, as much as the portion of the column selection signal AYP10 is activated. Undesired data may be input / output from the semiconductor memory device. That is, the semiconductor memory device may malfunction.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems in the prior art, and provides a circuit capable of performing a reliable burst termination operation in a process of continuously generating a column selection signal through a burst operation mode in a semiconductor memory device. The purpose is to provide.

According to an aspect of the present invention for achieving the above object, the column selection signal generating means for generating a column selection signal in response to the column command signal and the burst command signal; And generating a burst command signal for periodically activating the burst command signal in response to a system clock in a burst operation mode entering in response to the column command signal, and forcibly deactivating the burst command signal in response to a burst termination command signal. A semiconductor memory device having a means is provided.

In addition, according to another aspect of the present invention for achieving the above object to be solved, the step of activating the column selection signal and the burst operation mode entry signal in response to the column command signal; Periodically activating a burst command signal in response to a system clock in an activation period of the burst operation mode entry signal; Maintaining the burst command signal in an inactive state in response to a burst termination command signal in an activation section of the burst operation mode entry signal; And activating the column selection signal in response to the activation of the burst command signal.

The present invention described above generates a column selection signal continuously in response to a burst command signal that is continuously activated in a burst operation mode of a semiconductor memory device, but in a burst termination operation, the burst command signal is prevented from being activated. This has the effect of performing a Nate operation.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

5 is a block diagram illustrating a semiconductor memory device supporting burst mode operation according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a semiconductor memory device supporting burst mode operation according to an embodiment of the present invention may include a column in response to a plurality of command signals (/ CAS, / RAS, / CS, / WE) applied from the outside. The column command signal generation unit 500 for generating the command signals CASP6RD and CASP6WR and the burst command signal in response to the system clock CLK in the burst operation mode in which the column command signals CASP6RD and CASP6WR enter. A burst command signal generator 520 for periodically activating ICASP_BUST and forcibly deactivating the burst command signal ICASP_BUST in response to the burst termination operation entry signal BUST_TERMINATION_ENTRY, and a column command signal CASP6RD, CASP6WR and And a column select signal generator 560 for generating the column select signal AYP10 in response to the burst command signal ICASP_BUST.

Here, the column selection signal generation unit 560 is a logic combination unit 562 for outputting a signal CASP which is activated in response to the column command signals CASP6RD and CASP6WR being activated or the burst command signal ICASP_BUST being activated. And an activation section length adjusting unit 564 for adjusting the length of the activation section of the signal CASP output from the logic combination section 562 to output the column selection signal AYP10.

FIG. 6 is a detailed circuit diagram illustrating a burst command signal generation unit among components of a semiconductor memory device that supports a burst mode operation according to the exemplary embodiment of FIG. 5.

Referring to FIG. 6, a burst command signal generator 520 of components of a semiconductor memory device supporting burst mode operation according to an exemplary embodiment of the present invention is activated in response to entering a burst operation mode, and burst termination Burst operation signal generation unit 522 for generating burst operation signals ICASP_BST_CON and ICASP_BST_CONb which are activated in response to the operation entry signal BUST_TERMINATION_ENTRY being activated or exiting from the burst operation mode, and burst operation signals ICASP_BST_CON and ICASP_BST_CONb. A burst command signal output unit 524 is provided for outputting a burst command signal ICASP_BUST having a predetermined activation period periodically in response to the system clock CLK in the activation period of.

Here, the burst operation signal generator 522 receives a plurality of command signals / CAS, / RAS, / CS, and / WE that are applied from the outside, respectively, and the read column command signal CASP6RD and the burst termination operation entry signal. Responding to signals output from a plurality of NAND gates NAND1, NAND2, NAND3 and a plurality of inverters INV1, INV2, INV3, and a plurality of inverters INV1, INV2, INV3 to determine whether (BUST_TERMINATION_ENTRY) is activated. The plurality of PMOS transistors P1, P2, P3 and the plurality of NMOS transistors N1, N2, N3, inverters INV4, and passgate PG1 to determine the logic levels of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb. Corresponds to the signal CASWTb and burst length BL defined in the mode register set MRS in response to the logic level of the burst operation mode entry signal BUST_MODE_ENTRY and the write column command signal CASP6WR. Into the mode register set (MRS) Noah gate NOR1, NAND gate NAND4, PMOS transistor P4, NMOS transistor N4, and inverter for determining the logic level of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb in response to the signal BUST_LEN2. INV4 and the passgate PG1.

Specifically, the plurality of NAND gates NAND1, NAND2, NAND3, and NAND4 provided in the burst operation signal generator 522, the plurality of inverters INV1, INV2, INV3, and INV4, the NOA gate NOR1, The connection relations between the plurality of PMOS transistors P1, P2, P3, and P4, the plurality of NMOS transistors N1, N2, N3, and N4, and the pass gate PG1 and their operations will be described below.

First, referring to the connection relationship between the burst operation signal generator 522, the inversion signal CS of the '/ CS' command signal among a plurality of command signals / CAS, / RAS, / CS, and / WE that are applied from the outside The first NAND gate NAND1 and the first inverter INV1 for receiving and logically multiplying and outputting the '/ RAS' command signal RASb, and the inverted signal CAS and the '/ WE' command of the '/ CAS' command signal. Inverted signal WE of the second NAND gate NAND2 and the second inverter INV2 and the '/ CAS' command signal CASb and the '/ WE' command signal for receiving and multiplying and outputting the command signal WEb ), The third NAND gate NAND3 and the third inverter INV3 for receiving and logically outputting the result, and the charging node CHARGE_NODE connected to the source in response to the output signal of the first inverter INV1 applied to the gate. An output of the first PMOS transistor P1 for controlling the drain-connected output node OUT_NODE and the first inverter INV1 applied to the gate. In response to the call, the first NMOS transistor N1 for controlling the connection of the drain-connected output node OUT_NODE and the source-connected discharge node DISCH_NODE, and the output signal of the second inverter INV2 applied to the gate. In response to the output signal of the second PMOS transistor P2 for controlling the connection of the source-connected charging node CHARGE_NODE and the drain-connected intermediate node CHMID_NODE, and the second inverter INV2 applied to the gate. In response to the output signal of the second NMOS transistor N2 for controlling the connection of the drain-connected discharge node DISCH_NODE to the source-connected ground voltage VSS terminal and the third inverter INV3 applied to the gate. In response to the output signal of the third PMOS transistor P3 for controlling the connection of the source-connected intermediate node CHMID_NODE and the drain-connected output node OUT_NODE, and the third inverter INV3 applied to the gate. A mode register set corresponding to a logic level of the third NMOS transistor N3 and the write column command signal CASP6WR for controlling the connection between the connected discharge node DISCH_NODE and the source connected ground voltage VSS terminal. Register set: NOR1 for receiving negative logic and outputting the signal (BUST_LEN2) defined in the mode register set (MRS) corresponding to the signal (CASWTb) and burst length (BL) value defined in MRS ), A fourth NAND gate NAND4 for receiving the logical operation mode of the burst operation mode entry signal BUST_MODE_ENTRY and the output signal of the first NOR gate NOR1, and outputting the result of a negative logic multiplication, and a fourth NAND gate applied to the gate. The fourth PMOS transistor P4 for controlling the connection of the source voltage supply terminal VPERI and the drain-connected charging node CHARGE_NODE in response to an output signal of the second transistor; and a fourth NAND gate NAND4 applied to the gate. Exodus In response to the output signal, a signal loaded on the fourth NMOS transistor N4 and the output node OUT_NODE for controlling the connection of the drain-connected output node OUT_NODE and the source-connected ground voltage VSS terminal is received. The fourth inverter (INV4) for outputting as 'ICASP_BST_CONb' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb by inverting the phase, and the power supply voltage VPERI applied to the positive input terminal and the ground voltage VSS greeting to the negative input terminal. In response, a pass gate PG1 for outputting a signal loaded on the output node OUT_NODE applied to the signal input terminal as 'ICASP_BST_CON' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb through the signal output terminal.

In addition, the operation of the burst operation signal generation unit 522 is a case where the column command signals CASP6RD and CASP6WR are deactivated when the burst operation mode entry signal BUST_MODE_ENTRY is activated with logic 'high'. After entering the burst operation mode, the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated and output.

In addition, when the burst operation mode entry signal BUST_MODE_ENTRY is deactivated to logic 'low', the column command signals CASP6RD and CASP6WR are activated, or the burst termination operation entry signal BUST_TERMINATION_ENTRY is activated. The burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated and outputted.

More specifically, the case of activating and outputting the burst operation signals ICASP_BST_CON and ICASP_BST_CONb is as follows.

First, when the column command signals CASP6RD and CASP6WR are deactivated in order to enter the burst operation mode, the column command signals CASP6RD and CASP6WR are classified into two cases, and the conditions to be satisfied in the read operation are the column command signals CASP6RD, In the CASP6WR), the read column command signal CASP6RD should be deactivated, and in FIG. 6, a plurality of command signals (/ CAS, / RAS, / CS, / WE) applied from the outside are '/ RAS' command signals, which are predetermined conditions. For example, when the '/ WE' command signal is deactivated to logic 'High' and the '/ CAS' command signal and the '/ CS' command signal are not activated to logic 'Low', for example Read column command when '/ RAS' command signal and '/ WE' command signal are activated as logic 'Low' and '/ CAS' command signal and '/ CS' command signal are disabled as logic 'high'. If the signal CASP6RD is in the same state as Can.

In addition, the condition to be satisfied in the write operation is that the write column command signal CASP6WR of the column command signals CASP6RD and CASP6WR should be deactivated. In FIG. 6, the signal defined in the mode register set (MRS) ( Write when CASWTb) is not a condition in which logic 'High' is disabled, that is, when signal CASWTb defined in Mode Register Set (MRS) is activated as logic 'Low'. It can be seen that the column command signal CASP6WR is in the same state as inactivated.

For reference, in FIG. 6, a signal CASWTb defined in a mode register set (MRS) that is activated by logic 'low' to deactivate the write column command signal CASP6WR during a write operation. In response to this, it can be seen that the signal 'BUST_LEN2' must be deactivated to a logic 'low' in order for the logic level of the signal output from the first NOR gate NOR1 to change. At this time, the signal 'BUST_LEN2' is a signal defined in the mode register set (MRS) and is a signal inactivated by logic 'low' when the value of the burst length BL of the semiconductor memory device exceeds '2'. The signal BUST_LEN2 'is not a signal used to enter the burst operation mode in the mode semiconductor memory device. In the case of FIG. 6, it is assumed that the illustrated semiconductor memory device is a digital semiconductor memory device. That is, a signal corresponding to a minimum burst BL value may be input instead according to the type of semiconductor memory device. For example, when the semiconductor memory device is an SDR semiconductor memory device, the signal 'BUST_LEN2' may be eliminated in FIG. 3, or when the semiconductor memory device is a DDR2 semiconductor memory device. There should be a signal 'BUST_LEN4' instead of 'BUST_LEN2'. Therefore, in FIG. 6, the signal 'BUST_LEN2' becomes logic 'high' when the column command signals CASP6RD and CASP6WR are activated, and logic 'low' when the column command signals CASP6RD and CASP6WR are deactivated. It can be regarded as a (Low) state.

When the column command signals CASP6RD and CASP6WR are deactivated and the burst operation mode entry signal BUST_MODE_ENTRY is activated with logic 'High' through the conditions as described above, the burst operation signal generator shown in FIG. In operation 522, if the burst operation signals ICASP_BST_CON and ICASP_BST_CONb that are actually activated may be output, first, if the conditions in the write operation are matched, the signal CASWTb defined in the mode register set (MRS) ) And the 'BUST_LEN2' signal are deactivated to logic 'Low' so that the output signal of the first NOR gate NOR1 is activated as logic 'High' and the burst operation mode entry signal (BUST_MODE_ENTRY) is logic. 'High' is activated so that the output signal of the fourth NAND gate NAND4 is logic 'low', whereby the fourth PMOS transistor P4 is turned on and the fourth NMOS transistor is turned on. Is turned off.

When the conditions in the read operation are matched, the first NAND gate NAND1 and the first inverter INV1 are inverted signal CS and logic 'low' of the '/ CS' command signal having a logic 'low' state. In response to the '(low)' / RAS 'command signal (RASb), a logic' low 'signal is output, and the second NAND gate NAND2 and the second inverter INV2 are logic' low '. Signal of logic 'low' state in response to inverted signal (CAS) of '(low)' / CAS command signal and logic 'low' (WE) command signal (WEb) And the third NAND gate NAND3 and the third inverter INV3 are logic 'high' / CAS command signals CASb and logic 'high' / WE. A logic high signal is output in response to the inversion signal WE of the command signal, and correspondingly, the first and second PMOS transistors P1 and P2 and the third NMOS transistor N3 are turned on. Turned on, the first and second NMOS transistors N1 and N2 and the third PMOS Transistor P3 is turned off.

Accordingly, the output node OUT_NODE is activated with logic 'high', and in response, 'ICASP_BST_CON' of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb becomes logic 'high' and the burst operation signal ICASP_BST_CON, Among the ICASP_BST_CONb), the 'ICASP_BST_CONb' becomes a logic 'low', indicating that the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated.

In more detail, a case in which the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated and output is described as follows.

First, when the column command signals CASP6RD and CASP6WR are activated in order to escape from the burst operation mode, any one of the column command signals CASP6RD and CASP6WR may be satisfied. The condition that must be satisfied in the read operation is the column command signal. Among the (CASP6RD and CASP6WR), the read column command signal CASP6RD should be activated. In FIG. 6, a plurality of command signals (/ CAS, / RAS, / CS, / WE) that are applied from outside are scheduled conditions' / RAS. Read column command signal when 'command signal' and '/ WE' command signal are disabled with logic 'high' and '/ CAS' command signal and '/ CS' command signal are activated with logic 'low' It can be regarded as the same state that (CASP6RD) is activated.

In addition, the condition to be satisfied in the write operation is that the write column command signal CASP6WR of the column command signals CASP6RD and CASP6WR should be activated. In FIG. 6, the signal defined in the mode register set (MRS) ( When the CASWTb is deactivated to logic 'high', it can be regarded as the same state as the write column command signal CASP6WR is activated.

In addition, referring to a condition in which the burst termination operation entry signal (BUST_TERMINATION_ENTRY) is activated, in FIG. 6, a plurality of command signals (/ CAS, / RAS, / CS, / WE) applied from the outside are scheduled conditions '/ RAS' command. When the signal and '/ CAS' command signal are deactivated to logic 'High' and the '/ WE' command signal and '/ CS' command signal are activated to logic 'Low' BUST_TERMINATION_ENTRY) is the same state that is activated.

When the column command signals CASP6RD and CASP6WR are activated through the above conditions, the burst operation mode entry signal BUST_MODE_ENTRY is deactivated to logic 'low', or the burst termination operation entry signal BUST_TERMINATION_ENTRY is activated. Referring to whether the burst operation signals ICASP_BST_CON and ICASP_BST_CONb that are actually deactivated by the burst operation signal generation unit 522 shown in FIG. 6 can be outputted, first, if the conditions in the write operation are matched, the mode register set (Mode) As soon as the signal CASWTb and the signal 'BUST_LEN2' defined in the Register Set (MRS) are deactivated to logic 'High', the output signal of the first NOR gate NOR1 is deactivated to logic 'Low'. In response, the output signal of the fourth NAND gate NAND4 becomes logic 'high' irrespective of the logic level of the burst operation mode entry signal BUST_MODE_ENTRY and thus the fourth PMOS transistor. P4 is turned off and the fourth NMOS transistor is turned on, whereby the output node OUT_NODE is deactivated to a logic 'low' and in response to a burst operation signal ( Among ICASP_BST_CON and ICASP_BST_CONb, 'ICASP_BST_CON' becomes logic 'Low' and 'ICASP_BST_CONb' becomes logic 'High' among burst operation signals (ICASP_BST_CON, ICASP_BST_CONb) so that burst operation signals (ICASP_BST_CON) are disabled. It can be seen that.

When the conditions in the read operation correspond, the first NAND gate NAND1 and the first inverter INV1 are inverted signal CS and logic 'high' of the 'CS' command signal having a logic 'high' state. In response to the '(High)' / RAS 'command signal (RASb), a logic' High 'signal is output, and the second NAND gate and the second inverter (INV2) are logic' high. Signal of logic 'High' state in response to inversion signal (CAS) of '(High)' / CAS command signal and logic 'High' / WE 'command signal (WEb) And the third NAND gate NAND3 and the third inverter INV3 are in a logic low state / CAS command signal CASb and a logic low state. In response to the inverted signal WE of the WE 'command signal, a signal in a logic' low 'state is output, and correspondingly, the first and second PMOS transistors P1 and P2 and the third NMOS transistor N3 are output. Turned off, and the first and second NMOS transistors N1 and N2 and the third PMOS transistor P3 is turned on.

Accordingly, the output node OUT_NODE is deactivated to logic 'low', and in response, 'ICASP_BST_CON' of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb becomes logic 'low' and the burst operation signal ICASP_BST_CON, Among the ICASP_BST_CONb), 'ICASP_BST_CONb' becomes logic 'high', indicating that the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated.

When the burst operation mode entry signal BUST_MODE_ENTRY corresponds to a condition in which the logic 'low' is inactivated, the fourth NAND gate NAND4 of the fourth NAND4 may be irrelevant regardless of the logic level of the signal output from the first NOR gate NOR1. The output signal is logic 'high' so that the fourth PMOS transistor P4 is turned off and the fourth NMOS transistor is turned on, so that the output node OUT_NODE is logic 'low. '(Low) is deactivated, and in response,' ICASP_BST_CON 'of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb becomes logic' low 'and' ICASP_BST_CONb 'of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb is logic' high ' It can be seen that the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are inactivated.

If the condition that the burst termination operation entry signal (BUST_TERMINATION_ENTRY) is activated is applied,

The first NAND gate NAND1 and the first inverter INV1 are inverted signal CS of the 'CS' command signal in logic 'high' state and '/ RAS' in logic 'high' state. A logic 'high' signal is output in response to the command signal RASb, and the second NAND gate NAND2 and the second inverter INV2 are logic 'low' / CAS 'signals. In response to the inversion signal CAS of the command signal and the '/ WE' command signal WEb in a logic 'low' state, a signal in a logic 'low' state is output, and the third NAND gate NAND3 is output. ) And the third inverter (INV3) to the inverted signal (WE) of the logic 'high' (CAS) command signal (CASb) and the logic 'high' ('High) state' / WE 'command signal In response to outputting a logic 'high' signal, correspondingly, the first and third PMOS transistors P1 and P3 and the second NMOS transistor N2 are turned off. The third NMOS transistors N1 and N3 and the second PMOS transistor P2 are turned on.

Accordingly, the output node OUT_NODE is deactivated to logic 'low', and in response, 'ICASP_BST_CON' of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb becomes logic 'low' and the burst operation signal ICASP_BST_CON, Among the ICASP_BST_CONb), 'ICASP_BST_CONb' becomes logic 'high', indicating that the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated.

In addition, the burst command signal output unit 524 includes a plurality of PMOS transistors P5 and P6 and NMOS transistors N5 for controlling the operation of the output unit 524 of the burst command signal in response to the system clock CLK. And a plurality of NMOS transistors N6 and N7 for adjusting the potential levels of the output nodes BUST_OND and BUST_ONDb in response to the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522. Burst in response to the potential levels of the signals loaded on the NMOS transistors N8 and N9 and the PMOS transistors P7 and P8 and the output nodes BUST_OND and BUST_ONDb for sensing and amplifying the potential levels of the nodes BUST_OND and BUST_ONDb. A plurality of inverters INV5, INV6, INV7 and dummy inverters INV8 for determining the logic level of the command signal ICASP_BUST are provided.

Specifically, the PMOS transistors P5, P6, P7, and P8, the NMOS transistors N5, N6, N7, N8, and N9 and the inverters INV5, INV6, INV7, which are provided in the burst command signal output unit 524. The connection relationship between the INV8 and its operation are as follows.

First, referring to the connection relationship of the burst command signal output unit 524, the first NMOS for controlling the connection of the drain-connected common node COMN and the source-connected ground voltage VSS terminal in response to the system clock CLK is performed. A source connected to the transistor N5 and the sensed output node TU_BUST_OND drained in response to 'ICASP_BST_CON' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522 applied to the gate. The second NMOS transistor N6 for controlling the connection of the common node COMN and the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522 applied to the gate in response to 'ICASP_BST_CONb'. In response to the third NMOS transistor N7 and the system clock CLK for controlling the connection of the drain-connected sensing unit output node TU_BUST_ONDb and the source-connected common node COMN. The first PMOS transistor P5 for controlling the connection of the source-connected power supply voltage VPERI and the drain-connected constant output node BUST_OND, and the source-connected power supply voltage VPERI in response to the system clock CLK. A power supply voltage VPERI source connected in response to a potential level of the second PMOS transistor P6 for controlling the connection between the terminal and the drain-connected sub-output node BUST_ONDb and the sub-output node BUST_ONDb applied to the gate. The third PMOS transistor P7 for controlling the amount of current flowing to the drain-connected constant output node BUST_OND and the constant output node BUST_OND drained in response to the potential level of the sub-output node BUST_ONDb applied to the gate. Source connected in response to the potential level of the fourth NMOS transistor P8 for controlling the amount of current flowing to the sensing constant output node TU_BUST_OND connected to the source and the constant output node BUST_OND applied to the gate at A drain connected to the potential level of the fourth PMOS transistor P8 for controlling the amount of current flowing from the voltage VPERI terminal to the drain-connected sub-output node BUST_ONDb and the constant output node BUST_OND applied to the gate. The fifth NMOS transistor P9 for controlling the amount of current flowing from the output node BUST_ONDb to the source connected to the sensing unit output node TU_BUST_ONDb and the potential level of the constant output node BUST_OND are determined based on the predetermined logic decision level. Connected to the first to third inverters INV5, INV6, INV7 and the sub output node BUST_ONDb connected in series to form a burst command signal ICASP_BUST, and the first to third inverters INV5, Dummy inverters INV8 having sizes corresponding to INV6 and INV7 are provided.

In addition, referring to the operation of the burst command signal output unit 524, one of the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522 maintains a logic 'High' state. During the period in which the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated, the logic 'ICASP_BST_CONb' remains in a logic 'low' state among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb. The burst command signal ICASP_BUST having a predetermined activation period is activated by being activated at high 'level.

In addition, among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522, 'ICASP_BST_CON' maintains a logic 'low' state, and 'ICASP_BST_CONb' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb. A burst command signal (ICASP_BUST) that maintains a logic 'high' state and maintains a disabled state with a logic 'low' regardless of the system clock CLK in a section where the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated. )

More specifically, the case where the burst command signal ICASP_BUST has a periodically scheduled activation period in response to the system clock CLK and the case where the burst command signal ICASP_BUST is continuously deactivated regardless of the system clock CLK will be described below.

First, when the system clock CLK is logic 'low', both the constant output node BUST_OND and the sub output node BUST_ONDb have the same level as the power supply voltage VPERI, and the power supply voltage VPERI. Since the potential level of N is higher than the logic decision level, the burst command signal ICASP_BUST remains unconditionally logic 'low' when the system clock CLK is logic 'low'.

Therefore, in the state where the system clock CLK is logic 'low', even if the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522 are changed, the constant output node BUST_OND and It is not possible to change the potential level of the sub-output node BUST_ONDb, and the burst command signal ICASP_BUST is unconditionally logic 'low'.

In addition, when the system clock CLK is logic 'high', the minute potential difference between the constant output node BUST_OND and the negative output node BUST_ONDb is sensed to detect the constant output node BUST_OND and the negative output node BUST_ONDb. The potential level is determined by the power supply voltage VPERI or ground voltage VSS.

That is, when the constant output node BUST_OND has a potential level higher than that of the negative output node BUST_ONDb, the potential level of the constant output node BUST_OND is set to be the same level as the power supply voltage VPERI and the negative output node BUST_ONDb. The potential level of the output voltage VSS is equal to the ground voltage VSS. However, when the constant output node BUST_OND has a lower potential level than the negative output node BUST_ONDb, the potential level of the constant output node BUST_OND is set to the ground voltage (VSS). And the potential level of the sub output node BUST_ONDb to be the same level as the power supply voltage VPERI.

In this case, the potential difference between the constant output node BUST_OND and the sub-output node BUST_ONDb may be changed according to the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522, and thereby the burst command signal (ICASP_BUST) can be enabled with logic 'high'.

That is, 'ICASP_BST_CON' and 'ICASP_BST_CONb' are always signals having opposite logic levels among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb, and 'ICASP_BST_CON' is a detection output node. It is possible to determine that the potential level of the constant output node BUST_OND is changed, and among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb, the ICASP_BST_CONb is the potential level of the sub-output node BUS_ONDb via the sensing output node TU_BUST_ONDb. Since the change may be determined, the burst command signal ICASP_BUST may be activated to a logic 'high' according to whether the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated.

For example, among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb, 'ICASP_BST_CON' is logic 'high', and 'ICASP_BST_CONb' is logic 'low' so that the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are activated. In this case, the potential level of the constant output node BUST_OND is lowered more quickly than the potential level of the negative output node BUST_ONDb. Thus, the potential level of the constant output node BUST_OND is equal to the ground voltage VSS. The potential level of the negative output node BUST_ONDb is the same as the power supply voltage VPERI. As a result, the burst command signal ICASP_BUST is activated with logic 'High'.

However, when 'ICASP_BST_CON' is logic 'low' among the burst operation signals ICASP_BST_CON and ICASP_BST_CONb, and 'ICASP_BST_CONb' is logic 'high' and the burst operation signals ICASP_BST_CON and ICASP_BST_CONb are deactivated. The potential level of the negative output node BUST_ONDb is lowered more quickly than the potential level of the constant output node BUST_OND. As a result, the potential level of the constant output node BUST_OND becomes the same level as the power supply voltage VPERI. The potential level of the output node BUST_ONDb is equal to the ground voltage VSS. As a result, the burst command signal ICASP_BUST is deactivated to a logic 'high'.

Accordingly, when the system clock CLK is logic 'high', the burst command signal ICASP_BUST is logic 'when the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generator 522 are activated. The burst command signal ICASP_BUST is deactivated to a logic 'low' when the burst operation signal ICASP_BST_CON and ICASP_BST_CONb are deactivated.

At this time, if the burst operation signals ICASP_BST_CON and ICASP_BST_CONb output from the burst operation signal generation unit 522 continue to be activated while the system clock CLK toggles several times, the system clock CLK is logic 'low'. In response to a transition from 'Low' to a logic 'High', i.e., in response to a rising edge of the system clock CLK, the burst command signal ICASP_BUST is logic 'High'. Is activated and bursts in response to the system clock CLK transitioning from logic 'high' to logic 'low', that is, in response to the falling edge of the system clock CLK. The command signal ICASP_BUST may be deactivated to a logic 'high'.

Accordingly, in response to the burst operation signals ICASP_BST_CON and ICASP_BST_CONb remaining in the active state when the burst termination operation entry signal BUST_TERMINATION_ENTRY is deactivated when the burst operation mode is entered, the burst command signal ICASP_BUST is received by the system clock ( It is possible to activate periodically at the edge of CLK) to remain active for a predetermined time.

In addition, the burst command signal ICASP_BUST responds to the system clock CLK in response to the burst operation signals ICASP_BST_CON and ICASP_BST_CONb, which remain in the deactivated state when the burst operation mode is exited or the burst termination operation entry signal BUST_TERMINATION_ENTRY is activated. It is possible to keep it deactivated regardless of).

FIG. 7 is a timing diagram illustrating an operation waveform of a semiconductor memory device supporting burst mode operation according to an exemplary embodiment of the present invention illustrated in FIG. 5.

Referring to FIG. 7, in the semiconductor memory device supporting burst mode operation according to an exemplary embodiment of the present invention, a read operation is performed through a plurality of command signals / CAS, / RAS, / CS, and / WE applied from the outside. When the read column command signal CASP6RD for performing is activated on the first edge of the system clock CLK, in response, the burst command signal ICASP_BUST is activated only on the second edge of the system clock CLK and the system clock CLK. It can be seen that the burst command signal ICASP_BUST is not activated on the third edge of the C1) edge.

That is, although the burst operation mode entry signal BUST_MODE_ENTRY is still activated in response to the read column command signal CASP6RD at the third edge of the system clock CLK, the burst termination operation entry signal BUST_TERMINATION_ENTRY is activated. It can be seen that the burst command signal ICASP_BUST is not activated at the third edge of the system clock CLK.

The column selection signal AYP10 may be activated not only in response to the read column command signal CASP6RD but also in response to the burst command signal ICASP_BUST.

Specifically, the read column command signal CASP6RD for performing the read operation through the plurality of command signals / CAS, / RAS, / CS, and / WE applied from the outside is first raised of the system clock CLK. When activated at the edge, the burst operation mode entry signal BUST_MODE_ENTRY is activated in response, and the burst command signal ICASP_BUST is activated within the activation period of the burst operation mode entry signal BUST_MODE_ENTRY. It can be seen that it is activated at the second rising edge but not at the third rising edge.

In addition, the burst termination operation signal (BUST_TERMINATRION_ENTRY) for performing the burst termination operation through a plurality of command signals (/ CAS, / RAS, / CS, / WE) applied from the outside is raised third of the system clock (CLK). This is activated at the rising edge. The operation to be achieved by activating the burst termination operation entry signal (BUST_TERMINATION_ENTRY) at the third rising edge of the system clock (CLK) is the third rise of the system clock (CLK). This is to prevent the burst command signal ICASP_BUST from being activated at the edge.

That is, the burst command signal ICASP_BUST is activated at the second rising edge of the system clock CLK, but is not activated at the third rising edge. The burst termination operation signal BUST_TERMINATRION_ENTRY is not activated. This is because it is activated at the third rising edge of the system clock CLK.

Therefore, in the activation section length adjusting unit 564, the read column command signal CASP6RD and the second rising edge of the system clock CLK are activated at the first rising edge of the system clock CLK. It can be seen that the signal which receives only the burst command signal ICASP_BUST activated at and adjusts the length of the activation period and becomes the column selection signal AYP10.

As described above, according to the exemplary embodiment of the present invention, the column select signal is continuously activated in response to the burst command signal continuously activated at the edge of the system clock in the burst operation mode, but the burst termination operation is performed. When started, the burst command signal is no longer activated even when the burst operation mode is entered, thereby completely eliminating the possibility that the column select signal can be activated in the burst termination operation.

That is, in the semiconductor memory device supporting the burst operation mode, the burst termination operation may be reliably performed regardless of the PVT (Process, Voltage, Temperature) change.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

1 is a block diagram illustrating a semiconductor memory device supporting burst mode operation according to the prior art.

FIG. 2 is a circuit diagram illustrating in detail a burst termination command signal generation unit among components of a semiconductor memory device supporting a burst mode operation according to the related art shown in FIG.

3 is a circuit diagram illustrating in detail a burst command signal generation unit among components of a semiconductor memory device supporting a burst mode operation according to the related art shown in FIG.

FIG. 4 is a timing diagram illustrating an operation waveform of a semiconductor memory device supporting burst mode operation according to the related art shown in FIG. 1.

5 is a block diagram illustrating a semiconductor memory device supporting burst mode operation according to an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating in detail a burst command signal generation unit among components of a semiconductor memory device that supports a burst mode operation according to an exemplary embodiment of the present invention illustrated in FIG. 5.

FIG. 7 is a timing diagram illustrating an operation waveform of a semiconductor memory device supporting burst mode operation according to an exemplary embodiment of the present invention illustrated in FIG. 5.

DESCRIPTION OF THE REFERENCE NUMERALS

100, 500: column command signal generation unit

120, 520: Burst command signal generation unit

122, 522: burst operation signal generation unit

124, 524: Burst command signal output section

140: burst termination command signal generation unit

142: burst termination operation signal generator

144: burst termination command signal output unit

160, 560: column selection signal generation unit 162, 562: logic combination unit

164, 564: length of the activation section control unit 166: extension of the activation section

168: column select signal output unit

Claims (16)

Column select signal generating means for generating a column select signal in response to the column command signal and the burst command signal; And Burst command signal generating means for periodically activating the burst command signal in response to a system clock in a burst operation mode entering in response to the column command signal and forcibly deactivating the burst command signal in response to a burst termination operation signal; A semiconductor memory device having a. The method of claim 1, The column selection signal generating means, A logic combiner for outputting a signal that is activated in response to the column command signal being activated or the burst command signal being activated; And And an activation section length adjusting section for adjusting the length of the activation section of the signal output from the logic combination section to output the column selection signal. The method of claim 1, The burst command signal generating means, A burst operation signal generator configured to generate a burst operation signal activated in response to entering the burst operation mode and deactivated in response to the burst termination operation signal being activated or exiting from the burst operation mode; And And a burst command signal output unit configured to output the burst command signal having a predetermined activation period periodically in response to the system clock in the activation period of the burst operation signal. The method of claim 3, The burst operation signal generation unit, And activating the burst operation signal in response to the column command signal being deactivated in a state in which the signal controlling to enter the burst operation mode is activated. The method of claim 4, wherein The burst operation signal generation unit, And the burst operation signal is deactivated when the signal controlling to enter the burst operation mode is in an inactive state, the burst termination operation signal is in an activated state, or the column command signal is in an active state. The method of claim 3, The burst command signal output unit, And activating the burst command signal for a predetermined time in response to an edge of the system clock when the burst operation signal is activated. The method of claim 3, The burst command signal output unit, And activating the burst command signal in response to a rising edge of the system clock when the burst operation signal is activated. The method of claim 7, wherein The burst command signal output unit, And deactivating the burst command signal in response to a falling edge of the system clock when the burst operation signal is activated. The method according to any one of claims 6 to 7, The burst command signal output unit, And keep the burst command signal in an inactive state regardless of whether the system clock toggles while the burst operation signal is inactive. Activating a column selection signal and a burst operation mode entry signal in response to the column command signal; Periodically activating a burst command signal in response to a system clock in an activation period of the burst operation mode entry signal; Maintaining the burst command signal in an inactive state in response to a burst termination operation signal in an activation section of the burst operation mode entry signal; And Activating the column selection signal in response to activation of the burst command signal Method of operating a semiconductor memory device comprising a. The method of claim 10, The activating of the column selection signal and the burst operation mode entry signal may include: Activating the column selection signal in response to the column command signal being activated, and adjusting the length of the column selection signal activation section in response to the length of the activation section of the column command signal; And Activating the burst operation mode entry signal in response to the column command signal being activated, and maintaining the activation period for the burst operation mode signal for a time defined in a mode register set (MRS). A method of operating a semiconductor memory device. The method of claim 10, Periodically activating the burst command signal, Periodically activating the burst command signal in response to a rising edge of the system clock when the burst operation mode entry signal is activated; Periodically deactivating the burst command signal in response to a falling edge of the system clock when the burst operation mode entry signal is activated; And And maintaining the burst command signal in an inactive state regardless of toggling of the system clock while the burst operation mode entry signal is inactive. The method of claim 12, The burst command signal may be maintained in an inactive state. And when the burst termination operation signal is activated while the burst operation mode entry signal is activated, the burst command signal is no longer activated at the rising edge of the system clock. The method of claim 10, Periodically activating the burst command signal, The burst command signal is periodically activated in response to an edge of the system clock while the burst operation mode entry signal is activated, and the burst command signal is periodically inactivated in response to a predetermined time flow from the periodically activated time. Operating a semiconductor memory device. The method of claim 14, The burst command signal may be maintained in an inactive state. And when the burst termination operation signal is activated while the burst operation mode entry signal is activated, the burst command signal is no longer activated at an edge of the system clock. The method according to any one of claims 12 to 14, Activating the column selection signal, And periodically activating the column selection signal in response to the burst command signal being periodically activated, and adjusting the length of the activation period of the column selection signal in response to the activation period length of the burst command signal. How the device works.

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