KR20060035836A - Generation device of output enable signal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output enable signal generating device, and more particularly, by using a read signal as a control signal of an operation for generating an output enable signal during a read operation of the semiconductor memory device, thereby continuing the read operation of the semiconductor memory device. An output enable signal generator for stably outputting a time output enable signal.

Output enable signal.

Description

Output enable signal generator             

1 is a detailed circuit diagram illustrating an output enable signal generator according to a preferred embodiment of the present invention.

FIG. 2 is a timing diagram for explaining the operation of FIG. 1.

Description of the main parts of the drawing-

10: input unit 20: detection unit

30: delay unit 40: control unit

50: output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output enable signal generating device, and more particularly, by using a read signal as a control signal of an operation for generating an output enable signal during a read operation of the semiconductor memory device, thereby continuing the read operation of the semiconductor memory device. An output enable signal generator for stably outputting a time output enable signal.

Current semiconductor memory devices use a continuous read operation. The output enable signal generator used in a read operation of the semiconductor memory device receives an internal clock signal, a write signal, a burst signal, and a read signal generated by an external clock to enable output. Generate a signal.

The output enable signal generator of such a semiconductor memory device should maintain the enable state without resetting the output enable signal if the read signal is applied to the next clock after the burst signal is disabled during the continuous read operation.

However, in the conventional output enable signal generator, since the burst signal is used as a control signal of an operation for generating the output enable signal, the read signal is applied to the next clock after the burst signal is disabled in successive read operations. When the output enable bar signal is glitch, the output enable signal is reset.

This is becoming a more serious problem as the margin of the semiconductor memory device becomes faster and the margin becomes shorter. This problem causes a failure of the semiconductor memory device because a read operation is performed other than the previously desired operation.

Accordingly, the present invention has been made to solve the above problems, the output enable signal to stably output the output enable signal by preventing the output enable signal is reset during the continuous read operation of the semiconductor memory device The object is to provide a generator.

According to an exemplary embodiment of the present invention, an input unit detects whether a burst signal indicating a burst operation of a semiconductor memory device is enabled and detects an internal clock signal according to a write signal in a section in which the burst signal is disabled. A detection unit detecting a level change of the detected signal after detecting the output of the input unit according to a read signal, a delay unit for delaying the output signal of the detection unit, and a control unit for masking the output of the delay unit according to the read signal And an output unit configured to generate an output enable signal according to the output of the controller and the read signal.

The input unit may include a first inverter for inverting the burst signal, a second inverter for inverting the write signal, a NAND gate for performing a logical operation on the internal clock signal, an inverted write signal, and an inverted burst signal; And a delay select circuit for selecting an even number of inverter groups connected in series and a delay amount of the delay unit to delay the output signal of the NAND gate, and outputting the delayed output signal of the NAND gate to the detector.

The detection unit includes a NOR gate that logically operates an output signal and a read signal of the input unit, an odd number of inverter groups connected in series to invert and delay the output signal of the NOR gate, an output signal of the NOR gate, and the inverter. The NAND gate logic operation of the output signal of the group and the second inverter for inverting the output signal of the NAND gate.

The delay unit may be implemented as a delay selection circuit for selecting an even number of inverters connected in series to delay the output signal of the detector and a degree of delay of the output signal of the detector.

The control unit may be implemented as an inverter for inverting the read signal and a NAND gate for masking an output of the delay unit according to an output signal of the inverter.

The output unit may include a first PMOS transistor connected between a first power supply voltage terminal and a first node and operated by the read signal and connected between the first node and a second node, the first PMOS transistor being operated by an output signal of the controller. A first NMOS transistor, an inverter for inverting a power down signal, a second NMOS transistor connected between the second node and the ground and operated by an output signal of the inverter, and operated by a reset bar signal and operated by a second power supply voltage. A second PMOS transistor connected between a terminal and a third node, a third PMOS transistor operated by the read signal and connected between the first node and the third node, operated by an output signal of the inverter, and powered by a third power source A fourth PMOS transistor connected between a voltage terminal and the first node, and a latch unit configured to latch a signal of the first node to generate an output enable signal All.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a circuit diagram of an output enable signal generator according to a preferred embodiment of the present invention.

As shown in FIG. 1, an output enable signal generator according to a preferred embodiment of the present invention includes an input unit 10, a detector 20, a delay unit 30, a controller 40, and an output unit 50. do.

The input unit 10 detects whether or not the burst signal YBST indicating the burst operation of the semiconductor memory device is enabled, and the write signal WTS in the period in which the burst signal YBST is disabled. ) Detects the internal clock signal BCLK. The input unit 10 is composed of inverters I11 and I12, NAND gate NAND1, inverters I13, I14, I15, and I16, and a delay selection circuit SC10. The inverter INV11 inverts the potential of the write signal WTS that is enabled by the write command. The inverter I12 inverts the potential of the burst signal YBST informing the burst operation of the semiconductor memory element. The NAND gate NAND1 performs a logical operation on the internal clock signal BCLK generated by the external clock CLK (see FIG. 2), the output signal of the inverter I11, and the output signal of the inverter I12, thereby causing a burst signal YBST. The internal clock signal BCLK is detected according to the write signal WTS in the period in which the burst signal YBST is disabled. That is, since the write signal WTS becomes low during the read operation, when the burst signal YBST is disabled when the internal clock signal BCLK is enabled, the signal S1 becomes low and the burst signal YBST Is enabled, the signal S1 is at a high level. On the other hand, when the internal clock signal BCLK is disabled, the signal S1 becomes a high level regardless of the burst signal YBST, so that the burst signal (B1) according to the output signal S1 and the internal clock signal BCLK is generated. YBST) can be detected. Even-numbered inverters I13, I14, I15 and I16 serve to delay the signal detected through the NAND gate NAND1. The delay selection circuit SC10 selects and outputs one of the signals delayed by the two inverters I13 and I14 and the signals delayed by the four inverters I13, I14, I15 and I16.

The detector 20 detects an output of the input unit 10 according to the read signal RD, and detects a level change of the detected signal. The detector 20 includes a NOR gate NOR, an odd number of inverter groups I21, I22, I23, I24, and I25, a NAND gate NAND2, and an inverter I26. The NOR gate generates a signal S2 by performing a logic operation on the output signal S1 and the read signal RD of the input unit 10. Inverters I21, I22, I23, I24 and I25 generate signal S3 by inverting and delaying signal S2. The NAND gate NAND2 logically combines the signal S2 and the signal S3 to detect the level of the signal S2 according to the signal S3 and at the same time change the level of the signal S2 according to the signal S3. Detect. The inverter I26 inverts the detected signal S4 at this time.

The delay unit 30 delays the output of the detector 20 for a predetermined time. The delay unit 30 includes an even number of inverter groups I31, I32, I33, and I34 connected in series and a delay selection circuit SC30 to delay the output of the detector 20. FIG. The delay selection circuit SC30 selects and outputs one of the signals delayed by the two inverters I31 and I32 and the signals delayed by the four inverters I31, I32, I33 and I34.

The controller 40 masks the output of the delay unit 30 according to the read signal RD. This control unit is composed of an inverter I41 and a NAND gate NAND3. The inverter I41 inverts the read signal RD to generate the signal S6. The NAND gate NAND3 generates a signal S7 by masking a signal S5 which is an output signal of the delay unit 30 according to the read signal RD.

The output unit 50 generates an output enable signal OE through the signal S7 and the read signal RD. The output unit 50 includes a plurality of PMOS transistors P1, P2, P3 and P4, a plurality of NMOS transistors N1 and N2, an inverter I51, and a latch circuit 51. The PMOS transistor P1 is connected between the power supply voltage terminal VDD1 and the node A. The NMOS transistor N1 is operated by the read signal RD and is connected between the node A and the node B. FIG. The inverter I51 inverts the power down signal PWDD. The power down signal PWDD refers to a signal that becomes a high level only at power down. The NMOS transistor N2 operates by the output signal of the inverter I51 and is connected between the node B and the ground terminal VSS. The PMOS transistor P2 is operated by the reset bar signal RSTB and is connected between the power supply voltage terminal VDD2 and the node C. The PMOS transistor P3 operates by the read signal RD and is connected between the node A and the node C to detect the level of the output enable bar signal OBE. That is, the output enable signal generator of the present invention controls the output enable bar signal (OEB) of the read signal RD so that the glitch that may occur when the burst signal YBST is at a low level in a continuous read operation. ) To prevent the formation of. The PMOS transistor P4 operates by the output signal of the inverter I51 and is connected between the power supply voltage terminal VDD3 and the node A. FIG. The latch unit 51 is implemented with an inverter I56 for inverting the signal of the node A and an inverter I57 for reversing the inverted signal through the inverter I56.

FIG. 2 is a timing diagram for explaining the operation of FIG. 1.

Referring to Figure 2 describes the operation of the output enable signal generating apparatus according to a preferred embodiment of the present invention.

Referring to FIG. 2, the plurality of input signals input to the input unit 10 (see FIG. 1) of the output enable signal generator according to an exemplary embodiment of the present invention may include an internal clock signal BCLK, a write signal WTS, There is a burst signal YBST and a read signal RD.

The internal clock signal BCLK is a signal generated by the external clock CLK. The internal clock signal BCLK is enabled when the external clock CLK is enabled and has a shorter period of enabling than the external clock CLK. The read signal RD is a signal that is enabled by a read command. When the read command is input, the read signal RD is enabled and becomes a high level. The write signal WTS is a signal enabled by a write command and is always at a low level during a read operation. The burst signal YBST is a signal indicating the burst operation of the semiconductor memory device.

As shown in FIG. 2, the external clock CLK and the internal clock BCLK created by the external clock CLK are enabled and disabled, thereby regularly polling the rising edges. (falling) I'm drawing the edge An output enable signal generator that operates according to a plurality of input signals including the internal clock signal BCLK operates as follows.

First, the write signal WTS inverted by the internal clock signal BCLK and the inverter I11 (see FIG. 1) and the burst signal YBST inverted by the inverter I12 (see FIG. 1) are the NAND gate NAND1; 1, the delay select circuit SC10 (see FIG. 1) generates a signal S1 by adjusting a delay degree of the NAND gate NAND1 (see FIG. 1) output signal. The write signal WTS (see FIG. 1) always becomes a low level during a read operation. Therefore, if the internal clock signal BCLK is at a high level, the signal S1 is at a low level when the burst signal YBST is at a low level. On the other hand, when the internal clock signal BCLK is at a low level, the internal clock signal BCLK is at a high level regardless of the signal S1 burst signal YBST. That is, the signal S1 is output at a low or high level after being delayed by a predetermined time than the internal clock signal BCLK. The NOR gate NOR (see FIG. 1) of the detector 20 (see FIG. 1) receives the signal S1 and generates a signal S2. Therefore, the signal S2 becomes high level when the signal S1 is low level when the read signal RD is low level, and low level regardless of the potential of the signal S1 when the read signal RD is high level. Becomes The signal S3 is generated by inverting and delaying the signal S2 by the inverters I21, I22, I23, I24 and I25 (see FIG. 1) of the detector 20 (see FIG. 1). The NAND gate NAND2 (see FIG. 1) masks the signal S2 according to the signal S3 to detect a level transition of the signal S2. That is, when the signal S3 is at the low level, the signal S4 at the high level is output regardless of the potential of the signal S2. When the signal S3 is at the high level, the signal S4 at the level opposite to the signal S2 is output. By outputting the signal, the level of the signal S2 is detected. The signal S5 is outputted after the signal S4 inverted through the inverter I26 (see FIG. 1) is delayed by a predetermined time by the delay selection circuit SC30. The signal S6 is the read signal RD inverted by the inverter I41. That is, the signal S6 becomes high level when the read signal RD is low level and becomes low level when the read signal RD is high level. The signal S7 is an output signal of the control unit 40 (see FIG. 1) generated by logically combining the signal S5 and the signal S6 through the NAND gate NAND3. That is, the signal S7 becomes a low level when both the signal S5 and the signal S6 are high level, and otherwise becomes a high level. The output enable signal OE is a signal finally generated through the output unit 50 (see FIG. 1) and has a potential at a level opposite to that of the output enable bar signal OEB.

Hereinafter, the operation of the output unit 50 (see FIG. 1) for generating the output enable signal OE according to the signal S7 and the read signal RD will be described in more detail.

When the signal S7 is at the low level, the PMOS transistor P1 (see FIG. 1) is turned on to connect the power supply voltage terminal VDD1 (see FIG. 1) with the node A (see FIG. 1). At this time, when the read signal RD is at the low level, the NMOS transistor N1 (see FIG. 1) is turned off so that the signal of the node A (see FIG. 1) is at a high level and the PMOS transistor P3 (see FIG. 1) is turned on. Since the power supply voltage terminal VDD2 (see FIG. 1) and the node A (see FIG. 1) are connected, the output enable bar signal OBE has a power supply voltage value. Therefore, the output enable bar signal OEB becomes high level and the output enable bar signal OE becomes low level in contrast. On the other hand, when the read signal RD is at the high level, the NMOS transistor N1 (see FIG. 1) is turned on and connected to the ground terminal VSS (see FIG. 1), so that the signal of the node A (see FIG. 1) has a low level. The PMOS transistor P3 (see FIG. 1) is turned off so that the output enable bar signal (OEB) becomes low level as the signal of the node A (see FIG. 1). Therefore, the output enable signal OE becomes a high level as opposed to the output enable bar signal OEB. When the signal S7 is at a high level, since the PMOS transistor P1 (see FIG. 1) is turned off, the level of the node A signal is determined according to the turn-on / turn-off state of the NMOS transistor N1 (see FIG. 1). . At this time, when the read signal RD is at the low level, the NMOS transistor N1 (see FIG. 1) is turned off while the PMOS transistor P3 (see FIG. 1) is turned on. The PMOS transistor P2 (see FIG. 1) is turned on because the reset bar signal is input at a low level and the node A (see FIG. 1) is connected to the power supply voltage terminal VDD2 (see FIG. 1). Accordingly, the output enable bar signal OEB is at the high level, and the output enable bar signal OE is at the low level. On the other hand, when the read signal RD is at the high level, the NMOS transistor N1 (see FIG. 1) is turned on and connected to the ground terminal VSS (see FIG. 1), so that the signal of the node A (see FIG. 1) has a low level. do. At this time, since the read signal RD is at the high level, the PMOS transistor P3 (see FIG. 1) is turned off, and the output enable bar signal OECD is at a low level while maintaining the signal of the node A (see FIG. 1). . Therefore, the output enable signal OE is at the high level in contrast.

In this case, since the fourth PMOS transistor P4 (see FIG. 1) is controlled by the power down signal PWDD inverted by the inverter INV41 (see FIG. 1), the fourth PMOS transistor P4; 1) is turned off. Therefore, regardless of the fourth PMOS transistor P4 (see FIG. 1), the output enable signal OE has a potential opposite to that of the output enable bar signal OBE by the latch circuit.

In other words, as described above, when the output of the output enable signal generator is controlled by the burst signal YBST, when the clock is applied while the burst signal YBST is at a low level during a continuous read operation, the output enable bar While a problem arises in that a glitch is formed in the signal OBE to reset the output enable signal OE, in the present invention, the output of the output enable signal generator is controlled by the read signal RD. When the clock is applied after the burst signal YBST is disabled and low level during the read operation, the output enable bar signal OBE is not influenced by the burst signal so that glitches are not formed. , The glitch has occurred in the portion G of FIG. 2) Therefore, the output enable signal OE is not reset.

As described above, according to the present invention, by using the read signal as a control signal of the output enable signal generator, the output enable signal can be stably output during continuous read operations.

Therefore, the timing margin is secured, so that a stable read operation can be performed even at a high frequency.

Claims (6)

An input unit detecting whether a burst signal indicating a burst operation of a semiconductor memory device is enabled and detecting an internal clock signal according to a write signal in a section in which the burst signal is disabled; A detector detecting a level change of the detected signal after detecting an output of the input unit according to a read signal; A delay unit for delaying the output signal of the detector; A controller for masking an output of the delay unit according to the read signal; And And an output unit configured to generate an output enable signal according to the output of the controller and the read signal. The method of claim 1, wherein the input unit, A first inverter for inverting the burst signal; A second inverter for inverting the write signal; A NAND gate for logic operation on the internal clock signal, the inverted write signal, and the inverted burst signal; An even group of inverters connected in series to delay the output signal of the NAND gate; And And a delay selection circuit for selecting a delay amount of the delay unit and outputting the delayed output signal of the NAND gate to the detection unit. The method of claim 1, wherein the detection unit, A NOR gate for logically calculating an output signal and a read signal of the input unit; An odd number of inverter groups connected in series for inverting and delaying an output signal of the NOR gate; A NAND gate logic operation for outputting the output signal of the NOR gate and the output signal of the inverter group; And And a second inverter for inverting the output signal of the NAND gate. The method of claim 1, wherein the delay unit, An even number of inverters connected in series to delay the output signal of the detector; And And an delay selecting circuit for selecting a delay degree of the output signal of the detector. The method of claim 1, wherein the control unit An inverter for inverting the read signal; And And an NAND gate for masking an output of the delay unit according to an output signal of the inverter. The method of claim 1, wherein the output unit, A first PMOS transistor operated by an output signal of the controller and connected between a first power supply voltage terminal and a first node; A first NMOS transistor operated by the read signal and connected between the first node and a second node; An inverter inverting the power down signal; A second NMOS transistor operated by an output signal of the inverter and connected between the second node and ground; A second PMOS transistor operated by a reset bar signal and connected between the second power supply voltage terminal and the third node; A third PMOS transistor operated by the read signal and connected between the first node and the third node; A fourth PMOS transistor operated by an output signal of the inverter and connected between a third power supply voltage terminal and the first node; And And a latch unit configured to latch the signal of the first node to generate an output enable signal.

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