JP2010062578A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of forming fine metal wiring with a reduced side etch amount and restraining a via hole formed on the metal wiring from running through the metal film, in the formation of the metal wiring containing Al. <P>SOLUTION: The method of manufacturing the semiconductor device includes: a process of forming a metal wiring layer 6 in which a first TiN film 3, a metal film 4 containing Al, and a second TiN film 5 are successively laminated on a substrate; a process of forming a hard mask layer 12 in which a stopper film 7 and a silicon oxide film 8 are successively laminated on the metal wiring layer 6; a process of forming a hard mask 12a on the metal wiring layer 6 by selectively etching the hard mask layer 12; a process of forming the metal wiring 6a by performing etching with the hard mask 12a as a mask; a process of forming an interlayer insulating film 14 on the hard mask 12a and the metal wiring 6a; and a process of forming the via hole 17a on the interlayer insulating film 14 with the stopper film 7 as an etching stopper. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal wiring containing aluminum.

  As a metal wiring of a semiconductor device, a metal wiring containing aluminum such as an AlCu film, an AlSi film, and an AlSiCu film is widely used. In order to increase the reliability of the wiring, a structure in which a Ti film or a TiN film is laminated on the upper layer and the lower layer of these metal wirings is often employed.

  When these metal wirings are formed, a resist pattern is formed on a metal film containing aluminum, and etching is performed using a gas containing any or all of chlorine, carbon, inert gas, nitrogen using this as a mask. It was.

  However, since the resist pattern has to be reduced in thickness with the recent reduction in design rules, the etching resistance is lowered. For this reason, a hard mask process for etching using an inorganic insulating film such as a silicon oxide film or a silicon nitride film as a hard mask has been used (for example, see Patent Documents 1 and 2).

In the hard mask process, an additive gas such as N ₂ or CHF ₃ has been used in order to obtain a side wall protection effect for reducing the amount of side etching. However, when these additive gases are used, AlN _X , AlF _{X, and the} like that cause a reduction in yield are generated as reaction byproducts. In order to avoid this, C ₂ H ₄ was used as the additive gas (see, for example, Patent Document 3).

JP 2001-210468 A JP 2000-58507 A JP 2001-53059 A

  In the above conventional semiconductor device manufacturing method, in the method of forming an inorganic insulating film serving as a hard mask on a metal film containing aluminum and directly forming a resist pattern thereon, the dimensions of the resist pattern are reduced when the wiring pitch is reduced. There was a problem that it was difficult to satisfy the accuracy.

  Further, the method of etching the metal film by forming only the silicon nitride film as a hard mask has a problem that the silicon nitride film is a film that is easily etched by chlorine gas, and thus is not suitable for a hard mask.

  On the other hand, in the method of etching the metal film by forming only the silicon oxide film as a hard mask, the via hole penetrates the metal film because the hard mask does not become the etching stopper film in the process of forming the via hole on the metal wiring later. As a result, there is a problem that the yield of wiring is lowered.

  Further, when the wiring pitch is reduced, there is a problem that the side etch amount cannot be sufficiently reduced by the conventional technique.

  The present invention has been made to solve the above problems, and in forming a metal wiring containing aluminum, a fine metal wiring with a reduced amount of side etching can be formed, and a via hole formed on the metal wiring has a metal film. An object of the present invention is to provide an excellent method for manufacturing a semiconductor device.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal wiring layer in which a first TiN film, a metal film containing aluminum, and a second TiN film are sequentially stacked on a substrate from the lower layer; Forming a hard mask layer in which a stopper film and a silicon oxide film are sequentially laminated from the lower layer, a step of selectively etching the hard mask layer to form a hard mask on the metal wiring layer, and the hard Etching the metal wiring layer using the mask as a mask to form metal wiring, forming an interlayer insulating film on the hard mask and the metal wiring, and using the stopper film as an etching stopper, the interlayer insulating film And a step of forming a via hole.

  Other features of the present invention are described in detail below.

  According to the present invention, by optimizing the laminated structure of the hard mask formed on the metal film containing aluminum, it is possible to form a fine metal wiring with a reduced side etch amount, and to form on this metal wiring. A via hole can be prevented from penetrating the metal film, and an excellent method for manufacturing a semiconductor device can be obtained.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1-3 of this invention. The figure explaining the notch amount of the interface of a hard mask and metal wiring. The figure which shows the effect by the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same number is attached | subjected to the same component and description is abbreviate | omitted.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment 1 FIG.
1A to 1F are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment.

  First, as shown in FIG. 1A, after an element (not shown) such as a transistor is formed on a silicon substrate 1, an interlayer insulating film 2 is formed on the entire surface. For example, it is formed with a film thickness of about 300 to 400 nm by a chemical vapor deposition (hereinafter referred to as “CVD”) method or the like.

  Next, a metal wiring layer 6 in which a lower layer TiN film 3, an AlCu film 4, and an upper layer TiN film 5 are sequentially stacked is formed on the interlayer insulating film 2. The lower TiN film 3 and the upper TiN film 5 are each formed with a film thickness of about 100 nm by sputtering or the like. The AlCu film 4 is an aluminum alloy film containing about several percent of copper in the aluminum film, and is formed with a film thickness of about 500 nm by sputtering or the like.

  In this way, the metal wiring layer 6 containing aluminum is formed on the silicon substrate 1.

  In the above example, an example in which a laminated film in which the TiN film 3, the AlCu film 4, and the TiN film 5 are sequentially laminated from the lower layer is formed as the metal wiring layer 6 is shown. A laminated film in which a film, an AlCu film, a Ti film, and a TiN film are sequentially laminated may be formed.

  Next, a stopper film 7 and a silicon oxide film 8 are sequentially stacked on the metal wiring layer 6. For example, as the stopper film 7, a silicon oxynitride film (SiON film) is formed with a film thickness of about 50 nm by plasma CVD. Then, a silicon oxide film 8 is formed with a film thickness of about 100 to 200 nm by plasma CVD.

  At this time, the silicon oxynitride film has a nitrogen content of 12% or more. In place of the silicon oxynitride film, a silicon nitride film (SiN film) having a thickness of about 50 nm may be formed by plasma CVD.

  The silicon oxide film 8 may contain nitrogen (content rate of 11% or less). Further, since the silicon oxide film 8 serves as a hard mask when the metal wiring layer 6 is etched in a later process, the silicon oxide film 8 has a sufficiently thick film thickness.

  Next, a two-layer silicon oxynitride film, that is, a lower silicon oxynitride film 9 and an upper silicon oxynitride film 10 are successively formed on the silicon oxide film 8. For example, each film is formed with a film thickness of about 50 nm by plasma CVD (hereinafter, this two-layer silicon oxynitride film is referred to as “antireflection film 11” as a whole. Then, the stopper film 7, the silicon oxide film 8, the reflection film The prevention film 11 as a whole is referred to as a “hard mask layer 12”).

  In this manner, the hard mask layer 12 is formed on the metal wiring layer 6 by sequentially laminating the stopper film 7, the silicon oxide film 8, and the antireflection film 11 from the lower layer.

  As described above, a silicon oxynitride film or a silicon nitride film is used as the stopper film 7 included in the hard mask layer 12. Thereby, when forming a via hole on the metal wiring finally formed, it can suppress that a via hole penetrates a metal wiring.

  In addition, since the two-layer silicon oxynitride film is used as the antireflection film 11 included in the hard mask layer 12, the reflection from the base film is performed in the step of forming a resist pattern on the antireflection film 11 later. Thus, a fine resist pattern can be formed with good controllability.

  Furthermore, when the metal wiring layer 6 is etched using the hard mask as a mask in a later step, the hard mask becomes a forward tapered shape with a narrow upper portion. With such a shape, when a silicon oxide film using high-density plasma CVD is formed between adjacent metal wirings, embeddability can be improved.

  Further, an organic film may be used as the antireflection film 11 included in the hard mask layer 12. Thereby, compared with the case where a two-layer silicon oxynitride film is used, reflection from the base film can be more effectively suppressed, and a fine resist pattern can be formed with better controllability.

  Next, a resist pattern 13 is formed on the hard mask layer 12 by lithography. At this time, since the antireflection film 11 is formed under the resist pattern 13, the fine resist pattern 13 can be formed with good controllability.

  Next, the hard mask layer 12 shown in FIG. 1A is selectively etched using the resist pattern 13 as a mask, so that the hard mask 12a is formed on the metal wiring layer 6 as shown in FIG. Form.

Here, etching is performed using a gas containing carbon and fluorine, a gas containing oxygen, or a mixed gas containing at least two of an inert gas (for example, a CHF ₃ / CF ₄ / O ₂ / Ar mixed gas). I do.

  Further, although not shown, the resist pattern 13 is removed by ashing, and etching residues such as polymers are removed with a stripping solution mainly composed of organic amine or organic phosphoric acid.

  Next, the metal wiring layer 6 is etched using the hard mask 12a shown in FIG. 1B as a mask to form the metal wiring 6a as shown in FIG. 1C.

For example, a deposition gas containing a halogen element such as Cl ₂ , BCl ₃ , HCl or HI, an inert gas such as Ar or He, or C (carbon) such as CHF ₃ , CH ₄ or C ₂ H _4. Etching is performed using a mixed gas to which is added.

  By adding the above-described deposition gas, the amount of side etching (in which the width of the wiring becomes narrow) of the metal wiring 6a can be reduced.

Further, instead of the deposition gas, a deposition gas containing one having a conjugated double bond such as CO, CO ₂ , cycloalkane (cyclobutane, etc.), cycloalkene (cyclopentene, etc.), 1,3 butadiene, benzene, etc. It may be used. Thereby, the amount of side etching can be reduced more effectively.

  At this time, the antireflection film 11a (see FIG. 1B) is simultaneously etched when the metal wiring layer 6 is etched, and the hard mask 12a has a forward tapered shape with a narrow upper width.

  Further, since the hard mask 12a has a structure in which the silicon oxide film 8a is laminated on the stopper film 7a, the etching resistance is superior to the case where only the silicon oxynitride film (or silicon nitride film) is etched as a hard mask, The amount of side etching can be reduced and the metal wiring 6a can be formed with good controllability.

  Next, as shown in FIG. 1D, an interlayer insulating film 14 is formed on the entire surface of the metal wiring 6a and the hard mask 12a. For example, a silicon oxide film is formed with a thickness of about 1000 nm by a high density plasma CVD method.

  At this time, as described above, since the hard mask 12a has a forward taper shape with a narrow upper width, even when the wiring pitch of the metal wiring 6a is reduced, the frontage can be increased, and the adjacent metal A space between the wirings 6a can be satisfactorily embedded.

  Further, although not shown, a silicon oxide film having a thickness of about 300 to 400 nm is formed on the interlayer insulating film 14 by plasma CVD or the like. Then, the surface is polished and flattened by chemical mechanical polishing (hereinafter referred to as “CMP”).

  Next, an antireflection film 15 made of an organic film or the like is formed on the planarized silicon oxide film. Then, a resist pattern 16 is formed on the antireflection film 15 by lithography.

  Next, using the resist pattern 16 shown in FIG. 1D as a mask, the antireflection film 15 and the interlayer insulating film 14 are etched to form a via hole 17a on the metal wiring 6a as shown in FIG. Then, the stopper film 7a is exposed.

For example, after the antireflection film 15 is etched, a mixed gas containing at least two of a gas containing carbon and fluorine, a gas containing oxygen, and an inert gas (for example, C ₄ F ₈ / O ₂ / Ar The interlayer insulating film 14 is selectively etched using a mixed gas or a C ₅ F ₈ / O ₂ / Ar mixed gas).

Next, the stopper film 7a exposed on the bottom surface of the via hole 17a shown in FIG. 1E is selectively etched using a CHF ₃ / O ₂ / Ar mixed gas, as shown in FIG. 1F. Then, the upper TiN film 5a is exposed on the bottom surface of the via hole 17b.

  At this time, as described above, a silicon oxynitride film or a silicon nitride film is used as the stopper film 7 included in the hard mask layer 12 (see FIG. 1A). As a result, it is possible to suppress the via hole 17b from penetrating the metal wiring 6a by absorbing the film thickness variation of the interlayer insulating film 14 and the variation in the amount of chipping due to CMP.

Before selectively etching the stopper film 7a, the CHF ₃ / O ₂ / Ar mixed gas is used, and the flow rate ratio of CHF ₃ / O _{2 to} Ar is set higher than the etching condition of the stopper film 7a. An etching step for removing the deposition film adhering to the inner surface of the via hole 17a shown in FIG. Thereby, the upper TiN film 5a can be satisfactorily exposed on the bottom surface of the via hole 17b.

  Thereafter, although not shown, a laminated film of a Ti film and a TiN film is formed on the inner surface of the via hole 17b shown in FIG. Further, the groove formed by this laminated film is filled with a metal film such as tungsten, and the Ti film, TiN film, and metal film formed outside the groove are removed by CMP or the like, and the via hole 17b is filled with the metal film. Form.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, first, the metal wiring layer 6 containing aluminum is formed on the silicon substrate 1, and then the stopper film 7 and silicon are formed thereon from the lower layer. The hard mask layer 12 in which the oxide film 8 and the antireflection film 11 are sequentially laminated is formed.

  Next, the hard mask layer 12 was selectively etched to form a hard mask 12 a on the metal wiring layer 6.

  Then, the metal wiring layer 6 is etched using the hard mask 12a as a mask to form the metal wiring 6a.

  By forming in this way, when etching the metal wiring layer 6 to form the metal wiring 6a, the etching resistance is superior to the case where only the silicon oxynitride film (or silicon nitride film) is etched as a hard mask, The amount of side etching can be reduced and the metal wiring 6a can be formed with good controllability. Further, it is possible to improve the embedding property between the adjacent metal wirings 6a, and to reduce the inter-wiring capacitance between these metal wirings and the via resistance formed on the metal wiring 6a.

  Further, it is possible to suppress the via hole 17b formed on the wiring from penetrating into the metal wiring 6a, and to suppress a decrease in the yield of forming the via hole.

Embodiment 2. FIG.
In the method of manufacturing the semiconductor device according to the present embodiment, a metal film is used as the stopper film 7 included in the hard mask layer 12 (see FIG. 1A) shown in the first embodiment. .

  Since other configurations are the same as those in the first embodiment, the differences from the first embodiment will be mainly described with reference to FIGS. 1A to 1F as appropriate.

  First, after an element (not shown) such as a transistor is formed on the silicon substrate 1, the process from the formation of the interlayer insulating film 2 over the entire surface to the formation of the metal wiring layer 6 containing aluminum (FIG. 1 (FIG. (a) is performed in the same manner as in the first embodiment.

  Thereafter, a hard mask layer 12 is formed on the metal wiring layer 6. At this time, the stopper film 7 included in the hard mask layer 12 is a metal made of any one of tungsten, tantalum, platinum, silver, gold, nickel, ruthenium, cobalt, iron, manganese, iridium, zirconium, and indium. Use a membrane. Here, a tungsten film is used.

  Thereafter, the process from the step of forming the silicon oxide film 8 on the stopper film 7 (see FIG. 1A) to the step of forming the resist pattern 16 on the antireflection film 15 (see FIG. 1D). ) In the same manner as in the first embodiment.

  Next, using the resist pattern 16 shown in FIG. 1D as a mask, the antireflection film 15 and the interlayer insulating film 14 are etched to form a via hole 17a on the metal wiring 6a as shown in FIG. Then, the stopper film 7a (tungsten film) is exposed.

  At this time, if the etching rate of the interlayer insulating film 14 (silicon oxide film) with respect to the etching rate of the stopper film 7a is defined as "etching selection ratio", the etching selectivity when the tungsten film is used as the stopper film is silicon It is larger than the etching selectivity when an oxynitride film (or silicon nitride film) is used as a stopper film.

  Therefore, when the via hole 17a is formed on the metal wiring 6a, the via hole 17a can be more effectively prevented from penetrating the metal wiring 6a than in the first embodiment.

  The tungsten film is a metal film, and even if the via film is formed by embedding the metal film in the via hole 17a with the stopper film 7a exposed at the bottom surface of the via hole 17a, the conductivity is not lost. The step of removing the film 7a can be omitted. Furthermore, since the tungsten film is laminated on the metal wiring 6a, the resistance of the metal wiring 6a can be lowered.

  A similar effect is obtained when a metal film other than the tungsten film described above is used as the stopper film.

  Thereafter, the stopper film 7a may be removed by etching as in the first embodiment (see FIG. 1F).

  Since other configurations are the same as those in the first embodiment, description thereof is omitted.

  As described above, the manufacturing method of the semiconductor device according to the present embodiment uses tungsten, tantalum, platinum, silver, gold, nickel, as the stopper film 7 included in the hard mask layer 12 shown in the first embodiment. A metal film made of any one of ruthenium, cobalt, iron, manganese, iridium, zirconium, and indium is used.

  By forming in this way, when the via hole 17a is formed on the metal wiring 6a, it is possible to suppress the penetration into the metal wiring 6a more effectively than in the first embodiment.

  In addition, even if the via film is formed by embedding the metal film in the via hole 17a with the stopper film 7a exposed at the bottom surface of the via hole 17a, the conductivity is not lost, so the step of removing the stopper film 7a is performed. Can be omitted. Furthermore, the resistance of the metal wiring 6a can be lowered by stacking the tungsten film on the metal wiring 6a.

Embodiment 3 FIG.
In the method of manufacturing the semiconductor device according to the present embodiment, in the step of forming the silicon oxide film 8 shown in the first embodiment (see FIG. 1A), the composition ratio of oxygen to silicon is set within a specific range. The temperature is set as a specific range.

  In addition, the step of etching the metal wiring layer 6 to form the metal wiring 6a (see FIG. 1C) is performed by etching one of the specific films formed on another silicon substrate in advance. This is performed using an apparatus.

  Since other configurations are the same as those in the first and second embodiments, the differences from the first and second embodiments will be mainly described with reference to FIGS. 1A to 1F as appropriate.

  First, after an element (not shown) such as a transistor is formed on the silicon substrate 1, the process from the step of forming the interlayer insulating film 2 over the entire surface to the step of forming the stopper film 7 on the metal wiring layer 6 ( 1A) is performed in the same manner as in the first embodiment (or the second embodiment).

  After that, the silicon oxide film 8 included in the hard mask layer 12 shown in the first embodiment is formed using a plasma CVD method so that the composition ratio of oxygen to silicon is in the range of 1.5 to 2.

  By forming in this way, in the step (see FIG. 1C) of etching the metal wiring layer 6 shown in the first embodiment to form the metal wiring 6a (see FIG. 1C), the upper TiN film 5a is replaced with the silicon oxide film 8a. It is possible to suppress the reaction and reduce the amount of notches generated at the interface between the hard mask 12a and the metal wiring 6a.

  Alternatively, the silicon oxide film 8 included in the hard mask layer 12 may be formed using a plasma CVD method at a temperature in the range of 290 to 400 ° C.

  By forming in this way, the notch amount generated at the interface between the hard mask 12a and the metal wiring 6a can be reduced in the same manner as described above.

  Thereafter, the step of forming the antireflection film 11 on the silicon oxide film 8 and the step of forming the resist pattern 13 on the hard mask layer 12 (see FIG. 1A) are the same as in the first embodiment. To do.

  Next, in the step of etching the metal wiring layer 6 (see FIG. 1C), a silicon oxide film, silicon nitride film, or metal wiring layer 6 (see FIG. 1) formed on another silicon substrate different from the silicon substrate 1 is used. 1 (b)), the etching is performed using an etching apparatus that etches one of the metal films of the same type as the metal film included in 1).

  For example, before etching the metal wiring layer 6, a silicon oxide film, a silicon nitride film, or TiN contained in the metal wiring layer 6 formed on a silicon substrate different from the silicon substrate 1 on which the metal wiring layer 6 is formed. One of the films and the metal film such as the AlCu film is etched (this process is hereinafter referred to as “seasoning process”). Then, the metal wiring layer 6 is etched using an etching apparatus that has been subjected to seasoning.

  By etching the metal wiring layer 6 in this way, a reaction product containing a trace amount of oxygen, nitrogen, and metal supplied from the film etched in the seasoning process remains in the etching apparatus, and the metal wiring layer 6 Since the side walls of the metal wiring 6a are protected during the etching, the notch amount A at the interface between the hard mask 12a and the metal wiring 6a shown in FIG. 2 can be reduced.

  Thereby, the notch amount A at the interface between the hard mask 12a and the metal wiring 6a can be further reduced.

  FIG. 3A shows the relationship between the composition ratio of oxygen (O) to silicon (Si) in the silicon oxide film 8 and the notch amount A when the seasoning process is not performed before the metal wiring layer 6 is etched. The data shows the relationship between the formation temperature of the silicon oxide film 8 and the notch amount A.

  From these data, it can be seen that the notch amount A can be reduced by setting the composition ratio of oxygen to silicon in the silicon oxide film 8 in the range of 1.5 to 2. Moreover, it turns out that there exists an effect which further reduces the notch amount A by making formation temperature into the range of 290-400 degreeC.

  FIG. 3B shows that when a seasoning process is performed before the metal wiring layer 6 is etched, the composition ratio of oxygen to silicon in the silicon oxide film 8 is 1.7, and the generation temperature of the silicon oxide film 8 is 420 ° C. It is the data which shows the notch amount A at the time of doing. From the comparison with FIG. 3A, it can be seen that the effect of reducing the notch amount A is further increased by performing the seasoning process.

  From these results, it can be seen that the manufacturing method of the present embodiment has an effect of reducing the notch amount at the interface between the hard mask 12a and the metal wiring 6a.

  Thereby, the embedding property between the adjacent metal wirings 6a is improved, and the capacitance variation between these metal wirings can be reduced. In addition, it is possible to prevent the upper TiN film 5a from being reduced in the metal wiring 6a, and to reduce variations in resistance of vias formed on the metal wiring 6a.

  Since other configurations are the same as those in the first embodiment (or the second embodiment), description thereof is omitted.

  As described above, the manufacturing method of the semiconductor device according to the present embodiment allows the silicon oxide film 8 included in the hard mask layer 12 described in the first embodiment (or the second embodiment) to be oxygenated with respect to silicon. The plasma CVD method is used to form the composition ratio in the range of 1.5-2.

  In addition, the silicon oxide film 8 included in the hard mask layer 12 is formed using a plasma CVD method at a temperature in the range of 290 to 400 ° C.

  Further, the process of forming the metal wiring 6a by etching the metal wiring layer 6 using the hard mask 12a shown in the first embodiment (or the second embodiment) as a mask is performed on another silicon substrate different from the silicon substrate 1. The etching was performed using an etching apparatus in which any one of the silicon oxide film, the silicon nitride film, and the metal film of the same type as the metal film included in the metal wiring layer 6 was etched.

  By forming in this way, in addition to the effects of the first and second embodiments, the notch amount at the interface between the hard mask 12a and the metal wiring 6a can be reduced.

  Thereby, the embedding property between the adjacent metal wirings 6a is improved, and the capacitance variation between these metal wirings can be reduced. In addition, it is possible to prevent the upper TiN film 5a from being reduced in the metal wiring 6a, and to reduce variations in resistance of vias formed on the metal wiring 6a.

  DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2 interlayer insulation film, 3 lower layer TiN film, 4 AlCu film, 5 upper layer TiN film, 6 metal wiring layer, 6a metal wiring, 7a stopper film, 8 silicon oxide film, 11 antireflection film, 12 hard mask layer 12a hard mask, 14 interlayer insulation film, 17a, 17b via hole.

Claims (12)

Forming a metal wiring layer in which a first TiN film, a metal film containing aluminum, and a second TiN film are sequentially laminated on a substrate from the lower layer;
Forming a hard mask layer in which a stopper film and a silicon oxide film are sequentially laminated on the metal wiring layer from a lower layer;
Selectively etching the hard mask layer to form a hard mask on the metal wiring layer;
Etching the metal wiring layer using the hard mask as a mask to form a metal wiring;
Forming an interlayer insulating film on the hard mask and the metal wiring;
Forming a via hole in the interlayer insulating film using the stopper film as an etching stopper.   2. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxynitride film or a silicon nitride film is used as the stopper film included in the hard mask layer.   As the stopper film included in the hard mask layer, a metal film made of any metal of tungsten, tantalum, platinum, silver, gold, nickel, ruthenium, cobalt, iron, manganese, iridium, zirconium, and indium is used. The method of manufacturing a semiconductor device according to claim 1.   2. The silicon oxide film included in the hard mask layer is formed using a plasma chemical vapor deposition method so that a composition ratio of oxygen to silicon is in a range of 1.5-2. The manufacturing method of the semiconductor device in any one of -3. The hard mask layer further includes an antireflection layer provided on the silicon oxide film,
5. The semiconductor according to claim 1, wherein the silicon oxide film included in the hard mask layer is formed by plasma enhanced chemical vapor deposition at a temperature in a range of 290 to 400 ° C. 6. Device manufacturing method. The hard mask layer further includes an antireflection layer provided on the silicon oxide film,
6. The method of manufacturing a semiconductor device according to claim 1, wherein a two-layered silicon oxynitride film is used as the antireflection film included in the hard mask layer.   6. The method of manufacturing a semiconductor device according to claim 5, wherein an organic film is used as the antireflection film included in the hard mask layer.   The step of etching the metal wiring layer is performed by any of a silicon oxide film, a silicon nitride film formed on a different substrate different from the substrate, or a metal film of the same type as the metal film included in the metal wiring layer. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed using an etching apparatus that etches the film.   9. The method of forming a via hole according to claim 1, wherein a mixed gas containing at least two of a gas containing carbon and fluorine, a gas containing oxygen, and an inert gas is used. The manufacturing method of the semiconductor device in any one.   The method of manufacturing a semiconductor device according to claim 9, wherein the mixed gas includes a gas containing carbon and fluorine. The method for manufacturing a semiconductor device according to claim 9, wherein the mixed gas is a C ₄ F ₈ / O ₂ / Ar-based mixed gas or a C ₅ F ₈ / O ₂ / Ar-based mixed gas. Forming a metal wiring material in which a first TiN film, a metal film containing aluminum, and a second TiN film are sequentially laminated on a substrate from a lower layer;
Forming a hard mask layer in which a stopper film, a silicon oxide film, and an antireflection film are sequentially laminated from the lower layer on the metal wiring material;
Selectively etching the hard mask layer to form a hard mask on the metal wiring material;
Etching the metal wiring material using the hard mask as a mask to form a metal wiring;
Forming an interlayer insulating film covering a side surface and an upper surface of the metal wiring;
Forming a contact hole in the interlayer insulating film by etching stopping at the stopper film,
A method of manufacturing a semiconductor device, wherein a silicon oxynitride film or a silicon nitride film is used as a film included in the hard mask layer.

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