JPH10242274A - Manufacture of multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the protuberance of lower-layer wiring under a connection hole and the occurrence of voids within the lower-layer wiring, when connecting the lower wiring layer with the upper wiring layer of a multi-layer wiring board by connection hole stopping technique. SOLUTION: A multilayer wiring board is manufactured by forming an etching stopper layer 10 and a lower-layer insulating film 2 in order on a lower wiring layer 1, and making a connection hole 3 in the interlayer insulating film 2 and the etching stopper layer 10 so that the etching stopper layer 10 may remain at the bottom of the connection hole 3, and making an upper wiring layer 5 to fill the connection hole 3 with the upper wiring layer 3 or filling the connection hole with the upper wiring material together with the formation of the upper wiring layer after heat treatment, and connecting the lower wiring layer 1 with the upper wiring layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a multilayer wiring board in which a lower wiring layer and an upper wiring layer of a multilayer wiring board are connected by a connection hole filling technique.

[0002]

2. Description of the Related Art With the improvement in the degree of integration of LSIs, techniques for connecting a lower wiring layer and an upper wiring layer by embedding fine connection holes have been actively studied.

As the embedding technique, a CVD method, a high-temperature sputtering method, a reflow method, a high-pressure reflow method and the like have been studied. Among them, the high-pressure reflow method is considered to be promising in that an extremely high embedding performance can be obtained. .

FIG. 3 shows a method of connecting an upper wiring layer and a lower wiring layer using an embedding technique based on a high-pressure reflow method.

First, an interlayer insulating film 2 is formed on a lower wiring layer 1 of a substrate for forming a multilayer wiring board (FIG. 1A), and a connection hole 3 reaching the lower wiring layer 1 is opened in the interlayer insulating film 2. Then, the substrate is heated to 400 to 500 ° C. to degas moisture and the like in the interlayer insulating film 2.

Next, Ti or TiN or a laminated film of these is formed as a base layer 4 by a normal sputtering method (FIG. 1C), and an upper wiring layer 5 is formed thereon.
A wiring main material such as that described above is usually formed by a sputtering method, thereby closing the upper portion of the connection hole 3 (FIG. 4D). The atmosphere for forming the upper wiring layer 5 is 10 ⁻⁶ to 10 ⁻⁶ .
A high vacuum of about 10 ⁻⁷ Pa is used, and the substrate temperature is set to about 400 ° C.

Subsequently, the substrate is placed under a high vacuum atmosphere.
At about 400 ° C., the upper wiring layer 5 is softened.
A high-pressure gas such as r is introduced into the system, and the material for forming the upper wiring layer 5 is reflowed by the high-pressure gas and pushed into the connection holes 3 (FIG. 3E). Thus, the upper wiring layer 5 and the lower wiring layer 1 are connected by filling the connection holes 3 with the material for forming the upper wiring layer 5 (FIG. 4F).

In the technique of filling the connection holes by the high-pressure reflow method, in order to obtain a good filling property, the substrate is heat-treated before the formation of the underlayer 4 by the sputtering method.
It is important to degas moisture and the like in the interlayer insulating film 2. If the degassing is insufficient, moisture is released from the interlayer insulating film 2 by heating the substrate during the formation of the underlayer 4 or the upper wiring layer 5 or during reflow of the upper wiring layer 5, and the underlayer 4 and the upper layer An oxide layer is formed at the interface with the wiring layer 5, and the embedding property is likely to deteriorate. Note that this heat treatment is performed as an annealing before the formation of the underlayer 4 by the sputtering method or in a sputtering apparatus immediately before the formation of the underlayer 4.

[0009]

However, in the conventional technique of filling the connection holes by the high-pressure reflow method, as shown in FIG. 4, the bottom of the connection holes 3 is exposed at the time of heat treatment before the formation of the underlayer 4. The raised lower wiring layer 1 is raised, and a void 6 is generated in the lower wiring layer 1 due to the reaction of the protrusion of the lower wiring layer 1, resulting in a problem that a wiring failure and a reduction in reliability are caused.

An object of the present invention is to solve the above-described problems of the prior art. In connecting a lower wiring layer and an upper wiring layer of a multilayer wiring board by a technique of burying a connection hole, an upper wiring is used. Improves the embedding property by heat treatment of the layer, suppresses the protrusion of the lower wiring at the bottom of the connection hole,
The purpose is to improve the reliability of wiring.

[0011]

In order to achieve the above object, the present invention provides an etching stopper layer and an interlayer insulating film sequentially formed on a lower wiring layer, and a connection hole is formed in the interlayer insulating film and the etching stopper layer. An opening is formed so that the etching stopper layer remains at the bottom of the connection hole, and an upper wiring layer is formed after the heat treatment, and the upper wiring layer is buried in the connection hole, or the upper wiring is formed together with the formation of the upper wiring layer after the heat treatment. Provided is a method for manufacturing a multilayer wiring board, characterized by filling connection holes with a material and connecting a lower wiring layer and an upper wiring layer.

In the present invention, an etching stopper layer is formed between the lower wiring layer and the interlayer insulating film, and when opening the connection hole, the etching stopper layer is left at the bottom of the connection hole. Therefore, in obtaining a multilayer wiring board in which the lower wiring layer and the upper wiring layer are connected by using the connection hole embedding technique, after the connection hole is opened, the heat treatment for degassing from the interlayer insulating film is performed at the bottom of the connection hole. In this case, the etching stopper layer is exposed instead of the lower wiring layer.

Therefore, it is possible to prevent the lower wiring layer from being raised at the bottom of the connection hole due to the heat treatment, and the occurrence of voids in the lower wiring layer due to this, thereby preventing the occurrence of wiring failure.
In addition, the embedding property of the connection hole is improved, and the inside of the connection hole can be completely filled with the wiring material without generating a void inside the connection hole. Furthermore, even if a void is formed in the lower wiring layer below the connection hole due to electromigration, the etching stopper layer functions as a current bypass layer. This redundancy effect ensures conduction between the lower wiring layer and the upper wiring layer. Will be secured.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

FIG. 1 is a process explanatory view of a manufacturing method according to one embodiment of the present invention.

As shown in FIG. 1A, in the present invention, first, an etching stopper layer 10 and an interlayer insulating film 2 are sequentially formed on a lower wiring layer 1 constituting a multilayer wiring board.

Here, the material for forming the lower wiring layer 1, the interlayer insulating film 2, and the underlayer 4 and the upper wiring layer 5, which will be described later, is not particularly limited, and is conventionally used in high-density multilayer wiring boards such as LSIs. Can be used. For example, the lower wiring layer and the upper wiring layer are made of Al, Al-Cu, Al-S
i, Al alloys such as Al-Si-Cu, Al-Ge, A
It can be formed by forming a wiring material such as g, Cu, Cu-Zr or the like by a sputtering method or the like. in this case,
The wiring layer may have a stacked structure of a plurality of types of wiring layers.

As the interlayer insulating film 2, an insulating film made of, for example, plasma CVD TEOS-SiO ₂ , O ₃ -TEOS, or the like can be formed.

On the other hand, as the etching stopper layer 10 characteristic of the present invention, a high melting point metal such as Ti, W, Ta, TiW or the like having a melting point of 1500 ° C. or more, an alloy thereof, or a nitride thereof (for example, TiN, WN) is used. , TiWN, etc.). Further, the etching stopper layer 10 can have a laminated structure of two or more of these.

The thickness of the etching stopper layer 10 is 80
It is preferably at least nm. If this layer thickness is too thin, as will be described later, the connection hole 3
It is difficult to sufficiently secure the thickness of the etching stopper layer 10 remaining at the bottom of the substrate, and it is difficult to obtain the effect of forming the etching stopper layer 10. on the other hand,
The upper limit of the thickness of the etching stopper layer 10 is 1
It is preferable that the thickness be not more than 00 nm. If the thickness of the etching stopper layer 10 is excessively increased, the total thickness of the wiring is increased, and the wiring aberration is increased.

The lower wiring layer 1 and the etching stopper layer 10 can be appropriately etched to form a predetermined wiring pattern.

Next, a connection hole 3 is formed in the interlayer insulating film 2 and the etching stopper layer 10 and the etching stopper layer 1 is formed.
0 is opened so as to remain at the bottom of the connection hole 3 (FIG. 4B). In this case, it is preferable that the thickness of the etching stopper layer 10 remaining at the bottom of the connection hole 3 be 20 nm or more. If the thickness of the etching stopper layer 10 remaining at the bottom of the connection hole 3 is not sufficiently secured,
Since the effect of forming the etching stopper layer 10 cannot be obtained, it is difficult to reliably prevent the lower wiring layer 1 from being raised or voided by the heat treatment after the opening of the connection hole 3.

The diameter and depth of the connection hole 3 are not particularly limited as long as the etching stopper layer 10 remains at the bottom of the connection hole 3. The diameter and depth of the connection hole 3 are appropriately determined according to the application of the multilayer wiring board, the process of filling the connection hole 3, and the like. Can be set, but usually
The diameter of the connection hole 3 is 300-500 nm, and the depth is 600-1.
It is preferably set to 000 nm.

After the connection holes 3 are opened, heat treatment is performed. This heat treatment is performed for degassing from the interlayer insulating film 2 in the same manner as the heat treatment performed by the conventional embedding technique by the high-pressure reflow method. It can be set appropriately according to the material and the like. For example, an annealing process or the like in which heating is performed at 450 to 500 ° C. for about 0.5 hour, and then cooling is performed.

After the heat treatment, the upper wiring layer 5 is formed. Prior to this, as shown in FIG. 1C, it is necessary to form a base layer 4 covering the surface of the substrate having the connection holes 3 formed therein. It is preferable from the viewpoint of improving the embedding property and the reliability. The underlayer 4 has a melting point of 150, such as Ti, W, Ta, or TiW.
A single film or a laminated film of a high melting point metal or an alloy thereof at 0 ° C. or more, or a nitride thereof is formed to a thickness of 30 to 70 n.
m.

The upper wiring layer 5 is formed in a manner corresponding to the process of filling the connection holes 3 and the like. For example, when the connection hole 3 is buried by a high-pressure reflow method, the upper wiring layer 5 is formed so as to close the upper part of the connection hole 3 as shown in FIG. On the other hand, when the connection hole 3 is buried by the high-temperature reflow method or the high-temperature sputtering method, the upper wiring layer 5 is
Is formed so that the upper part is not closed. In addition, the connection hole 3
1 is buried by a high-temperature sputtering method, the burying of the connection holes 3 progresses simultaneously with the formation of the upper wiring layer 5.
The state shown in FIG. 11E is obtained directly from the state shown in FIG.

As described above, the upper wiring layer 5 is made of Al,
Al-Cu, Al-Si, Al-Si-Cu, Al-G
It can be formed by forming a wiring material such as an Al alloy such as e, Ag, Cu, Cu-Zr or the like by a sputtering method or the like. In this case, the wiring layer may have a stacked structure of a plurality of types of wiring layers.

After or together with the formation of the upper wiring layer 5, the connection hole 3 is buried as shown in FIG. 1E by a reflow method or a sputtering method, in particular, a high-pressure reflow method or a high-temperature sputtering method. 1 and the upper wiring layer 5 are connected.
Here, the reflow method means that a high temperature state of about 500 ° C. is obtained after sputtering, the high-pressure reflow method means that pressure is applied while being heated to about 400 ° C. after sputtering, and the sputtering method is usually used. DC magnetron sputtering, etc., and the high temperature sputtering method refers to sputtering at a high temperature of about 500 ° C. When the connection holes 3 are buried by reflow or sputtering, the atmosphere pressure is 10 ⁻⁷ to 10 ⁻⁶ Pa, including the transfer of the substrate in the middle.
It is preferably performed in a high vacuum atmosphere.

In the process of connecting the lower wiring layer 1 and the upper wiring layer 5 by filling the connection holes 3 as described above, a preheating process, an oxide film removing process, and the like can be appropriately performed as necessary.

The method of the present invention can also be applied to the case where the lower wiring layer 1 and the upper wiring layer 5 are connected, and then the upper wiring layer 5 is connected to the upper wiring layer. Therefore, by repeating the method of the present invention, for example, as shown in FIG. 2, the lower wiring layer 1 and the first upper wiring layer 5
a by connecting the first upper wiring layer 5a and the second upper wiring layer 5b by burying the second connection hole 3b. Can be.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.

Example 1 (Method of Manufacturing Multilayer Wiring Board for Filling Connection Holes by Reflow Method) (1) Formation of Lower Wiring Layer and Etching Stopper Layer Lower wiring by DC magnetron sputtering on a substrate that has been subjected to ordinary LSI processing. A layer and an etching stopper layer were formed (see FIG. 1A). In this case, the layer structure of the lower wiring layer and the etching stopper layer is TiN100
nm / Al-Cu500nm / TiN50nm / Ti2
A layered structure having a thickness of 0 nm was formed under the following film forming conditions.

Ti film formation conditions DC power: 6 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film formation temperature: 200 ° C. TiN film formation conditions DC power: 12 kW Process gas: Ar / N ₂ = 20/70 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C. Al-Cu film forming conditions DC power: 15 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C.

(2) Opening of connection hole On the lower wiring layer formed in (1), as an interlayer insulating film, plasma CVD TEOS-SiO ₂ and, in some cases, O ₃
-600 nm of TEOS was deposited, and a connection hole was opened by an RIE process (see FIG. 1B). In this case, the bottom of the connection hole was located in the TiN / Ti layer so that the Al-Cu layer as the lower wiring layer was not exposed. Also,
The size of the connection hole was 0.6 μm in depth and 0.3 μm in diameter.

(3) Annealing Treatment (Heat Treatment) In burying the wiring material in the upper wiring layer performed afterward, in order to obtain a good burying property, the interlayer insulating film was degassed without annealing treatment. In this case, the annealing treatment was foreness annealing. The annealing conditions were as follows.

Annealing conditions Temperature: 450 ° C. Time: 30 min Gas: N ₂

(4) Formation of Upper Wiring Layer First, a preheat treatment was performed under the following conditions using a gas heating method from the back surface of the substrate.

Preheating conditions Temperature: 500 ° C. Time: 1 min Gas: Ar Backside gas pressure: 1000 Pa

Next, the oxide film on the etching stopper layer at the bottom of the connection hole was removed by ordinary Ar sputter etching.

Then, as the underlayer and the upper wiring layer, T
i, TiN, and Al—Cu were deposited by DC magnetron sputtering under the same film forming conditions as those for forming the lower wiring layer and the etching stopper layer described above, for 20 nm and 50 nm, respectively.
m, 500 nm was formed.

(5) Embedding Connection Holes The substrate was heated under the following reflow conditions to embed the connection holes (see FIG. 1E). In this case, as the heating method, a gas heating method from the back surface of the substrate was used. In addition, this reflow step is performed under the atmospheric pressure of 10 ⁻⁷ including the transfer of the substrate.
The test was performed under a high vacuum of about Pa.

Reflow conditions Temperature: 500 ° C. Time: 1 min Gas: Ar Backside gas pressure: 1000 Pa

When the connection state between the lower wiring layer and the upper wiring layer of the multilayer wiring board thus obtained was observed by SEM, no protrusion was found at the bottom of the connection hole, and no void was found in the lower wiring layer. No observation was observed, and the lower wiring layer and the upper wiring layer were well connected by the connection holes.

Example 2 (method of manufacturing a multilayer wiring board in which connection holes are buried by a high-pressure reflow method)
After repeating each of the steps (4), (5) the process after filling the connection holes was performed as follows.

(5) Embedding of Connection Hole The substrate was heated under the following high-pressure reflow conditions to perform high-pressure reflow embedding.

High-pressure reflow conditions Process gas: Ar pressure: 70 MPa Reflow time: 1 min Substrate temperature: 450 ° C.

When the connection state between the lower wiring layer and the upper wiring layer of the multilayer wiring board thus obtained was observed by SEM, no protrusion was found at the bottom of the connection hole, and no void was found in the lower wiring layer. No observation was observed, and the lower wiring layer and the upper wiring layer were well connected by the connection holes.

[0048]

According to the present invention, when the lower wiring layer and the upper wiring layer of the multilayer wiring board are connected by the connection hole filling technique, the embedding property by the heat treatment of the upper wiring layer can be improved. . In addition, it is possible to suppress the protrusion of the lower wiring below the connection hole and the generation of voids in the lower wiring layer. Further, the reliability of the wiring can be improved due to the redundancy effect of the etching stopper layer against electromigration.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of the present invention.

FIG. 2 is a cross-sectional view of a multilayer wiring board obtained by the present invention.

FIG. 3 is an explanatory view of a process in a conventional method.

FIG. 4 is an explanatory diagram of a problem of the conventional method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Lower wiring layer, 2 ... Interlayer insulating film, 3 ... Connection hole, 4 ... Underlayer, 5 ... Upper wiring layer, 10 ... Etching stopper layer

Claims (6)

[Claims] An etching stopper layer and an interlayer insulating film are sequentially formed on a lower wiring layer, and a connection hole is opened in the interlayer insulating film and the etching stopper layer such that the etching stopper layer remains at the bottom of the connection hole. After the heat treatment, the upper wiring layer is formed, and the upper wiring layer is buried in the connection hole, or after the heat treatment, the connection hole is buried with the upper wiring material together with the formation of the upper wiring layer, and the lower wiring layer and the upper wiring layer are separated. A method for manufacturing a multilayer wiring board, comprising connecting. 2. The method according to claim 1, wherein after the heat treatment, an upper wiring layer is formed so as to close the upper portion of the connection hole, and the upper wiring layer is embedded in the connection hole by a high-pressure reflow method. 3. An etching stopper layer comprising Ti, W,
3. The method for manufacturing a multilayer wiring board according to claim 1, wherein the multilayer wiring board is formed from Ta, TiW, or an alloy containing a nitride thereof. 4. The method according to claim 1, wherein the thickness of the etching stopper layer before opening the connection hole is 80 nm or more. 5. The method for manufacturing a multilayer wiring board according to claim 1, wherein after forming the connection hole, a base layer is laminated on the substrate surface and an upper wiring layer is formed thereon. 6. The method for manufacturing a multilayer wiring board according to claim 5, wherein the underlayer is made of a laminated film of TiN and Ti.