JP2010054931A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve further thickness reduction in a plasma display device without lowering an effective screen rate and without lowering an electric power collecting rate. <P>SOLUTION: The plasma display device has, in a chassis, a panel which includes a plurality of electrical discharge cells which has scanning electrodes and sustaining electrodes, a scanning side circuit board 100 where a sustain pulse generating circuit which generates a sustain pulse to be applied to the scanning electrodes is mounted, and a sustaining side circuit board where a sustain pulse generating circuit which generates a sustain pulse to be applied to the sustaining electrodes is mounted, wherein a plurality of capacitors are mounted on the scanning side circuit board 100 and the sustaining side circuit board, and the plurality of capacitors 151 to 158 are mounted in a vertical direction in the chassis and further the longest side of each of the plurality of capacitors 151 to 158 is arranged in a vertical direction in the chassis. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device which is a thin image display device.

  A typical plasma display panel (hereinafter abbreviated as “panel”) as an image display device having a large number of pixels arranged in a plane is a large number of glass substrates disposed between opposed front and back substrates. A discharge cell is formed. A plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed on the front substrate in parallel, and a plurality of parallel data electrodes are formed on the rear substrate. The front substrate and the rear substrate are arranged opposite to each other so as to be three-dimensionally crossed and sealed. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  As a method for driving the panel, a subfield method in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields to emit light is generally used. Each subfield has an initialization period, an address period, and a sustain period. Initialization discharge is generated in the initialization period, and address discharge is selectively generated in the address period to form wall charges. In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge has occurred to display an image.

  In such a plasma display device, various power consumption reduction techniques have been proposed in order to reduce power consumption. In particular, a so-called power recovery circuit is disclosed as one of the techniques for reducing power consumption in the sustain period (see, for example, Patent Document 1). Patent Document 1 focuses on the fact that the scan electrode and the sustain electrode are capacitive loads having interelectrode capacitance, and includes a power recovery inductor and a power recovery capacitor, and the power recovery inductor and electrode An electric power recovery circuit is disclosed in which LC resonance is performed between the inter-electrode capacitance, the electric charge stored in the inter-electrode capacitance is recovered in an electric power recovery capacitor, and the recovered electric charge is reused for driving the display electrode pair.

  The plasma display device is configured by attaching a panel and its drive circuit to a chassis member and housing them in a housing made up of a front frame and a back cover. The panel itself is a thin image display device, and its thickness is about several millimeters. However, there is a problem of the size of circuit parts and other members, and further there is a problem of heat generation of the panel and the drive circuit. The thickness of the device was about 10 cm.

  As a structure of a plasma display device that realizes further reduction in thickness, a panel is attached to the front side of a flat plate-shaped chassis member, and a large size is provided in a region of the chassis member other than the back side of the region where the panel is arranged. A structure in which a drive circuit block including the circuit components is attached and disposed is disclosed (for example, see Patent Document 2).

In order to solve the problem of heat generation, a structure in which a heat radiating plate is attached to the back of the panel and a heat radiating fan for exhaust is provided to efficiently release heat to the outside of the housing (see, for example, Patent Document 3) A structure in which a heat radiating plate is attached to the back of the circuit board and the circuit board is divided into a plurality of parts and heat radiating fins are provided between the circuit boards is proposed (for example, see Patent Document 4).
Japanese Examined Patent Publication No. 7-109542 JP 2004-198580 A JP-A-9-233406 Japanese Patent Laid-Open No. 11-251772

  However, according to the structure described in Patent Document 2, there is a problem that the image display area relative to the entire area of the plasma display device as viewed from the front side, that is, a so-called effective screen ratio is significantly reduced. In addition, if the plasma display device is made thinner without reducing the effective screen ratio, the space inside the housing becomes narrower, and heat generated in the panel and drive circuit tends to stay inside the housing, increasing the temperature of circuit components. is there. In particular, when the temperature of the circuit components constituting the power recovery circuit rises, there is a problem that power recovery efficiency decreases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a plasma display device that achieves further thinning without reducing the effective screen ratio and without reducing power recovery efficiency. To do.

  In order to achieve the above object, a plasma display apparatus according to the present invention includes a panel having a plurality of discharge cells each having a scan electrode and a sustain electrode and a scan pulse generating circuit for generating a sustain pulse to be applied to the scan electrode. A plasma display apparatus having a side circuit board and a sustain side circuit board equipped with a sustain pulse generating circuit for generating a sustain pulse applied to the sustain electrode inside the housing, the scan side circuit board and the sustain side circuit board Each capacitor has a plurality of capacitors mounted thereon, and the plurality of capacitors are mounted so that they are arranged in the vertical direction inside the housing, and the longest side of each of the plurality of capacitors is arranged in the vertical direction inside the housing. It is characterized by. With this configuration, it is possible to provide a plasma display device that is further reduced in thickness without reducing the effective screen ratio and without reducing the power recovery efficiency.

  Further, the scanning side circuit board and the sustain side circuit board of the plasma display device of the present invention may each be equipped with a power recovery unit having a recovery capacitor, and the plurality of capacitors may include a recovery capacitor.

  In addition, the scanning circuit board and the sustain circuit board of the plasma display device of the present invention may each include a clamp portion having a decoupling capacitor, and the plurality of capacitors may include a decoupling capacitor.

  The plurality of capacitors of the plasma display device of the present invention are mounted next to the heat generating component mounted on the scanning side circuit board or the sustain side circuit board so as to form an air passage between the heat generating component. It is desirable.

  According to the present invention, it is possible to provide a plasma display device that realizes further thinning without reducing the effective screen ratio and without reducing the power recovery efficiency.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. The panel 10 is configured such that a glass front substrate 11 and a back substrate 21 are disposed to face each other and a discharge space is formed therebetween. A plurality of display electrode pairs 14 including scan electrodes 12 and sustain electrodes 13 are formed on the front substrate 11. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed in parallel on the back substrate 21, an insulating layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is provided on the insulating layer 23. Yes. A phosphor layer 25 is provided on the surface of the insulator layer 23 and on the side surfaces of the partition wall 24. The front substrate 11 and the rear substrate 21 are arranged to face each other so that the scan electrode 12 and the sustain electrode 13 and the data electrode 22 cross each other, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  The size of the front substrate 11 and the rear substrate 21 is, for example, 980 mm × 570 mm if the screen size is a panel corresponding to 42 inches, and is, for example, 1500 mm × 870 mm if the panel is 60 inches. . The thickness is 1.8 mm, for example.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In the panel 10, n scanning electrodes 12 and n sustain electrodes 13 that are long in the row direction are arranged, and m data electrodes 22 that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode 12 and sustain electrode 13 intersects with one data electrode 22, and m × n discharge cells are formed in the discharge space. The number n of the scan electrodes 12 and the sustain electrodes 13 and the number m of the data electrodes 22 are determined by the resolution of the panel 10, and n = 1080 and m = 5760, for example, if the panel has full high-definition resolution.

  As shown in FIGS. 1 and 2, scan electrode 12 and sustain electrode 13 are formed in parallel with each other, and therefore a large interelectrode capacitance is formed between scan electrode 12 and sustain electrode 13. Cp exists.

  Next, a method for driving the panel 10 will be described. In the present embodiment, a so-called subfield method is used as a method of displaying a gradation corresponding to an image signal. In the subfield method, one field period is divided into a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by controlling light emission / non-light emission of each discharge cell for each subfield. It is.

  FIG. 3 is a diagram showing drive voltage waveforms applied to each electrode of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 3 shows drive voltage waveforms for two subfields. The driving voltage waveforms in the other subfields are almost the same.

  In the initialization period of the subfield, a voltage 0 (V) is applied to the data electrode 22 and the sustain electrode 13, and a ramp waveform voltage that gradually increases from the voltage Vi1 to the voltage Vi2 is applied to the scan electrode 12. Thereafter, the voltage Ve1 is applied to the sustain electrode 13, and the ramp waveform voltage that gently decreases from the voltage Vi3 to the voltage Vi4 is applied to the scan electrode 12. Then, a weak initializing discharge occurs in each discharge cell, and wall charges necessary for the subsequent address operation are formed on each electrode. Note that as the operation in the initialization period, as shown in the initialization period of the second subfield in FIG. 3, a ramp waveform voltage that gently falls may be applied to the scan electrode 12.

  In the subsequent address period, voltage Ve <b> 2 is applied to sustain electrode 13, voltage Vc is applied to scan electrode 12, and voltage 0 (V) is applied to data electrode 22.

  Then, a scan pulse of voltage Va is applied to the scan electrode 12 in the first row where the address operation is performed, and an address pulse of voltage Vd is applied to the data electrode 22 corresponding to the discharge cell to emit light. Then, an address discharge is generated in the discharge cell to which the scan pulse and the address pulse are simultaneously applied, and an address operation for accumulating wall charges in the scan electrode 12 and the sustain electrode 13 is performed.

  The above addressing operation is repeated in all rows of discharge cells, and address discharge is selectively generated in the discharge cells to emit light to form wall charges.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrode 13. Then, a sustain pulse of voltage Vs is applied to scan electrode 12. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred and emits light. Next, voltage 0 (V) is applied to scan electrode 12 and a sustain pulse of voltage Vs is applied to sustain electrode 13. Then, in the discharge cell in which the sustain discharge has occurred, the sustain discharge occurs again to emit light. Similarly, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrode 12 and sustain electrode 13. In this way, the discharge cells that have performed the address operation in the address period are caused to emit light with a luminance corresponding to the luminance weight. Thereafter, a sustain pulse of voltage Vs is applied to scan electrode 12, voltage Ve1 is applied to sustain electrode 13, so-called wall charge erasure is performed, and the sustain period ends.

  The subsequent operation of the subfield is substantially the same as the operation of the first subfield, and thus description thereof is omitted.

  In this embodiment, the voltage value applied to each electrode is, for example, voltage Vi1 = voltage Vi3 = voltage Vs = 200 (V), voltage Vi2 = 440 (V), voltage Vi4 = −80 (V), voltage Va = −85 (V), voltage Ve1 = 150 (V), and voltage Ve2 = 155 (V). However, these voltage values are merely an example, and it is desirable to set them appropriately to optimum values according to the panel characteristics, the specifications of the plasma display device, and the like.

  FIG. 4 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and further, the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 32 converts the image data into an address pulse corresponding to each data electrode 22 and applies it to each data electrode 22.

  The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit block. The scan electrode drive circuit 33 includes an initialization waveform generation circuit 41 that generates a ramp waveform voltage in the initialization period, a scan pulse generation circuit 42 that generates a scan pulse in the write period, and a sustain pulse generation circuit that generates a sustain pulse in the sustain period 43, a drive voltage waveform is generated based on the timing signal and applied to each of the scanning electrodes 12. Sustain electrode drive circuit 34 includes sustain pulse generation circuit 45 that generates a sustain pulse during the sustain period, and generates a drive voltage waveform based on the timing signal and applies it to sustain electrode 13.

  Next, details of sustain pulse generating circuits 43 and 45 will be described. FIG. 5 is a circuit diagram of sustain pulse generating circuits 43 and 45 of plasma display apparatus 30 in the embodiment of the present invention. In FIG. 5, the interelectrode capacitance of the panel 10 is shown as “Cp”. Further, the circuit for generating the voltage Ve1 and voltage Ve2 of the initialization waveform generation circuit 41 and the scan pulse generation circuit 42 of the scan electrode drive circuit 33 and the sustain electrode drive circuit 34 is omitted.

  Sustain pulse generation circuit 43 includes power recovery unit 51 and clamp unit 53. The power recovery unit 51 includes a power recovery capacitor C51, switching elements Q51 and Q52, backflow prevention diodes D51 and D52, and power recovery inductors L51 and L52. The clamp unit 53 includes switching elements Q53 and Q54 and a decoupling capacitor C53. The power recovery unit 51 and the clamp unit 53 are connected to the scan electrode 12 which is one end of the interelectrode capacitance Cp via a scan pulse generation circuit (which is in a short circuit state during the sustain period).

  The power recovery unit 51 causes the sustain pulse to rise by causing LC resonance between the inductor L51 and the interelectrode capacitance Cp, and causes the sustain pulse to fall by causing LC resonance between the inductor L52 and the interelectrode capacitance Cp. When the sustain pulse rises, the charge stored in the power recovery capacitor C51 is transferred to the interelectrode capacitance Cp via the switching element Q51, the diode D51, and the inductor L51. When the sustain pulse falls, the charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C51 via the inductor L52, the diode D52, and the switching element Q52. In this way, the sustain pulse is applied to the scan electrode 12. Thus, since the power recovery unit 51 drives the scan electrode 12 by LC resonance without being supplied with power from the power source, the power consumption is ideally zero. The power recovery capacitor C51 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half of the voltage Vs, so as to serve as a power source for the power recovery unit 51.

  The clamp unit 53 connects the scan electrode 12 to the power source of the voltage Vs via the switching element Q53, and clamps the scan electrode 12 to the voltage Vs. Further, the scanning electrode 12 is grounded via the switching element Q54 and clamped to a voltage of 0 (V). In this way, the clamp unit 53 drives the scanning electrode 12. Therefore, the impedance at the time of voltage application by the clamp part 53 is small, and a large discharge current due to strong sustain discharge can flow stably. The decoupling capacitor C53 is provided to reduce the impedance of the power supply of the voltage Vs to suppress voltage fluctuation.

  Switching elements Q51, Q52, Q53, and Q54 can be configured using generally known elements such as MOSFETs and IGBTs.

  Sustain pulse generation circuit 45 includes power recovery capacitor C56, switching elements Q56 and Q57, backflow prevention diodes D56 and D57, power recovery inductor L56, power recovery unit 56 including inductor L57, switching element Q58, Q59 and a clamp portion 58 having a decoupling capacitor C58, and is connected to the sustain electrode 13 which is one end of the interelectrode capacitance Cp of the panel 10. The details of sustain pulse generating circuit 45 are the same as those of sustain pulse generating circuit 43 and will not be described.

  Next, the operation of sustain pulse generating circuits 43 and 45 will be described. FIG. 6 is a timing chart showing the operation of sustain pulse generating circuits 43 and 45 of plasma display apparatus 30 in the embodiment of the present invention. One period Tw of the sustain pulse applied to the scan electrode 12 is divided into four periods indicated by T11 to T14, and each period will be described. In the following description, the operation for turning on the switching element is expressed as ON, and the operation for blocking is described as OFF.

  First, the operation of applying the sustain pulse to the scan electrode 12 will be described in detail.

(Period T11)
Switching element Q51 is turned ON at time t11. Then, current starts to flow from the power recovery capacitor C51 to the scan electrode 12 through the switching element Q51, the diode D51, and the inductor L51, and the voltage of the scan electrode 12 starts to rise. At this time, since the inductor L51 and the interelectrode capacitance Cp resonate, the voltage of the scan electrode 12 rises to almost twice the voltage of the capacitor C51, that is, near the voltage Vs after the time of ½ of the resonance period has elapsed.

(Period T12)
The switching element Q53 is turned ON at time t12 when the voltage of the scan electrode 12 rises to near the voltage Vs. Then, the scanning electrode 12 is connected to the power source of the voltage Vs through the switching element Q53, and is clamped to the voltage Vs. When the scan electrode 12 is clamped to the voltage Vs, the voltage difference between the scan electrode 12 and the sustain electrode 13 exceeds the discharge start voltage in the discharge cell in which the address discharge has occurred, and a sustain discharge occurs. Switching element Q51 is turned off after time t12, and switching element Q53 is turned off after the sustain discharge occurs.

(Period T13)
At time t13, switching element Q52 is turned on. Then, current starts to flow from the scan electrode 12 to the capacitor C51 through the inductor L52, the diode D52, and the switching element Q52, and the voltage of the scan electrode 12 starts to decrease. At this time, since the inductor L52 and the interelectrode capacitance Cp resonate, the voltage of the scan electrode 12 drops to the vicinity of the voltage 0 (V) after a half time of the resonance period has elapsed.

(Period T14)
The switching element Q54 is turned on at time t14 when the voltage of the scan electrode 12 drops to near voltage 0 (V). Then, since the scan electrode 12 is grounded through the switching element Q54, the voltage of the scan electrode 12 is clamped to 0 (V). Switching element Q52 is turned off after time t14, and switching element Q54 is turned off until a sustain pulse is next applied to scan electrode 12.

  By repeating the operations in the above-described periods T11 to T14, sustain pulse generating circuit 43 applies a necessary number of sustain pulses to scan electrode 12.

  Similarly, in the operation of applying the sustain pulse to the sustain electrode 13, one period Tw of the sustain pulse applied to the sustain electrode 13 is divided into four periods indicated by T21 to T24, and each period will be described.

(Period T21)
At time t21, switching element Q56 is turned on. Then, the inductor L56 and the interelectrode capacitance Cp resonate, and the voltage of the sustain electrode 13 rises to the vicinity of the voltage Vs after the lapse of half the resonance period.

(Period T22)
Switching element Q58 is turned on at time t22 when the voltage of sustain electrode 13 rises to near voltage Vs. Then, sustain electrode 13 is clamped at voltage Vs, and a sustain discharge is generated in the discharge cell that has caused the address discharge. Then, the switching elements Q56 and Q58 are turned off.

(Period T23)
Switching element Q57 is turned ON at time t23. Then, the inductor L57 and the interelectrode capacitance Cp resonate, and the voltage of the sustain electrode 13 drops to near the voltage 0 (V) after ½ time of the resonance period has elapsed.

(Period T24)
Switching element Q59 is turned ON at time t24 when the voltage of sustain electrode 13 drops to near voltage 0 (V). Then, sustain electrode 13 is clamped at a voltage of 0 (V). Then, the switching elements Q57 and Q59 are turned off.

  By repeating the operations in the above-described periods T21 to T24, sustain pulse generating circuit 45 applies the necessary number of sustain pulses to sustain electrode 13.

  Thus, sustain pulse generation circuits 43 and 45 resonate between interelectrode capacitance Cp and inductors L51, L52, L56, and L57 to charge and discharge interelectrode capacitance Cp, thereby applying power for applying a sustain pulse. Is recovered. Therefore, in order to recover power efficiently, the inductances of the inductors L51, L52, L56, and L57 are set accurately, and the current path of the power recovery circuit, particularly the resistance values of the inductors L51, L52, L56, and L57 are set. It is important to reduce the heat loss of the inductors L51, L52, L56, and L57. In the present embodiment, in order to suppress the resistance values of these inductors L51, L52, L56, and L57 and to suppress fluctuations in inductance, a method for mounting circuit components of sustain pulse generating circuits 43 and 45 is devised.

  FIG. 7 is an exploded perspective view of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, a chassis 61 that holds the panel 10 on the front surface, a heat conductive sheet 62 that transfers heat generated in the panel 10 to the chassis 61 and bonds the panel 10 and the chassis 61 to each other. A circuit board group 64 comprising a plurality of circuit boards mounted on the rear side of the chassis 61 and mounted with various drive circuits for driving the panel 10, and a front frame 65 and a back cover serving as a housing for housing them 66. The front frame 65 may be provided with a transparent protective plate for protecting the panel 10, but in the present embodiment, in order to reduce the thickness of the plasma display device 30, a protective sheet is used instead of the protective plate. Is directly attached to the surface of the panel 10.

  Thus, in the present embodiment, since the circuit board group 64 is attached to the back side of the chassis 61, the effective screen ratio of the plasma display device 30 does not decrease.

  FIG. 8 is a schematic diagram showing a cross section of a side surface of plasma display device 30 in the exemplary embodiment of the present invention. 8 shows the front frame 65, the panel 10, the chassis 61, the circuit board group 64, and the back cover 66.

  In the present embodiment, the panel 10, the heat conductive sheet 62, the chassis 61, and the back cover 66 have thicknesses of 3.6 mm, 1.2 mm, 1.5 mm, and 1.0 mm, respectively. The height of the components mounted on the circuit board group 64 after mounting is limited to 11 mm or less, the spatial distance between the circuit board group 64 and the chassis 61, and the components mounted on the circuit board group 64 and the back cover. The total of these thicknesses including the spatial distance with 66 is 25 mm or less.

  FIG. 9 is a diagram showing the arrangement of the circuit board group 64 of the plasma display device 30 according to the embodiment of the present invention. The plasma display device 30 on which the panel 10 having a screen size equivalent to 50 inches is mounted, and the back cover 66 is installed. It is the figure seen from the back side after removing. In particular, FIG. 9 shows a scanning-side circuit board (hereinafter simply referred to as “circuit board”) 100 on which the sustain pulse generating circuit 43 of the scan electrode driving circuit 33 is mounted, and the sustain pulse generating circuit 45 of the sustain electrode driving circuit 34. A maintenance-side circuit board (hereinafter simply abbreviated as “circuit board”) 200 is attached with a reference numeral.

  FIG. 10 is a detailed view of the circuit board 100 of the plasma display device 30 according to the embodiment of the present invention. FIG. 10A shows a layout of main components mounted on the circuit board 100. FIG. (B) is a figure which shows typically the ventilation path formed on the circuit board 100, and its air flow, and FIG.10 (c) is AA sectional drawing of FIG.10 (b).

  In the present embodiment, inductor L51 of sustain pulse generating circuit 43 is configured by connecting six coils 101 to 106 using ferrite cores in parallel, and inductor L52 is six coils 111 to 116 using ferrite cores. Are connected in parallel. On the circuit board 100, six coils 101 to 106 are mounted so as to be arranged in a line in the vertical direction inside the casing, and six coils 111 to 116 are arranged in a line in the vertical direction inside the casing. Has been implemented.

  Switching elements Q51 and Q52 and diodes D51 and D52 of the power recovery unit 51 are mounted on the right side of the coils 101 to 106 and the coils 111 to 116, and the clamp unit 53 is positioned on the left side of the coils 101 to 106 and the coils 111 to 116. Switching elements Q53 and Q54 are mounted.

  In the present embodiment, each of switching elements Q51, Q52, Q53, and Q54 is configured by connecting a plurality of switching elements in parallel, and each of diodes D51 and D52 is also connected by connecting a plurality of diodes in parallel. It is configured. A common heat sink 141 is attached to the switching element Q51 and the diode D51, and a common heat sink 142 is attached to the switching element Q52 and the diode D52. Further, a heat radiating plate 143 and a heat radiating plate 144 are attached to the switching element Q53 and the switching element Q54.

  With this configuration, as shown in FIGS. 10B and 10C, an air passage 171 is formed between the coils 101 to 106 and the heat radiating plate 143, and between the coils 111 to 116 and the heat radiating plate 143. A ventilation path 172 is formed. Further, a ventilation path 173 is formed between the coils 101 to 106 and the heat radiating plate 141, and a ventilation path 174 is formed between the coils 111 to 116 and the heat radiating plate 142.

  The ventilation path here is surrounded by a circuit board, a tall circuit component arranged in a row in the vertical direction on the circuit board, and a member arranged in parallel to the circuit board, and The lower part has an opening through which air flows, and the upper part has a space with an opening through which air is discharged. In the present embodiment, the member arranged in parallel with the circuit board is the back cover 66.

  In the present embodiment, the power recovery capacitor C51 is configured by connecting capacitors 151 to 158 such as eight film capacitors in parallel, and the decoupling capacitor C53 of the power source of the voltage Vs is eight film capacitors. These capacitors 161 to 168 are connected in parallel.

  Here, the four capacitors 151 to 154 are mounted so as to form a ventilation path 175 between the switching element Q51, which is a heat generating component, the diode D51, and the heat dissipation plate 141. Specifically, the circuit board 100 is arranged so that the four capacitors 151 to 154 are arranged in the vertical direction inside the housing, and the longest sides of the capacitors 151 to 154 are arranged in the vertical direction inside the housing. Implemented above. The lengths of the four capacitors 151 to 154 in the vertical direction (the length from the upper end of the capacitor 151 to the lower end of the capacitor 154 in FIG. 10A) are longer than the vertical length of the heat sink 141. . In this way, the ventilation path 175 is formed between the capacitors 151 to 154 and the heat radiating plate 141. Capacitors 161 to 164 are arranged adjacent to the capacitors 151 to 154. This makes it difficult for air to leak from the gaps between the capacitors 151-154.

  Similarly, the four capacitors 155 to 158 are mounted so as to form a ventilation path 176 between the switching element Q52, which is a heat generating component, the diode D52, and the heat radiating plate 142 thereof. Specifically, the circuit board 100 is arranged such that the four capacitors 155 to 158 are arranged in the vertical direction inside the casing, and the longest sides of the capacitors 155 to 158 are in the vertical direction inside the casing. Implemented above. The vertical lengths of the four capacitors 155 to 158 (the length from the upper end of the capacitor 155 to the lower end of the capacitor 158 in FIG. 10A) are equal to or longer than the vertical length of the heat sink 142. . In this way, the ventilation path 176 is formed between the capacitors 155 to 158 and the heat radiating plate 142. Capacitors 165 to 168 are arranged adjacent to the capacitors 155 to 158. This makes it difficult for air to leak from the gap between the capacitors 155 to 158.

  Similarly, circuit components are mounted on the circuit board 200. FIG. 11 is a detailed view of the circuit board 200 of the plasma display device 30 in accordance with the exemplary embodiment of the present invention. FIG. 11A shows details of components mounted on the circuit board 200, and FIG. FIG. 4B is a diagram schematically illustrating the ventilation path formed on the circuit board 200 and the air flow thereof.

  In the present embodiment, inductor L56 of sustain pulse generating circuit 45 is also configured by connecting six coils 201-206 using a ferrite core in parallel, and inductor L57 is composed of six coils 211-216 using a ferrite core. Are connected in parallel. On the circuit board 200, six coils 201 to 206 are mounted so as to be arranged in one row in the vertical direction inside the housing, and six coils 211 to 216 are arranged in one row in the vertical direction inside the housing. Has been implemented.

  The switching elements Q56 and Q57 of the power recovery unit 56 and the diodes D56 and D57 are mounted on the left side of the coils 201 to 206 and the coils 211 to 216, and the clamp unit 58 is mounted on the right side of the coils 201 to 206 and the coils 211 to 216. Switching elements Q58 and Q59 are mounted.

  Each of these switching elements Q56, Q57, Q58, and Q59 is also configured by connecting a plurality of switching elements in parallel, and each of the diodes D56 and D57 is also configured by connecting a plurality of diodes in parallel. A common heat sink 241 is attached to the switching element Q56 and the diode D56, and a common heat sink 242 is attached to the switching element Q57 and the diode D57. Further, a heat dissipation plate 243 and a heat dissipation plate 244 are attached to the switching element Q58 and the switching element Q59.

  With this configuration, an air passage 271 is formed between the coils 201 to 206 and the heat radiating plate 243, and an air passage 272 is formed between the coils 211 to 216 and the heat radiating plate 244. In addition, a ventilation path 273 is formed between the coils 201 to 206 and the heat radiating plate 241, and a ventilation path 274 is formed between the coils 211 to 216 and the heat radiating plate 242.

  Further, the capacitor C56 for power recovery is realized by connecting eight film capacitors 251 to 258 in parallel, and the decoupling capacitor C58 of the power source of the voltage Vs is connected to eight film capacitors 261 to 268 in parallel. And realized.

  Here, the four capacitors 251 to 254 are mounted so as to form a ventilation path 275 between the switching element Q56, which is a heat generating component, the diode D56, and the heat dissipation plate 241. Specifically, the circuit board 200 is arranged such that the four capacitors 251 to 254 are arranged in the vertical direction inside the casing, and the longest sides of the capacitors 251 to 254 are in the vertical direction inside the casing. Implemented above. The vertical lengths of the four capacitors 251 to 254 (the length from the upper end of the capacitor 251 to the lower end of the capacitor 254 in FIG. 11A) are equal to or longer than the vertical length of the heat sink 241. . In this way, the ventilation path 275 is formed between the capacitors 251 to 254 and the heat radiating plate 241. Capacitors 261 to 264 are arranged adjacent to the capacitors 251 to 254. This makes it difficult for air to leak from the gap between the capacitors 251 to 254.

  Similarly, the four capacitors 255 to 258 are mounted so as to form a ventilation path 276 between the switching element Q57, which is a heat generating component, the diode D57, and the heat radiating plate 242 thereof. Specifically, the circuit board 200 is arranged so that the four capacitors 255 to 258 are arranged in the vertical direction inside the casing, and the longest sides of the capacitors 255 to 258 are in the vertical direction inside the casing. Implemented above. The vertical lengths of the four capacitors 255 to 258 (the length from the upper end of the capacitor 255 to the lower end of the capacitor 258 in FIG. 11A) are equal to or longer than the vertical length of the heat radiating plate 242. . In this way, the ventilation path 276 is formed between the capacitors 255 to 258 and the heat radiating plate 242. Capacitors 265 to 268 are disposed adjacent to the capacitors 255 to 258. This makes it difficult for air to leak from the gap between the capacitors 255 to 258.

  As described above, in the present embodiment, each of the inductors L51, L52, L56, and L57 is configured by connecting a plurality of coils using a ferrite core in parallel. The coil used in this embodiment is made by winding a copper wire with low resistance around a ferrite core, but the resistance value of the copper wire is not “0” but has a finite value. Generates heat and the coil temperature rises.

  When the coil temperature rises, the resistance value of the copper wire increases, so that power loss increases. A coil using a ferrite core is excellent in that it can be miniaturized. However, since the ferrite itself has temperature characteristics, when the coil temperature rises, power loss further increases and inductance also changes. Therefore, in order to suppress the power loss of the inductor for power recovery and to suppress the fluctuation of the inductance, it is important to suppress the temperature rise of the coil constituting the inductor.

  In the present embodiment, ventilation paths 171 and 173 are formed so as to surround the coils 101 to 106, and ventilation paths 172 and 174 are formed so as to surround the coils 111 to 116. For this reason, air flows smoothly in a laminar flow from below to above through the air passages 171 to 174 formed on both sides of the coils 101 to 106 and 111 to 116. It can be cooled effectively. Further, ventilation paths 173 to 176 are formed so as to surround the switching elements Q51 and Q52, the diodes D51 and D52, and the heat dissipation plates 141 and 142, which are current paths of the power recovery unit 51 and are heat generating components. Therefore, since the airflow paths 173 to 176 formed on both sides of the heat sinks 141 and 142 flow smoothly and laminarly from below to above, the heat sinks 141 and 142 can be effectively cooled, and the coil Thermal radiation to 101 to 106 and 111 to 116 can be suppressed.

  Similarly, ventilation paths 271 and 273 are formed so as to surround the coils 201 to 206, and ventilation paths 272 and 274 are formed so as to surround the coils 211 to 216. For this reason, air flows smoothly in a laminar flow from the lower side to the upper side in the ventilation paths 271 to 274 formed on both sides of the coils 201 to 206 and 211 to 216. Therefore, the coils 201 to 206, 211 to 216 are connected to each other. It can be cooled effectively. In addition, ventilation paths 273 to 276 are formed so as to surround the switching elements Q56 and Q57, the diodes D56 and D57, and the heat radiation plates 241 and 242 which are current paths of the power recovery unit 56 and are heat generating components. For this reason, air flows smoothly through the ventilation paths 273 to 276 formed on both sides of the heat sinks 241 and 242 from below to above, so that the heat sinks 241 and 242 can be effectively cooled. The heat radiation to the coils 201 to 206 and 211 to 216 can be suppressed.

  Thus, in this embodiment, since the temperature rise of the inductor for power recovery can be suppressed, the increase in resistance of these inductors and the change in inductance can be suppressed, and the plasma can be reduced without reducing the power recovery efficiency. Further thinning of the display device can be realized.

  In the present embodiment, circuit parts such as capacitors are arranged in rows in the vertical direction to form a ventilation path. Capacitors having a high withstand voltage and a large capacity tend to be large in volume, and in particular, a capacitor for a power supply line and a capacitor for a recovery circuit have a high withstand voltage and a large capacity, and therefore the volume is large. In the present embodiment, these capacitors are constituted by parallel connection of a large number of capacitors, and the large number of capacitors are arranged side by side in the vertical direction to form a ventilation path.

  In the present embodiment, as the decoupling capacitors C53 and C58 having the voltage Vs, eight 120 μF (withstand voltage of 220 V) electrolytic capacitors and eight 1.5 μF film capacitors are connected in parallel. . The recovery capacitors C51 and C56 are each configured by connecting eight 1.5 μF film capacitors in parallel. These film capacitors are 20 mm long, 10 mm wide and 11 mm high. These film capacitors are arranged in rows in the vertical direction and mounted on the circuit board so as to form a part of the wall of the ventilation path.

  It is important not to mount tall circuit components below and above each of the ventilation paths 171 to 176 and 271 to 276 so that air easily flows in. Further, in the present embodiment, ventilation holes are provided in the back cover 66 at positions corresponding to the lower and upper sides of the ventilation paths 171 to 176 and 271 to 276. FIG. 12 is a view showing the ventilation holes of the back cover 66 of the plasma display device 30 according to the embodiment of the present invention, and is a view of the plasma display device 30 as seen from the back side. In FIG. 12, circuit boards 100 and 200 are indicated by broken lines. Ventilation holes 191 are provided in the back cover 66 at positions corresponding to the lower sides of the ventilation paths 172, 174, 176, and correspond to the upper side of the ventilation paths 172, 174, 176 and the lower side of the ventilation paths 171, 173, 175. A ventilation hole 192 is provided in the back cover 66 at a position, and a ventilation hole 193 is provided in the back cover 66 at a position corresponding to the upper side of the ventilation paths 171, 173, and 175. Further, ventilation holes 291 are provided in the back cover 66 at positions corresponding to the lower sides of the ventilation paths 272, 274, 276 and above the ventilation paths 272, 274, 276 and below the ventilation paths 271, 273, 275. Ventilation holes 292 are provided in the back cover 66 at corresponding positions, and ventilation holes 293 are provided in the back cover 66 at positions corresponding to above the ventilation paths 271, 273, and 275.

  Thus, by providing ventilation holes in the back cover 66 corresponding to the lower and upper positions of each ventilation path, air can flow smoothly through each ventilation path, and the coils 101-106, 111-116. , 201 to 206, 211 to 216 can be effectively suppressed.

  In addition, each specific numerical value used in this Embodiment is only an example, and is not limited to these numerical values at all. These numerical values are desirably set optimally according to the characteristics of the panel and the specifications of the plasma display device.

  The present invention can realize further reduction in thickness without reducing the effective screen ratio and without reducing the power recovery efficiency, and is useful as a plasma display device.

The exploded perspective view of the panel used for the plasma display apparatus in an embodiment of the invention Panel arrangement of panels used in the plasma display device The figure which shows the drive voltage waveform applied to each electrode of the panel used for the plasma display apparatus Circuit block diagram of the plasma display device Circuit diagram of sustain pulse generation circuit of the plasma display device Timing chart showing operation of sustain pulse generating circuit of same plasma display device Exploded perspective view of the plasma display device Schematic showing the cross section of the side of the plasma display device The figure which shows arrangement | positioning of the circuit board group of the plasma display apparatus Detailed view of the circuit board on the scanning side of the plasma display device Detailed view of the maintenance-side circuit board of the plasma display device The figure which shows the ventilation hole of the back cover of the plasma display apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 21 Back substrate 22 Data electrode 30 Plasma display apparatus 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 43, 45 Sustain pulse generation circuit 51, 56 Power recovery part 53, 58 Clamping part 61 Chassis 64 Circuit board group 65 Front frame 66 Back cover 100,200 Circuit board 101-106, 111-116, 201-206, 211-216 Coil 151-158, 161-168, 251-258, 261 268 Capacitors 171 to 176, 271 to 276 Ventilation paths 191 to 193, 291 to 293 Ventilation holes

Claims (4)

A plasma display panel having a plurality of discharge cells each having a scan electrode and a sustain electrode, a scan-side circuit board having a sustain pulse generating circuit for generating a sustain pulse to be applied to the scan electrode, and a sustain to be applied to the sustain electrode A plasma display device having a sustain side circuit board equipped with a sustain pulse generating circuit for generating a pulse, and having a casing inside,
A plurality of capacitors are mounted on each of the scanning side circuit board and the maintenance side circuit board,
The plurality of capacitors are mounted so that they are arranged in a vertical direction inside the casing, and each longest side of the plurality of capacitors is mounted in a vertical direction inside the casing. Plasma display device. The scanning side circuit board and the sustain side circuit board are each equipped with a power recovery unit having a recovery capacitor,
The plasma display apparatus according to claim 1, wherein the plurality of capacitors include the recovery capacitor. The scanning side circuit board and the sustaining side circuit board are each equipped with a clamp portion having a decoupling capacitor,
The plasma display apparatus of claim 1, wherein the plurality of capacitors include the decoupling capacitor. The plurality of capacitors are mounted so as to form an air passage between the heat generating component and the heat generating component mounted on the scanning circuit board or the sustain circuit board. The plasma display device according to claim 1.

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