JP2007194163A - Plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel which suppresses cross talk and ensures high quality image display. <P>SOLUTION: In this plasma display panel 14, barrier ribs 12 are set between a front panel 1 with display electrodes 6 consisting of scanning electrodes 4 and sustaining electrodes 5, and a rear panel 2 with data electrodes 10 crossing the display electrodes 6, both the panels are arranged oppositely, and discharge spaces separated by the barrier ribs 12 are formed. Widths of the barrier ribs 12 in proximity locations including the scanning electrodes 4 are thicker than those in other locations. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma display panel known as a display device.

  Plasma display panels can be broadly divided into AC and DC types, and there are two types of discharge types: surface discharge type and counter discharge type. From the viewpoint of high definition, large screen, and ease of manufacturing. At present, the AC type and the surface discharge type are the mainstream.

  The AC type surface discharge type plasma display panel has a structure in which at least a pair of substrates transparent at least on the front side are arranged to face each other so that a discharge space is formed between the substrates, and a partition wall for dividing the discharge space into a plurality of partitions A plurality of discharges by arranging a group of electrodes on the substrate so that a discharge is generated in a discharge space partitioned by the barrier ribs, and providing phosphors that emit red, green, and blue light emitted by the discharge. This cell is composed of cells, and the phosphor is excited by vacuum ultraviolet light with a short wavelength generated by discharge, and red, green, and blue discharge cells emit red, green, and blue visible light, respectively, to perform color display. ing.

  Such a plasma display panel can display at a higher speed than a liquid crystal panel, has a wide viewing angle, is easy to increase in size, and is a self-luminous type because of its high display quality. Recently, the flat panel display has attracted particular attention, and is used as a display device in a place where many people gather or as a display device for enjoying a large screen image at home.

The plasma display panel as described above is held on the front side of a chassis member made of metal such as aluminum, and a circuit board constituting a drive circuit for causing the panel to emit light is disposed on the back side of the chassis member. (See Patent Document 1).
JP 2003-131580 A

  In the PDP having the above-described structure, crosstalk between adjacent discharge cells, which is considered to be caused by poor partitioning of the discharge space by the barrier ribs, has an adverse effect on the displayed image. There was a case where the problem of ending up occurred.

  The present invention has been made in view of such a current situation, and an object thereof is to realize a plasma display panel capable of displaying a high-quality image in which occurrence of crosstalk is suppressed.

  In order to achieve the above object, a plasma display panel according to the present invention includes a front plate on which display electrodes including scan electrodes and sustain electrodes are arranged, and a back plate on which data electrodes are arranged so as to intersect the display electrodes. The plasma display panel is arranged to face each other so that a discharge space partitioned by the partition wall is formed by sandwiching the partition wall therebetween, and the width of the partition wall with respect to the vicinity including the scanning electrode is In addition, it is characterized in that it is thicker than the width at other locations.

  According to the present invention, it is possible to realize a PDP capable of displaying a high-quality image in which occurrence of crosstalk is suppressed.

  That is, the invention according to claim 1 of the present invention includes a front plate on which display electrodes composed of scan electrodes and sustain electrodes are arranged, and a back plate on which data electrodes are arranged so as to intersect the display electrodes. The plasma display panel is disposed so as to form a discharge space partitioned by the partition wall by sandwiching the partition wall therebetween, and the width of the partition wall in the vicinity of the vicinity including the scanning electrode is other than The plasma display panel is characterized in that it is thicker than the width at the point.

  Hereinafter, a plasma display panel according to an embodiment of the present invention will be described with reference to the drawings. However, the embodiment of the present invention is not limited thereto.

  FIG. 1 is a perspective sectional view showing a schematic configuration of a plasma display panel according to an embodiment of the present invention. As shown in FIG. 1, the plasma display panel is configured by disposing a front plate 1 and a back plate 2 so as to form a discharge space therebetween. The front plate 1 includes, for example, a front substrate 3 made of glass, a display electrode 6 formed by pairing a scan electrode 4 and a sustain electrode 5 formed on the front substrate 3 in parallel with each other, and the display electrode 6. And a protective layer 8 formed on the dielectric layer 7.

  The back plate 2 includes a back substrate 9, a data electrode 10 formed on the back substrate 9, an insulator layer 11 covering the data electrode 10, and a vertical partition provided on the insulator layer 11. 12a and a partition wall 12 in the form of a cross formed by a lateral partition wall 12b, and a phosphor layer (not shown) provided on the surface of the insulator layer 11 and the side surface of the partition wall 12. The vertical partition 12 a has a thick and wide portion 13.

  The front plate 1 and the back plate 2 are arranged to face each other so that the display electrode 6 and the data electrode 10 intersect each other. In the discharge space formed between them, for example, a mixture of neon and xenon is used as a discharge gas. Gas is sealed as a discharge gas to constitute a plasma display panel 14. In addition, the structure of the plasma display panel described above is an example, and the structure is not limited thereto. For example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the plasma display panel. N scan electrodes SC1 to SCn (scan electrode 4 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 5 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 10 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram showing a schematic configuration of a plasma display device for displaying an image on the plasma display panel 14. The plasma display device includes a plasma display panel 14, an image signal processing circuit 15, a data electrode drive circuit 16, a scan electrode drive circuit 17, a sustain electrode drive circuit 18, a timing generation circuit 19, and a power supply circuit (not shown). .

  The image signal processing circuit 15 converts the image signal sig into image data for each subfield. The data electrode drive circuit 16 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 19 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each drive circuit block. Scan electrode drive circuit 17 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 18 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, the scan electrode drive circuit 17 and the sustain electrode drive circuit 18 include a sustain pulse generator 20.

  Next, a driving voltage waveform and its operation for driving the plasma display panel will be described with reference to FIG. FIG. 4 is a diagram showing a driving voltage waveform applied to each electrode. One field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period of the first subfield, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SC1 to SCn, and positive walls on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to 1) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive write pulse voltage Vd (V) is applied to m). At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va) (V). And the discharge start voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm and the scan electrode SC1 to which the address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as a first voltage, and ground potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn as a second voltage. Apply. In the discharge cell in which the address discharge has occurred at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and the phosphor layer emits light due to the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. At this time, a positive wall voltage is also accumulated on the data electrode Dk.

  In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi, Negative wall voltage is accumulated on sustain electrode SUi, and positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, by applying sustain pulses of the number corresponding to the luminance weight alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period. Done. Thus, the maintenance operation in the maintenance period is completed.

  The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.

  FIG. 5 shows an example of the overall configuration of a plasma display device incorporating a plasma display panel according to an embodiment of the present invention, and FIG. 6 shows an example of the arrangement of drive circuit blocks as viewed from the back side. Is.

  In the figure, 21 is a chassis member as a holding plate that also serves as a heat sink made of metal such as aluminum. On the front side of the chassis member 21, a plasma display panel 14 is disposed between the chassis member 21 and a heat dissipation sheet (see FIG. 5 is held by bonding with an adhesive or the like with a not shown) interposed therebetween. Further, as shown in FIG. 6, a plurality of drive circuit blocks for driving the plasma display panel 14 is arranged on the rear side of the chassis member 21, thereby constituting a module.

  Here, the heat-dissipating sheet is used for adhering and holding the plasma display panel 14 on the front surface side of the chassis member 21, efficiently transferring the heat generated in the plasma display panel 14 to the chassis member 21, and performing heat dissipation. Yes, the thickness is about 1 mm to 2 mm. As this heat radiating sheet, an insulating heat radiating sheet in which a synthetic resin material such as acrylic, urethane, silicon resin, or rubber contains a filler that enhances thermal conductivity, a graphite sheet, a metal sheet, or the like can be used. In addition, the heat radiation sheet itself has an adhesive force, and the plasma display panel 14 is bonded to the chassis member 21 with only the heat radiation sheet. The heat radiation sheet has no adhesive force, and another double-sided adhesive tape is used. A configuration in which the plasma display panel 14 is bonded to the chassis member 21 can be used.

  Further, flexible wiring boards 22 as display electrode wiring members connected to the electrode lead portions of the scan electrodes 4 and the sustain electrodes 5 are provided on both side edges of the plasma display panel 14, and pass through the outer periphery of the chassis member 21. It is routed to the back side and connected to the drive circuit block 23 of the scan electrode drive circuit 17 and the drive circuit block 24 of the sustain electrode drive circuit 18 via connectors.

  On the other hand, a plurality of flexible wiring boards 25 as data electrode wiring members connected to the electrode lead-out portions of the data electrodes 10 are provided on the lower and upper edges of the plasma display panel 14, and the flexible wiring boards 25 are Are electrically connected to each of the plurality of data drivers 26 of the data electrode driving circuit 16 and routed to the back side through the outer peripheral portion of the chassis member 21 and arranged at the lower and upper positions on the back side of the chassis member 21. The data electrode drive circuit 16 is electrically connected to the drive circuit block 27.

  The control circuit block 28 displays image data on the basis of a video signal sent from an input signal circuit block 29 having an input terminal portion to which a connection cable for connecting to an external device such as a television tuner is detachably connected. 14 is converted into an image data signal corresponding to the number of pixels 14 and supplied to the drive circuit block 27 of the data electrode drive circuit 16, and a discharge control timing signal is generated to drive and maintain the drive circuit block 23 of the scan electrode drive circuit 17. This is supplied to the drive circuit block 24 of the electrode drive circuit 18 and performs display drive control such as gradation control, and is arranged at substantially the center of the chassis member 21.

  The power supply block 30 supplies a voltage to each of the circuit blocks. Like the control circuit block 28, the power supply block 30 is disposed at a substantially central portion of the chassis member 21, and is commercialized through a connector to which a power supply cable (not shown) is attached. A power supply voltage is supplied. These drive circuit blocks 23, 24, 27, control circuit block 28, input signal circuit block 29, and power supply block 30 are fixed to the boss portion provided on the back side of the chassis member 21 with screws or the like.

  Further, a cooling fan 31 is disposed in the vicinity of the drive circuit blocks 23 and 24 while being held at an angle 32 so that the drive circuit blocks 23 and 24 are cooled by the wind sent from the cooling fan 31. It is configured. Further, the drive circuit block 27 of the data electrode drive circuit 16 disposed at the upper position is cooled at the upper position of the chassis member 21, and on the rear side of the chassis member 21, the entire apparatus is moved from the lower portion toward the upper portion. Three cooling fans 33 are arranged to cool the inside of the apparatus by causing an air flow.

  Further, reinforcing angles 34 and 35 are fixed to the chassis member 21 in the horizontal direction and the vertical direction, and the angle 34 arranged in the horizontal direction is a stand for holding the apparatus in an upright state. The pole 36 is fixed with screws or the like.

  The module having the above structure is provided in a housing having a front protective cover 37 disposed on the front side of the plasma display panel 14 and a metal back cover 38 disposed on the rear side of the chassis member 21. Thus, the plasma display apparatus is completed. Here, the front protective cover 37 is attached to the front frame 39 made of resin or metal having an opening 39a that exposes the image display area on the front side of the plasma display panel 14, and the opening 39a of the front frame 39. And a protective plate 40 made of glass or the like provided with an unnecessary radiation suppressing film for suppressing unnecessary radiation of an optical filter or electromagnetic wave, and the protective plate 40 includes a peripheral portion of the protective plate 40. The front frame 39 is attached to the front frame 39 by being sandwiched between the peripheral edge of the opening 39a and a protective plate pressing metal fitting (not shown). Further, the back cover 38 is provided with a plurality of vent holes (not shown) for releasing heat generated by the module to the outside.

  In FIG. 5, reference numeral 41 denotes a screw for attaching the back cover 38 to the chassis member 21, and 42 denotes a gripping part attached to the back cover 38 with a screw or the like.

  Next, features of the plasma display panel according to the present embodiment will be described in detail.

  FIG. 7 is a plan view showing a schematic configuration for explaining the positional relationship between the partition walls 12 and the display electrodes 6 of the plasma display panel according to the embodiment of the present invention. The scanning electrode 4 and the sustaining electrode 5 form a display electrode 6 pair, and a black stripe 71 serving as a light shielding portion is formed between the adjacent display electrode 6 pair. Scan electrode 4 and sustain electrode 5 are each composed of transparent electrodes 4a and 5a and bus electrodes 4b and 5b made of Cr / Cu / Cr or Ag electrically connected to transparent electrodes 4a and 5a, respectively. ing. The bus electrodes 4b and 5b also have a function of shielding light in the same manner as the black stripe 71.

  Further, the partition wall 12 is composed of a vertical partition wall 12a and a horizontal partition wall 12b, and the width of the vertical partition wall 12a with respect to the vicinity including the scanning electrode 4 is larger than the width at other positions. The structure has a thick width portion 13 so as to be thick.

  Here, in the plasma display panel, control of crosstalk with discharge cells adjacent in the horizontal direction is very important for improving image quality. That is, the discharge cells that are adjacent in the horizontal direction are discharge cells that emit light in different colors of red (R), green (G), and blue (B). In the case where only B is lit and G is not lit, the charge stored in the G cell changes due to crosstalk (movement of charges or electrons or impurities) from the lit R and B. Therefore, when the next G is turned on, there may be a problem that the lighting state becomes different from a desired state. Such a problem becomes more remarkable when the discharge gas of the plasma display panel is set to high Xe.

  Here, conventionally, the top surface of the partition wall on the rear substrate side and the protective layer surface on the front substrate side are formed as flat as possible, so that they are in close contact with each other, thereby partitioning the discharge space with high accuracy. Trying to suppress crosstalk between discharge cells.

  However, in the conventional configuration as described above, as shown in FIG. 8, for example, when the foreign material 72 is sandwiched therebetween, the top surface of the partition 12a and the protective layer 8 in contact with the top of the partition 12a. As a result, there arises a problem that a gap 73 is generated between the two and a crosstalk occurs.

  On the other hand, the present invention is based on the following knowledge obtained by a study on the occurrence of crosstalk performed by the present inventor. In other words, the above-described crosstalk problem becomes prominent when a gap is generated at a location with respect to the vicinity including the scanning electrode, and conversely, there is a clearance at a location corresponding to the vicinity including the sustain electrode. Even so, it has a very small effect on the occurrence of crosstalk. A possible reason for this is that the crosstalk generation factor has the most influence on the address period in which discharge (address discharge) occurs between the scan electrode 4 and the data electrode 10.

  Therefore, in the plasma display panel according to the embodiment of the present invention, the structure having the wide portion 13 in which the width of the partition with respect to the vicinity including the scanning electrode is thicker than the width in the other portions. It has become. With such a structure, a gap exists in the vicinity including the scanning electrode 4, and charges, electrons, impurities, or the like try to move (crosstalk) to the adjacent discharge cells through the gap through the gap. However, as the width of the partition wall is increased, charges, electrons, or impurities are trapped in the protection layer of the partition wall and / or the front plate before passing through, and the movement is greatly suppressed. The occurrence of crosstalk can be greatly suppressed.

  Here, in the above description, the width of the partition wall slightly deviated from the scan electrode 4 may be increased as expressed as a portion with respect to the vicinity including the scan electrode 4, but the effect is surely obtained. Obtained the result that it is desirable to increase the width of the portion of the partition wall 12a corresponding to the vicinity of the bus electrode 4b of the scanning electrode 4. This is considered due to the occurrence of address discharge between the bus electrode 4b and the data electrode 10.

  In the above description, the partition wall 12 has been shown as an example of a grid-shaped partition wall 12 having the same height in the vertical partition wall 12a and the horizontal partition wall 12b. However, the present invention is not limited to this. Even if it is a grid-shaped barrier rib having a different height in the horizontal direction, or even in a stripe-shaped barrier rib only in the vertical direction, the barrier partitioning the discharge cells adjacent in the horizontal direction, as described above, A similar effect can be obtained by adopting a structure in which the width at the location including the scan electrode is thicker than the width at other locations.

  As described above, the present invention is useful for providing a large-screen, high-definition plasma display panel.

1 is a perspective sectional view showing a schematic configuration of a plasma display panel according to an embodiment of the present invention. Electrode arrangement of the plasma display panel Circuit block diagram showing a schematic configuration of a plasma display device for displaying an image on the plasma display panel Waveform diagram showing drive voltage waveform applied to each electrode of the plasma display panel The exploded perspective view which shows an example of the whole structure of the plasma display apparatus incorporating the same plasma display panel The top view which shows an example of arrangement | positioning of the drive circuit block which looked at the plasma display apparatus incorporating the same plasma display panel from the back side The top view which shows schematic structure of the plasma display panel by one embodiment of this invention Sectional drawing which shows schematic structure of one example of the conventional plasma display panel

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front plate 2 Back plate 3 Front substrate 4 Scan electrode 4a Transparent electrode 4b Bus electrode 5 Maintenance electrode 5a Transparent electrode 5b Bus electrode 6 Display electrode 7 Dielectric layer 7a 2nd dielectric layer 8 Protective layer 9 Back substrate 10 Data electrode DESCRIPTION OF SYMBOLS 11 Insulator layer 12 Partition 12a Vertical partition 12b Horizontal partition 13 Thick part 14 Plasma display panel

Claims (1)

A front plate on which display electrodes composed of scan electrodes and sustain electrodes are arranged and a rear plate on which data electrodes are arranged so as to intersect the display electrodes are partitioned by this partition. A plasma display panel arranged to face each other so as to form a discharge space,
A plasma display panel, wherein a width of the partition with respect to the vicinity including the scanning electrode is thicker than a width at other positions.

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