JP2011228166A - Plasma display panel and image display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PDP allowing the back surface side to be transparently visible from the front surface side during emitting no light, while being capable of normal image display as a PDP.SOLUTION: A front surface board 1 on which a plurality of display electrodes 3 and 4 are arranged and a back surface board 2 on which data electrodes 8 are arranged are arranged oppositely so as to define a discharge space, thereby constituting the PDP. Discharge cells are formed at portions where the display electrodes 3 and 4 respectively intersect the data electrodes 8, and a phosphor layer 10 is formed on the back surface board 2 side in each of the discharge cells. In each phosphor layer 10, an opening 10a is bored, so that the back surface side is transparently visible from the front surface side through the openings 10a.

Description

  The present invention relates to a plasma display panel (hereinafter also referred to as PDP) and an image display device using the same, and more particularly to a transparent display.

  PDP is broadly divided into AC type and DC type in terms of driving, and there are two types of discharge types, surface discharge type and counter discharge type. However, due to high definition, large screen, and ease of manufacturing, At present, the surface discharge type with a three-electrode structure is the mainstream.

  In this surface discharge type PDP structure, at least a pair of substrates transparent at least on the front side are arranged so as to form a discharge space between the substrates, and partition walls for partitioning the discharge space are arranged on the substrate. In addition, a plurality of discharge cells are configured by arranging an electrode group on the substrate so that discharge is generated in a discharge space partitioned by the partition walls, and providing phosphors that emit red, green, and blue light emitted by discharge. Thus, the phosphor is excited by vacuum ultraviolet light having a short wavelength generated by discharge, and red, green, and blue visible light is emitted from the red, green, and blue discharge cells, respectively, to perform color display.

  Such a PDP is capable of high-speed display compared to a liquid crystal panel, has a wide viewing angle, is easy to increase in size, and is self-luminous, so that the display quality is high. Recently, it has attracted particular attention among panel displays, and is used for various purposes as a display device at a place where many people gather or a display device for enjoying a large screen image at home.

  The above-mentioned PDP is held on the front side of a chassis member made of metal such as aluminum, and a circuit board constituting a drive circuit for causing the PDP to emit light is disposed on the back side of the chassis member, thereby displaying an image. An apparatus is configured (see Patent Document 1).

JP 2003-131580 A

  By the way, in recent years, there is a demand for display of various types of images for such a PDP, and one of them is so-called transparent that the back side of the PDP can be seen through from the front side when the PDP is not emitting light. There is a display. However, in reality, a transparent display that can display a normal image as a PDP and can be seen through the back side has not been realized.

  The present invention has been made in view of such a current situation, and can display a normal image as a PDP, and at the same time, when not emitting light, a PDP in which the back side can be seen from the front side, and an image using the PDP An object is to provide a display device.

  In order to achieve the above object, in the PDP according to the present invention, a discharge space is formed between a front substrate on which a plurality of display electrodes are arranged and a rear substrate on which data electrodes are arranged so as to intersect the display electrodes. In this way, a discharge cell is formed at a portion where the display electrode and the data electrode intersect with each other, and each discharge cell is provided with a phosphor layer having an opening on the back substrate side. It is what.

Here, it is preferable that a partition wall for partitioning adjacent discharge cells is formed on the rear substrate, and the phosphor layer is formed on the side surface of the partition wall so as to surround the opening.
An image display apparatus according to the present invention includes the PDP and a drive circuit that drives the PDP.

  According to the present invention, at the time of light emission, a normal image display as a PDP is possible by applying a voltage to the display electrode and the data electrode, discharging in each discharge cell, and emitting visible light in the phosphor layer. . At the same time, in each discharge cell, the phosphor layer provided on the back substrate side has an opening, and visible light can pass through the opening. Therefore, when not emitting light, the back surface of the PDP is viewed from the front side. A transparent display with a transparent side can be realized.

As a result, various forms of image display can be realized.
In the phosphor layer having the opening as described above, a resin layer is formed between the partition walls on the back substrate with a partition wall and a gap, and a phosphor layer is formed in the gap between the resin layer and the partition wall. Thereafter, it can be formed by removing the resin layer.

It is a principal part section perspective view showing a schematic structure of PDP concerning an embodiment of the invention. It is an electrode array diagram of PDP concerning an embodiment of the invention. 1 is a circuit block diagram of a display device using a PDP according to an embodiment of the present invention. It is a figure which shows the drive voltage waveform applied to each electrode of PDP concerning embodiment of this invention. It is a figure which shows the whole structure of the display apparatus using PDP concerning embodiment of this invention. It is a figure which shows the form of the fluorescent substance layer in PDP concerning embodiment of this invention. It is a figure explaining the manufacturing method of PDP concerning one embodiment of the present invention. It is a principal part top view of PDP concerning embodiment of this invention.

Hereinafter, although PDP concerning one embodiment of the present invention is explained using a figure, an embodiment of the present invention is not limited to this.
First, the structure of the PDP will be described with reference to the drawings.

  As shown in FIG. 1, the PDP 11 is configured by disposing a transparent glass front substrate 1 and a rear substrate 2 so as to face each other so as to form a discharge space therebetween. On the front substrate 1, a plurality of scanning electrodes 3 and sustaining electrodes 4 constituting display electrodes are formed in parallel with each other. A dielectric layer 5 is formed so as to cover the scan electrode 3 and the sustain electrode 4, and a protective layer 6 is formed on the dielectric layer 5.

A plurality of data electrodes 8 covered with an insulator layer 7 are provided on the back substrate 2, and a grid-like partition wall 9 is provided on the insulator layer 7.
The front substrate 1 and the rear substrate 2 are arranged to face each other so that the scan electrodes 3 and the sustain electrodes 4 and the data electrodes 8 cross each other, and in the discharge space formed between them, for example, neon And a mixed gas of xenon.

  Here, a discharge cell is formed at a portion where scan electrode 3, sustain electrode 4 and data electrode 8 intersect, and in each discharge cell, opening 10a is formed on back substrate 2 side, that is, on insulator layer 7 in the above configuration. The phosphor layer 10 is provided in a form having

Note that the structure of the PDP is not limited to that described above. For example, the partition walls 9 may be striped.
FIG. 2 is an electrode array diagram of the PDP 11. N scan electrodes SC1 to SCn (scan electrode 3 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 4 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 8 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of a plasma display device which is a display device using the PDP 11. The plasma display device includes a PDP 11, an image signal processing circuit 12, a data electrode drive circuit 13, a scan electrode drive circuit 14, a sustain electrode drive circuit 15, a timing generation circuit 16, and a power supply circuit (not shown).

  The image signal processing circuit 12 converts the image signal sig into image data for each subfield. The data electrode drive circuit 13 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 16 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each drive circuit block. Scan electrode drive circuit 14 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 15 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, the scan electrode drive circuit 14 and the sustain electrode drive circuit 15 include a sustain pulse generator 17.

Next, a driving voltage waveform for driving the PDP 11 and its operation will be described with reference to FIG. FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the PDP 11.
In the plasma display device according to the present embodiment, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period of the first subfield, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SC1 to SCn, and positive walls on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to 1) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive write pulse voltage Vd (V) is applied to m). At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va) (V). And the discharge start voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm and the scan electrode SC1 to which the address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as a first voltage, and ground potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn as a second voltage. Apply. In the discharge cell in which the address discharge has occurred at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and the phosphor layer emits light due to the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. At this time, a positive wall voltage is also accumulated on the data electrode Dk.

  In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi, Negative wall voltage is accumulated on sustain electrode SUi, and positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, by applying sustain pulses of the number corresponding to the luminance weight alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period. Done. Thus, the maintenance operation in the maintenance period is completed.

The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.
FIG. 5 shows an example of the overall configuration of a plasma display device using the PDP having the structure described above.

The chassis member 21 has a frame structure having an opening in a portion corresponding to the image display portion of the PDP 11, and is made of metal such as aluminum. The PDP 11 is held on the front side of the chassis member 21.
As a mechanism for the chassis member 21 to hold the PDP 11, for example, the chassis member 21 may be held by a sheet-like adhesive member, or may be held by screwing in combination with an appropriate member.

  Further, in order to efficiently transmit heat generated when the PDP 11 is driven to the chassis member 21 and perform heat dissipation, it is preferable to interpose a heat dissipation sheet between the PDP 11 and the chassis member 21.

  As this heat radiating sheet, for example, an insulating heat radiating sheet having a thickness of about 1 mm to 2 mm and containing a filler that enhances thermal conductivity in a synthetic resin material such as acrylic, urethane, silicon resin, or rubber, a graphite sheet, A metal sheet etc. can be used. Further, the above-described adhesive member may be formed by giving an adhesive force to the heat radiating sheet itself, and the PDP 11 may be bonded and held to the chassis member 21. Also, the heat radiating sheet has no adhesive force and is separately bonded on both sides. The PDP 11 may be bonded to the chassis member 21 using a tape or the like.

  In addition, in order to improve heat dissipation on the entire surface of the PDP 11, heat generated in the PDP 11 can be quickly conducted to the chassis member 21 with the contact surface of the rear substrate 2 of the PDP 11 with the chassis member 21 or with the chassis member 21. It is also possible to adopt a structure in which a film with good heat conductivity is formed on the contact surface side with the heat dissipation sheet interposed therebetween, or a sheet with good heat conductivity is attached. In this case, transparency is required for the heat-conductive film or sheet, but this can be achieved, for example, by forming ITO, which is a light-conductive transparent film.

  In addition, flexible wiring boards 22 as display electrode wiring members connected to the electrode lead portions of the scan electrodes 3 and the sustain electrodes 4 are provided on both side edges of the PDP 11, and are arranged on the back side through the outer peripheral portion of the chassis member 21. The drive circuit block (not shown) of the scan electrode drive circuit 14 and the drive circuit block (not shown) of the sustain electrode drive circuit 15 are connected via a connector.

  On the other hand, a plurality of flexible wiring boards 25 as data electrode wiring members connected to the electrode lead portions of the data electrodes 8 are provided on the lower and / or upper edge of the PDP 11, and the flexible wiring boards 25 are A plurality of data drivers (not shown) of the data electrode drive circuit 13 are electrically connected to each other, and are routed to the back side through the outer peripheral portion of the chassis member 21 to drive the data electrode drive circuit 13 as shown in FIG. (Not shown).

  Although not shown, the plasma display device includes a control circuit block, and is transmitted from an input signal circuit block including an input terminal portion to which a connection cable for connecting to an external device such as a television tuner is detachably connected. The image data is converted into an image data signal corresponding to the number of pixels of the PDP 11 based on the video signal to be supplied to the drive circuit block of the data electrode drive circuit 13, and a discharge control timing signal is generated. 14 drive circuit blocks and the drive circuit block of the sustain electrode drive circuit 15 to perform display drive control such as gradation control. Further, a power supply block for supplying a voltage to each circuit block is provided, and a commercial power supply voltage is supplied through a connector to which a power cable is attached.

  In the installation of the drive circuit block (not shown), the control circuit block (not shown), the input signal circuit block (not shown), and the power supply block (not shown), for example, the chassis member 21 What is necessary is just to set it as the structure fixed to a boss | hub part with a bis | screw etc. in a frame part, or the structure installed separately as a separate unit.

Further, the frame part of the chassis member 21 may be provided with a structure in which a stand pole 36 for holding the apparatus in an upright state is fixed.
The module having the above structure is housed in a casing having a front protective cover 37 disposed on the front side of the PDP 11 and a back cover 38 disposed on the rear side of the chassis member 21, thereby the plasma display device. Is completed.

The front protective cover 37 is attached to a front frame 39 made of a resin or metal having an opening 39a from which an image display area on the front side of the PDP 11 is exposed, and to the opening 39a of the front frame 39, and is used for optical filters and electromagnetic waves. And a protective plate 40 made of glass or the like provided with an unnecessary radiation suppressing film for suppressing unnecessary radiation. The protective plate 40 has a peripheral portion of the protective plate 40 at an opening 39a of the front frame 39. Are attached to the front frame 39 by being sandwiched between a peripheral edge portion of the metal plate and a protective plate pressing metal fitting (not shown). The back cover 38 has an opening at a portion corresponding to the image display portion of the PDP 11. Further, the back cover 38 is provided with a plurality of ventilation holes (not shown) for releasing heat generated by the module to the outside.
[Phosphor layer form]
As described above, in the PDP 11, the phosphor layer 10 is provided on a part of the surface of the back substrate 2 side (the insulator layer 7 in the above-described configuration) and a part of the side surface of the partition wall 9.

A state in which the phosphor layer 10 is formed is schematically shown in FIG.
Fig.6 (a) is a top view, FIG.6 (b) is XX arrow sectional drawing in Fig.6 (a). As shown in FIG. 6, the phosphor layer 10 is not formed on a part of the surface of the insulator layer 7, and an opening 10 a is formed in the phosphor layer 10. That is, the opening 10 a is formed so as to penetrate the phosphor layer 10.

  Thus, since the phosphor layer 10 is formed in a form having the opening 10a, image display can be performed by light emission from the phosphor layer 10 when driven, and before and after sandwiching the PDP 11 when not driven. It can be seen through the opening 10a.

Therefore, a so-called see-through display or transparent display can be realized.
The phosphor layer 10 is preferably formed so as to surround the opening 10a along the side surface of the partition wall 9 as shown in FIG.

  That is, the inner wall surface of the opening 10a preferably has a shape substantially along the side surface of the partition wall 9 as shown in FIG. 6B, and the planar shape of the opening 10a is also as shown in FIG. In addition, it is preferable to have the same shape as the cell formation (vertically long shape in FIG. 6).

However, the shape of the opening 10a can be set to an arbitrary shape without being restricted thereto.
The smaller the area of the opening 10a, the lower the visible light transmittance in the PDP. Therefore, it is preferable to set the area within a range of 25 to 75% with respect to the area of the cell surrounded by the partition walls 9. The number of openings 10a formed in one cell may be two or more.

As for the position where the opening 10a is formed, it is preferable that the opening 10a is formed in the central portion between the adjacent barrier ribs 9 (the central portion of the discharge cell) as shown in FIG. However, it may be formed at a position deviated from the central portion between the partition walls 9.
[Method of forming phosphor layer]
Hereinafter, a method for forming the phosphor layer 10 on the surface of the back substrate 2 side (insulator layer 7 in the above-described configuration) in the form having the opening 10a as shown in FIG. 6 will be described.

FIG. 7 is a flowchart illustrating an example of a method for forming the phosphor layer 10 in the method for manufacturing the PDP 11 according to the embodiment.
After the silver paste is applied and baked on the back substrate 2 to form the data electrode 8 and the insulator layer 7 is formed so as to cover it, as shown in FIG. 7A, on the insulator layer 7, The partition wall 9 is formed by applying glass paste at a predetermined pitch and baking it.

  Using a resin component paste that can be removed by baking, as shown in FIGS. 7B and 7C, a resin component paste 50 is applied so as to cover the partition walls 9 and dried. The applied resin component paste shrinks by drying to form a resin layer 51. About the application quantity of the resin component paste 50, as shown in FIG.7 (c), the height of the resin layer 51 after drying is set so that it may become equivalent to the height of the partition 9. FIG.

As shown in FIG. 7D, a DFR (dry film resist) 52 is laminated on the resin layer 51.
As shown in FIG. 7E, the DFR 52 is patterned so that the DFR 52 remains only in the central portion between the adjacent partition walls 9.

  As shown in FIG. 7F, a portion of the resin layer 51 that is not covered with the DFR 52 is removed. This partial removal of the resin layer 51 can be performed by irradiating or blasting the patterned DFR 52 from above. As shown in FIG. 7G, the DFR 52 is peeled off.

  As shown in FIG. 7H, the phosphor paste 10b is filled between the partition wall 9 and the resin layer 51. Then, before the resin layer 51 absorbs the solvent contained in the phosphor paste 10b, the phosphor paste 10b is dried to form the phosphor layer 10 as shown in FIG. 7 (i).

And finally, as shown in FIG.7 (j), the resin layer 51 is burned down by baking. By this baking, the region occupied by the resin layer 51 becomes the opening 10a.
Therefore, the formed phosphor layer 10 has a shape including the opening 10a. That is, as shown in FIG. 6, the phosphor layer 10 is not formed on a part of the surface of the back substrate 2 side (insulator layer 7 in the above-described configuration).

  Regarding the positional relationship between the opening 10a and the data electrode 8, since the data electrode 8 is normally formed so as to pass through the central portion between the partition walls 9, the opening 10a and the data electrode 8 overlap with each other to form the opening 10a. The visible light transmittance at the aperture 10a tends to decrease, but the decrease in the visible light transmittance at the opening 10a is reduced by forming the data electrode 8 from a transparent material or by narrowing the line width of the data electrode 8. be able to.

  Further, for example, as schematically shown in a plan view in FIG. 8, if the lateral position of the data electrode 8 is shifted from the center line A of the opening 10 a and set to a position overlapping the phosphor layer 10, the opening Since the opening degree of 10a can be raised, it is preferable when improving visible light transmittance.

  Note that the insulator layer 7 is not indispensable for the configuration of the PDP, and the data electrode 8 may not be covered with the insulator layer 7. In this case, if the position of the data electrode 8 overlaps with the position of the opening 10a, the data electrode 8 is exposed to the discharge space. However, the position of the data electrode 8 is shifted as shown in FIG. As a result, the data electrode 8 can be prevented from being exposed to the discharge space.

  As described above, according to the present invention, it is possible to realize a transparent display in a PDP.

8 Data electrode 9 Partition 10 Phosphor layer 10a Opening 11 PDP
21 Chassis member

Claims (3)

A plasma display panel in which a front substrate on which a plurality of display electrodes are arranged and a rear substrate on which data electrodes are arranged so as to intersect the display electrodes are opposed to each other so that a discharge space is formed therebetween,
A discharge cell is formed at a portion where the display electrode and the data electrode intersect,
In each discharge cell, a phosphor layer having an opening on the back substrate side is provided,
Plasma display panel. The back substrate is formed with partition walls that partition adjacent discharge cells,
The plasma display panel according to claim 1, wherein the phosphor layer is formed on a side surface of the partition so as to surround the opening. A plasma display panel according to claim 1 or 2,
An image display device comprising a driving circuit for driving the plasma display panel.

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