JP2011159522A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image quality and product quality of a plasma display device. <P>SOLUTION: The plasma display device includes a plasma display panel including: a front substrate having a plurality of scanning electrodes and sustaining electrodes and a discharge gap arranged therebetween; a rear substrate having a plurality of data electrodes arranged in a direction intersecting with the scanning electrodes and sustaining electrodes, and a barrier wall for partitioning a discharge space; and a plurality of discharge cells formed in an intersection part of the scanning electrodes and sustaining electrodes, and the data electrodes. The plasma display device includes a plurality of connection terminals 21, which are formed on an end part of the front substrate 1 and to which a wiring member for connecting to an external drive circuit is connected, and a plurality of intermediate connection wirings 22 which electrically connect the connection terminals 21 and the scanning electrodes 3 respectively, and are formed in a region between end parts of the scanning electrodes 3 on the front substrate 1 and the connection terminals 21. The intermediate connection wirings 22 are covered with a sealing member 23. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a plasma display apparatus using a plasma display panel (hereinafter referred to as a panel) as a display device.

  Panels used in this plasma display device are roughly classified into AC type and DC type in terms of driving, and there are two types of discharge types: surface discharge type and counter discharge type. Due to the simplicity of manufacturing, at present, the mainstream of plasma display devices is a surface discharge type having a three-electrode structure.

  In this surface discharge type plasma display panel structure, at least a pair of substrates whose front sides are transparent are arranged to face each other so that a discharge space is formed between the substrates, and partition walls for dividing the discharge space into a plurality of substrates are arranged on the substrate. In addition, a plurality of discharge cells are configured by arranging an electrode group on the substrate so that a discharge is generated in the discharge space partitioned by the barrier ribs, and providing phosphors that emit red, green, and blue light emitted by the discharge. However, phosphors are excited by vacuum ultraviolet light having a short wavelength generated by discharge, and red, green, and blue visible light is emitted from red, green, and blue discharge cells, respectively, to perform color display.

  Such a plasma display device can display at a higher speed than a liquid crystal panel, has a wide viewing angle, is easy to enlarge, and is self-luminous so that the display quality is high. Recently, the flat panel display has attracted particular attention and is used for various purposes as a display device in a place where many people gather and a display device for enjoying a large screen image at home.

  In such a plasma display device, a circuit constituting a driving circuit for holding a panel made mainly of glass on the front side of a chassis member made of metal such as aluminum and causing the panel to emit light on the back side of the chassis member. Modules are configured by arranging the substrates (see Patent Document 1), and a large screen and high definition have been promoted. However, with the spread of general households, high image quality and low consumption are being promoted. There is also a growing demand for power.

JP 2003-131580 A

  The present invention has been made in view of such a current situation, and an object thereof is to improve image quality and quality of a plasma display device.

  In order to solve this problem, the present invention is arranged so that a discharge space is formed between a front substrate arranged with a discharge gap between a plurality of scan electrodes and sustain electrodes and the front substrate. A plurality of data electrodes arranged in a direction intersecting with the scan electrodes and the sustain electrodes, and a rear substrate on which partition walls are formed to partition the discharge space, the scan electrodes, the sustain electrodes, the data electrodes, A plasma display panel is formed by forming a plurality of discharge cells at intersections of the plasma display panel, and having a data driver for supplying a voltage to the data electrode of the plasma display panel. The front substrate and the rear substrate are formed by sealing the peripheral portions with a sealing member, and the front substrate A plurality of connection terminals to which wiring members for connection to an external drive circuit are connected, the connection terminals and the scan electrodes are electrically connected to each other, and the scan electrodes on the front substrate are connected to each other. A plurality of intermediate connection wires formed in a region between the end portion and the connection terminal, and in the intermediate connection wire portion, a connection interval with the connection terminal in which a wiring interval is narrower than other portions The end portion is covered with the sealing member.

  In the present invention, in the portion of the plurality of intermediate connection wirings that electrically connect the plurality of connection terminals and the scan electrodes formed at the end portion of the front substrate, the wiring interval is narrower than the other portions. The connection side end with the connection terminal is configured to be covered with a sealing member, and the intermediate connection wiring having a narrower wiring interval than other parts is covered with the sealing member. Migration can be prevented, and the reliability of the lead-out wiring portion to the outside of the scan electrode can be ensured.

The perspective view which shows the principal part of the panel used for the plasma display apparatus by one embodiment of this invention. Electrode arrangement of the panel Circuit block diagram of the plasma display device Waveform diagram showing drive voltage waveform applied to each electrode of panel Sectional drawing which shows the discharge cell structure of the panel of the plasma display apparatus Schematic plan view showing the state of the lead-out wiring side of the scanning electrode of the panel of the plasma display device The top view which shows the detail of the principal part of FIG.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7, but the embodiment of the present invention is not limited to this.

  First, the structure of the panel in the plasma display device will be described with reference to FIG. As shown in FIG. 1, the panel is configured by disposing a glass front substrate 1 and a back substrate 2 so as to form a discharge space therebetween. On the front substrate 1, a plurality of scan electrodes 3 and sustain electrodes 4 constituting display electrodes are formed in parallel with each other with a discharge gap G therebetween. A dielectric layer 5 made of a glass material is formed so as to cover the scan electrode 3 and the sustain electrode 4, and a protective layer 6 made of MgO is formed on the dielectric layer 5. The scanning electrode 3 and the sustain electrode 4 are composed of transparent electrodes 3a and 4a such as ITO, and bus electrodes 3b and 4b made of Ag formed on the transparent electrodes 3a and 4a.

  A plurality of data electrodes 8 made of Ag arranged in stripes covered with an insulating layer 7 made of a glass material are provided on the back substrate 2, and the front substrate 1 is formed on the insulating layer 7. A partition wall 9 made of a cross-shaped glass material is provided to divide the discharge space between the rear substrate 2 and the rear substrate 2 for each discharge cell. Further, red (R), green (G), and blue (B) phosphor layers 10 are provided on the surface of the insulator layer 7 and the side surfaces of the partition walls 9. The front substrate 1 and the rear substrate 2 are arranged to face each other so that the scan electrodes 3 and the sustain electrodes 4 and the data electrodes 8 cross each other, and in the discharge space formed between them, for example, neon And a mixed gas of xenon. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the panel 11. In the display area of the panel 11, n scan electrodes SC1 to SCn (scan electrode 3 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 4 in FIG. 1) are provided in the row direction. Scan electrode SC1-scan electrode SC2-sustain electrode SU2,... Are arranged, and m data electrodes D1-Dm (data electrode 8 in FIG. 1) are arranged in the column direction as scan electrodes SC1-SCn. And n sustain electrodes SU1 to SUn. A discharge cell S is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and discharge cell S is discharged. M × n are formed in the space. In addition, a non-display area is provided around the display area of the panel 11, and a plurality of dummy electrodes A (two in the illustrated example) are formed in the non-display area.

  FIG. 3 is a circuit block diagram of a plasma display device using this panel. The plasma display device includes a panel 11, an image signal processing circuit 12, a data electrode drive circuit 13, a scan electrode drive circuit 14, a sustain electrode drive circuit 15, a timing generation circuit 16, and a power supply circuit (not shown). Further, as shown in FIG. 2, the data electrode driving circuit 13 is connected to a lead terminal at one end of the data electrode 8 of the panel 11 and includes a plurality of data composed of semiconductor elements for supplying a voltage to the data electrode 8. It has a driver 13a. The data electrode 8 is divided into a plurality of blocks as one block by several data electrodes 8, and a plurality of data drivers 13a are connected to the electrode lead-out portion at the lower end of the panel 11 and arranged in units of the block. Yes.

  In FIG. 3, an image signal processing circuit 12 converts an image signal sig into image data for each subfield. The data electrode drive circuit 13 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 16 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each drive circuit block. Scan electrode drive circuit 14 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 15 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, the scan electrode drive circuit 14 and the sustain electrode drive circuit 15 include a sustain pulse generator 17.

  Next, a driving voltage waveform for driving the panel and its operation will be described with reference to FIG. FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the panel.

  In the plasma display device according to the present embodiment, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period of the first subfield, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SC1 to SCn, and positive walls on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to 1) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive write pulse voltage Vd (V) is applied to m). At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va) (V). And the discharge start voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm and the scan electrode SC1 to which the address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as a first voltage, and ground potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn as a second voltage. Apply. In the discharge cell in which the address discharge has occurred at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and the phosphor layer emits light due to the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. At this time, a positive wall voltage is also accumulated on the data electrode Dk.

  In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi, Negative wall voltage is accumulated on sustain electrode SUi, and positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, by applying sustain pulses of the number corresponding to the luminance weight alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period. Done. Thus, the maintenance operation in the maintenance period is completed. The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.

  Next, the panel structure of the plasma display device according to the present invention will be described in more detail with reference to FIGS.

  FIG. 5 shows a cross section of the panel structure of the plasma display device according to one embodiment of the present invention, FIG. 6 shows a schematic plane showing the arrangement of the connection terminals on the scan electrode side of the front substrate, and FIG. The main part around the connection terminal is shown enlarged.

  In FIG. 5, the cross-shaped barrier ribs 9 partitioning the discharge cells S are composed of vertical barrier ribs 9a formed in parallel to the data electrodes 8 and horizontal barrier ribs 9b formed to be orthogonal to the vertical barrier ribs 9a. Yes. The phosphor layer 10 formed by coating in the barrier rib 9 is arranged in the order of the blue phosphor layer 10B, the red phosphor layer 10R, and the green phosphor layer 10G in a stripe shape along the vertical barrier rib 9a. Is formed.

  As shown in FIGS. 6 and 7, a plurality of connection terminals 21 made of a conductive member such as Ag for connecting the scanning electrode 3 to an external drive circuit are provided in the row direction at the end of the front substrate 1. Are arranged at a predetermined pitch. The connection terminals 21 are formed at the end of the front substrate 1 as a group, in accordance with the number of wiring patterns of a wiring member such as a flexible wiring board used for connection with an external drive circuit. .

  Further, in order to electrically connect the plurality of connection terminals 21 and the bus electrodes 3b of the scan electrodes 3 to the regions between the end portions of the scan electrodes 3 on the front substrate 1 and the connection terminals 21, respectively. A plurality of intermediate connection wirings 22 made of a conductive member such as Ag are formed. The intermediate connection wiring 22 has one end connected to the connection terminal 21 and the other end connected to the bus electrode 3b of the scanning electrode 3, and the wiring interval in the intermediate connection wiring 22 is smaller than that of other portions. It is narrower. Further, the panel is configured by sealing the peripheral portions of the front substrate 1 and the back substrate 2 with a sealing member 23 made of frit glass. The sealing member 23 is disposed so as to be covered.

  FIG. 7 shows the intermediate connection wiring 22 in an enlarged manner. As shown in FIG. 7, the intermediate connection wiring 22 has a portion in which the wiring interval is narrower than that of the other portions. The connection side end 22 a is covered with the sealing member 23.

  Here, although not shown in the figure, on the sustain electrode 4 side, a common connection structure is adopted for driving the panel, and in this embodiment, the sustain electrode 4 side lead-out structure is also provided. Forms a common pattern made of a conductive member such as Ag to which the bus electrodes 4b of all the sustain electrodes 4 are commonly connected at the end of the front substrate 1 opposite to the connection terminal 21. The bus electrode 4b of the sustain electrode 4 is connected to the first electrode.

  As described above, in the present invention, the wiring interval is reduced in the portions of the plurality of intermediate connection wires 22 that electrically connect the plurality of connection terminals 21 and the scan electrodes 3 formed at the end portion of the front substrate 1. The connection side end 22a with the connection terminal 21 that is narrower than other portions is covered with the sealing member 23, and migration in the intermediate connection wiring 22 where the wiring interval is narrower than other portions. And the reliability of the lead-out wiring portion to the outside of the scan electrode can be ensured.

  As described above, the present invention is useful in providing a plasma display device with high image quality and low power consumption.

DESCRIPTION OF SYMBOLS 1 Front substrate 2 Back substrate 3 Scan electrode 4 Sustain electrode 5 Dielectric layer 6 Protective layer 7 Insulator layer 8 Data electrode 9 Partition 10 Phosphor layer 11 Panel 21 Connection terminal 22 Intermediate connection wiring 23 Sealing member

Claims (1)

The front substrate disposed with a discharge gap between a plurality of scan electrodes and sustain electrodes and the front substrate are arranged so as to face each other so as to form a discharge space and intersect the scan electrodes and sustain electrodes. A plurality of data electrodes arranged in a direction and a rear substrate on which barrier ribs defining the discharge space are formed, and a plurality of discharge cells are formed at intersections of the scan electrodes, the sustain electrodes, and the data electrodes. In the plasma display apparatus comprising the plasma display panel and having a data driver for supplying a voltage to the data electrode of the plasma display panel, the plasma display panel seals the peripheral portions of the front substrate and the back substrate It is configured by sealing with a member, and is formed at the end of the front substrate and is connected to an external drive circuit. A plurality of connection terminals to which wiring members for connection are connected; electrically connecting the connection terminals and the scan electrodes; and between the end portions of the scan electrodes on the front substrate and the connection terminals A plurality of intermediate connection wirings formed in a region, and in the intermediate connection wiring portion, the connection-side end portion of the connection terminal with which the wiring interval is narrower than other portions is covered with the sealing member. A plasma display device characterized in that it is configured as follows.

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