JP2010045374A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having shallow impurity regions. <P>SOLUTION: The semiconductor device includes a semiconductor including a channel forming region, and gate electrode parts 752, 753 formed on the channel forming region with a floating gate 762 and a control gate 763. In the semiconductor on the side of one of the gate electrode parts 752, 753, a first impurity region 755 is formed which is overlapped with the floating gate 762. In the semiconductor on the side of the other floating gate 762, second impurity regions 757, 758 are formed with laser doping treatment whose depths are 0.1 μm or smaller and which are not overlapped with the floating gate 762. The length of the channel forming region is 0.3 μm or smaller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a technique for performing a doping process in a process of manufacturing a semiconductor device such as a semiconductor integrated circuit, and a semiconductor device (element) manufactured by the above technique.

Conventionally, a thermal diffusion method or an ion implantation method is known as a doping technique. The thermal diffusion method is a method in which impurities are diffused into a semiconductor in a high temperature atmosphere of 500 degrees to 1200 degrees, and the ion implantation method is a method in which ionized impurities are accelerated by an electric field and implanted into a predetermined place. However, in the ion implantation method, the crystal structure is remarkably broken by high energy ions and becomes amorphous or close to it, and the electrical characteristics are remarkably deteriorated. Therefore, the heat diffusion method requires the same heat treatment. Since the ion implantation method is easier to control the impurity concentration than the thermal diffusion method, it has become an indispensable technique for manufacturing VLSI and ULSI.

However, the ion implantation method was not without problems. The biggest problem was that it was difficult to control the diffusion of the implanted ions. This is a big problem especially in so-called quarter micron devices having a design rule of 0.5 μm or less.
In recent years, regions in which impurities are diffused (diffusion regions)
However, it is difficult to form a diffusion region having a depth of 0.1 μm or less with good reproducibility by the ion implantation method. The above points will be described with reference to FIG.

The first problem is that, due to ion implantation, ions implanted in the semiconductor diffuse laterally due to secondary scattering and thermally spread around the heat treatment process. is there. Such an effect depends on design rules (typically MOS
When the width of the gate electrode of the FET was 1.0 μm or more, there was almost no problem, but below that, the diffusion portion due to the above effect was reduced to the width of the gate electrode as shown in FIG. As a result, the gate electrode 205 and the diffusion regions (source and drain) 202 and 203 are geometrically overlapped.
Such an overlap becomes a source of parasitic capacitance between the gate electrode, the source, and the drain, and lowers the operation speed.

The second problem is largely due to two effects. One is the diffusion effect due to thermal factors as pointed out in the first problem. For this reason, the thickness of the diffusion region is set to 0.
It is difficult to make it 1 μm or less. Another effect, which is remarkable when the semiconductor is crystalline, is the effect of channeling in ion implantation. This is an effect that, when incident perpendicularly to the crystal plane, ions do not receive any scattering and reach the deep part of the substrate.

Conventionally, in order to avoid this channeling effect, ion implantation is performed with an inclination of several degrees with respect to the crystal plane. However, even if such a contrivance is made, ions whose orbits are bent inside the semiconductor may meet the channeling conditions. Therefore, FIG.
As shown in (B), ions enter deeply. In addition, when ions are implanted into a polycrystalline semiconductor, the crystal planes are random, so that the ion depths are completely different.

There are other problems when using polycrystalline semiconductors. That is, in a polycrystalline semiconductor, the thermal diffusion of doped impurities tends to proceed through crystal grain boundaries, and therefore FIG.
As shown in C), the doping cannot be performed uniformly. These problems have been difficult to solve by the conventional methods of ion implantation and recrystallization by heat treatment. Of course, the thermal diffusion method could not be solved at all.

The problems to be solved by the present invention are summarized as follows. That is, the first is to prevent the lateral diffusion of impurities, and the second is to control the diffusion depth to 0.1 μm or less, preferably 50 nm or less. An object of the present invention is to provide a method for solving at least one of these two problems in part or all of a single crystal, polycrystal, or a semiconductor material equivalent thereto. By satisfying the above conditions, a MOS device having a channel length of 1.0 μm or less, typically 0.1 to 0.3 μm, can be stably produced.

In order to solve the above-described problems, the present invention provides a high-purity reactive gas (impurity gas) containing impurities that impart conductivity to a semiconductor, or a relatively stable gas such as hydrogen, fluorine, helium, or argon. Impurities are doped into the sample semiconductor by irradiating the surface of the sample semiconductor with pulsed laser light in an atmosphere diluted in a small amount. In this method, an impurity gas in the vicinity of the semiconductor surface heated instantaneously by laser irradiation is decomposed or reacted with the semiconductor surface, and impurities are doped only in a very thin portion of the semiconductor surface. The thickness depends on the temperature at which the semiconductor surface is held, but can be 0.1 μm or less.

In such a reaction, thermal diffusion causes the pulse width of laser light to be 1 μsec or less,
Preferably, it can be substantially eliminated by setting it to 100 nsec or less. Further, in the present invention, there is no channeling or secondary scattering that has become a problem in ion implantation. Therefore, as shown in FIG. 1A, an extremely ideal diffusion region is formed, and the impurity concentration in the depth direction is formed. The distribution is concentrated only at a required depth as shown in FIG. 1B, and the impurity distribution in the depth direction in the impurity region formed in the semiconductor is indicated by a distribution curve 106. Strictly speaking, there is also lateral diffusion, but the size is typically 50 nm or less, which can be ignored in real devices.

Further, since there is no thermal influence even in a semiconductor material having a grain boundary, the diffusion region is not affected by the grain boundary as shown in FIG. In addition, in the present invention, since a non-thermal equilibrium state of heating by a pulse laser is used, it is possible to diffuse an impurity at a high concentration that was impossible in the past.

In the present invention, the target concentration can be obtained by adjusting the energy of the laser, the concentration of the impurity gas in the atmosphere, the semiconductor surface temperature, and the like. In the present invention, the semiconductor surface where the impurity is to be diffused may be exposed or covered with another coating. When covered with another film, impurities are blocked by the chemical and physical properties of the film, and as a result, the diffusion concentration and diffusion depth into the semiconductor are controlled.

In the present invention, when a silicon semiconductor (silicon) is used as a semiconductor and a p-type is imparted, a trivalent impurity, typically B (boron) or the like can be used. If N-type is added, a pentavalent impurity, typically P (phosphorus) or As
(Arsenic) or the like can be used. And AsH as reactive gas containing these impurities
₃ , PH ₃ , BF ₃ , BCl ₃ , B (CH ₃ ) _{3 and the} like can be used.

As a semiconductor, in addition to a conventional wafer-like single crystal silicon semiconductor, an amorphous silicon semiconductor thin film formed by a vapor deposition method, a sputtering method, or the like is generally used if a TFT is manufactured. It is done. The present invention can also be applied to a polycrystalline or single crystal silicon semiconductor formed on an insulating substrate by liquid phase growth. Furthermore, it is needless to say that the semiconductor is not limited to a silicon semiconductor and may be other semiconductors.

As the laser light, it is useful to use a pulse oscillation type excimer laser device. This is because in a pulsed laser, the sample is heated instantaneously and is limited to the surface only, and does not affect the substrate. The heating by the continuous wave laser is impossible to realize the non-thermal equilibrium state as described above and is a local heating. Therefore, the heating part may be caused by a significant difference in thermal expansion between the heating part and the substrate. May peel. In this respect, in the pulse laser, the thermal relaxation time is overwhelmingly smaller than the reaction time of mechanical stress such as thermal expansion, and no mechanical damage is caused.

In particular, excimer laser light is ultraviolet light that is efficiently absorbed by many semiconductors including silicon and has a short pulse duration of 10 nsec. In addition, the excimer laser has already been used in experiments in which an amorphous silicon thin film is crystallized by laser irradiation to obtain a highly crystalline polycrystalline silicon thin film. As a specific type of laser, it is appropriate to use an ArF excimer laser (wavelength 193 nm), a XeCl excimer laser (wavelength 308 nm), a XeF excimer laser (wavelength 351 nm), a KrF excimer laser (248 nm), or the like.

In the present invention, the semiconductor surface may be heated or cooled. By controlling the temperature of the semiconductor surface, it becomes possible to promote or suppress the diffusion of impurities,
Those who implement the present invention are recommended to perform temperature control in order to obtain the target impurity concentration and diffusion depth.

In the present invention, in order to promote the decomposition of the impurity gas, it is also effective to convert the impurity gas into plasma using direct current or alternating current electric energy. The electromagnetic energy applied for this purpose is generally high frequency energy of 13.56 MHz. By the decomposition of the doping gas by the electromagnetic energy, doping can be performed efficiently even when a laser beam that cannot directly decompose the doping gas is used. The type of electromagnetic energy is not limited to a frequency of 13.56 MHz, for example 2.45 GH
A higher activation rate can be obtained by using z microwaves. 2.45GH
ECR conditions generated by the interaction of the z microwave and the 875 Gauss magnetic field may be used.
It is also effective to use light energy that can directly decompose the doping gas.

A conceptual diagram of the apparatus of the present invention is shown in FIGS. FIG. 3 includes a substrate heating device,
FIG. 4 shows an apparatus equipped with an electromagnetic device for generating plasma in addition to that. Since these drawings are conceptual, of course, in an actual device,
Other parts may be provided as necessary. In the following, the method of use will be outlined.

In FIG. 3, the sample 304 is placed on the sample holder 305. First, the chamber 301 is evacuated by an exhaust system 307 connected to an exhaust device. In this case, it is desirable to exhaust as high a vacuum as possible. That is, carbon, nitrogen, and oxygen, which are atmospheric components, are generally not preferable for semiconductors. Such an element is taken into the semiconductor, but may reduce the activity of impurities added at the same time. In addition, the crystallinity of the semiconductor is impaired, and it causes a dangling bond at the grain boundary. Therefore, it is desirable to evacuate the chamber to 10 ⁻⁶ torr or less, preferably 10 ⁻⁸ torr or less.

It is also desirable to activate the heater 306 before and after exhausting to expel atmospheric components adsorbed inside the chamber. As used in the current vacuum apparatus, it is also desirable to provide a spare chamber in addition to the chamber so that the chamber does not directly touch the atmosphere. As a matter of course, it is desirable to use a turbo molecular pump or a cryopump that is less contaminated with carbon or the like than a rotary pump or an oil diffusion pump.

When exhausted sufficiently, the reactive gas is introduced into the chamber by the gas system 308.
The reactive gas may consist of a single gas, or may be diluted with hydrogen, argon, helium, neon, or the like. The pressure may be atmospheric pressure or lower. These are selected in consideration of the type of the target semiconductor, the impurity concentration, the depth of the impurity region, the substrate temperature, and the like.

Next, the sample is irradiated with laser light 303 through the window 302. At this time, the sample is heated to a certain temperature by a heater. Laser light is usually 1-50 in one place
Irradiation is about pulse. With a very large variation in laser pulse energy,
If the number of pulses is too small, the probability of occurrence of a defect is high. On the other hand, it is not desirable from the viewpoint of mass productivity (throughput) to irradiate one place with too many pulses. According to the knowledge of the present inventor, the number of pulses described above was appropriate from the standpoints of mass productivity and yield.

In this case, for example, when the laser pulse has a specific rectangular shape of 10 mm (x direction) × 30 mm (y direction), the same region is irradiated with 10 pulses of laser pulses. Although the method of moving to a part may be used, the laser may be moved by 1 mm in the x direction per pulse.

When the laser irradiation is completed, the chamber is evacuated, the sample is cooled to room temperature, and the sample is taken out. Thus, in the present invention, the doping process is very simple, and
It is fast. That is, in the conventional ion implantation process, (1) Doping pattern formation (resist coating, exposure, development)
(2) Ion implantation (or ion doping)
(3) Three steps of recrystallization were necessary. However, in the present invention, (1) Doping pattern formation (resist application, exposure, development)
(2) The process is completed in two steps of laser irradiation.

The apparatus in FIG. 4 is almost the same as in FIG. First, the inside of the chamber 401 is evacuated by an exhaust system 407 and a reactive gas is introduced from the gas system 408. The sample 404 on the sample holder 405 is irradiated with laser light 403 through the window 402. At that time, power is supplied to the electrode 409 from a high-frequency or alternating current (or direct current) power supply 410 to generate plasma or the like in the chamber to activate the reactive gas. In the drawing, the electrode is shown as a capacitive coupling type, but may be an inductive (inductance) coupling type. Further, the sample holder may be used as one electrode even if it is a capacitive coupling type.
Further, the sample may be heated by the heater 406 during laser irradiation.

FIG. 5 shows a state of another doping treatment apparatus of the present invention. That is, the chamber 501
Is provided with a slit-like window 502 made of anhydrous quartz glass. The laser beam is formed into an elongated shape in accordance with this window. The laser beam is, for example, 10 mm x 300 m
The rectangle was m. The position of the laser beam is fixed. The chamber has an exhaust system 5
07 and a gas system 508 for introducing a reactive gas are connected. A sample holder 505 is provided in the chamber, a sample 504 is placed thereon, and an infrared lamp (functioning as a heater) 506 is provided below the sample holder. The sample holder is movable and the sample can be moved according to the laser shot.

As described above, when a mechanism for moving the sample is incorporated in the chamber, since the sample holder is thermally distorted by the heater, the temperature is controlled carefully. Further, since dust is generated by the sample transfer mechanism, the maintenance in the chamber is troublesome.

FIG. 6A shows a state of another doping treatment apparatus of the present invention. That is, the chamber 601 is provided with a window 602 made of anhydrous quartz glass. Unlike the case of the third embodiment, this window is wide enough to cover the entire surface of the sample 604. The chamber has an exhaust system 607,
And a gas system 608 for introducing a reactive gas is connected. In addition, a sample holder 605 is provided in the chamber, and a sample 604 is placed thereon, and the sample holder has a built-in heater. The sample holder is fixed to the chamber. A chamber base 601a is provided at the lower portion of the chamber, and laser irradiation is sequentially performed by moving the entire chamber in accordance with a laser pulse. The laser beam has an elongated shape, as in FIG. For example, it was a rectangle of 5 mm × 100 mm. As in FIG. 5, the position of the laser beam is fixed. In FIG. 6, unlike FIG. 5, a mechanism for moving the entire chamber is adopted. Therefore, there is no mechanical part in the chamber, and dust and the like are not generated, so that maintenance is easy. Further, the transfer mechanism is hardly affected by the heat of the heater.

The example of FIG. 6 is superior not only in the above points but also in the following points as compared with the example of FIG. That is, in the method of FIG. 5, laser irradiation could not be performed until the sample was placed in the chamber and then evacuated to a sufficient degree of vacuum. That is, there was a lot of dead time. However, in the example of FIG. 6, if a number of chambers as shown in FIG. 6A are prepared and rotated in order such as sample loading, vacuum evacuation, laser irradiation, and sample removal, respectively, No dead time occurs. Such a system is shown in FIG.

In other words, the chambers 617 and 616 containing the unprocessed sample are moved to the gantry 619 having a stage that can be accurately moved by the continuous transfer mechanism 618 during the exhaust process. A laser beam emitted from a laser device 611 and processed by appropriate optical devices 612 and 613 is irradiated onto a sample in the chamber 615 on the stage through a window. By moving the stage, the chamber 614 to which the necessary laser irradiation has been performed is sent again to the next stage by the continuous transfer mechanism 620, during which the heater in the chamber is turned off and exhausted, and the temperature is sufficiently high. After lowering, the sample is taken out.

As described above, in this embodiment, the continuous processing can be performed, so that the exhaust waiting time can be reduced and the throughput can be improved. Of course, in the case of FIG. 6, although the throughput is improved, a larger number of chambers are required than in the case of FIG. 5, so it should be carried out in consideration of the mass production scale and the investment scale.

As described above, in the examples of FIGS. 5 and 6, the shape of the laser beam is an elongated linear rectangle.
Of course, it may be rectangular or square. In this case, as shown in FIG. 7, a method of dividing a substrate such as a semiconductor wafer into an appropriate number of regions (32 in FIG. 7) and sequentially irradiating the laser may be adopted. . For example, the laser repetition frequency is 200H
If z, the time for processing one place on the wafer is 0.1 second, and the time for processing one wafer is considered even when the time for the wafer to move up, down, left and right (arrows in FIG. 7) is taken into consideration. Is 1
Less than 0 seconds. If the wafers are automatically conveyed, 200 or more wafers can be processed per hour. This productivity is not inferior to the conventional method.

Regarding similar laser doping processing apparatuses, Japanese Patent Application Nos. 3-283978 (filed on Oct. 4, 1991), 3-290719 (filed on Oct. 8, 1991), and 4-100.
479 (filed on March 26, 1991). According to the present invention, for example, a device having a channel length of 0.5 μm or less can be manufactured with good reproducibility, and the depth is 0.1 μm.
A diffusion region (impurity region) of m or less can be formed. On the other hand, the present invention has a feature in forming a device under such conditions. The following examples illustrate the invention in more detail.

According to the present invention, a MOS having a channel length of 1.0 μm or less, typically 0.1 to 0.3 μm
The device was stably manufactured, and a shallow impurity region having a depth of 0.1 μm or less could be manufactured. In the above embodiment, the semiconductor element is formed on single crystal silicon, but it goes without saying that the element using polycrystalline silicon or the like may be similarly applied. Thus, the present invention is industrially useful.

The effect of the present invention will be conceptually described. The problems of the prior art will be described. The conceptual diagram of the semiconductor processing (impurity doping) apparatus of this invention is shown. The conceptual diagram of the semiconductor processing (impurity doping) apparatus of this invention is shown. An example of a semiconductor processing (impurity doping) apparatus of the present invention is shown. An example of a semiconductor processing (impurity doping) apparatus of the present invention is shown. The example of the laser irradiation method of this invention is shown. The example of the manufacturing method of the semiconductor element using this invention is shown. The example of the manufacturing method of the semiconductor element using this invention is shown. The example of the manufacturing method of the semiconductor element using this invention is shown.

Using the present invention, a CMOS circuit was formed on a single crystal silicon substrate. The manufacturing procedure is shown in FIG. First, (100) of the single crystal silicon substrate 701
A field insulator 702 was formed on the surface by a so-called LOCOS method, and boron was thermally diffused in a part of the region not covered with the field insulator to form a P-type well 703. In this state, a region other than the P-type well is covered with a mask material 704, and diborane (B
₂ H ₆ ) in an atmosphere containing 2% by volume.
Boron was diffused in the region up to nm to form a P ⁺ region 705. (Fig. 8 (A))

In this case, the mask material 704 is preferably a material having good laser resistance, but is not necessarily opaque to the laser beam. For example, silicon nitride or silicon oxide satisfies the above conditions. A carbon film may also be used.

Laser doping was performed using the apparatus shown in FIG. In the apparatus shown in FIG.
In a B ₂ H ₆ / Ar atmosphere, boron (B) was doped by irradiating a laser beam without heating the sample. The laser is a KrF excimer laser (wavelength 248 nm, pulse width 2
Using the 0 nsec), with an energy density of 150~350mJ / cm ^2, it was subjected to irradiation of 2 to 20 shots per location. At this time, the temperature of the sample is below room temperature, preferably-
When the temperature is lowered to 50 ° C., the diffusion of impurities is suppressed, and the P ⁺ region 70 doped with impurities is added.
The depth of 5 can be made shallower. However, it is not preferable to lower the temperature to below the condensation point or boiling point of diborane.

Thereafter, the same operation was performed on the surface of the silicon substrate, and phosphorous doping was performed using phosphine to form an N ⁺ region 706. Thereafter, a gate oxide film 707 and gate electrodes 708 and 709 were formed as in the conventional case.
(Fig. 8 (B))

Thereafter, the area of the P-channel TFT (right side of the figure) is covered with the mask material 710, and again, FIG.
Doping was performed using the laser doping apparatus shown in FIG. At this time, phosphine was used as an impurity gas, and the substrate temperature was further heated to 200 to 450 ° C. The laser energy and the number of shots were within the range of the previous conditions. At this time, since the sample is heated, the diffusion is larger than that in the previous doping, and the source and drain regions 711 are deeply doped with phosphorus and become N-type. On the other hand, in the region below the gate electrode, the gate insulating film and the gate electrode serve as a mask so that the laser is not irradiated and doping is not performed.
^{+ Remains a} type. Typical doping conditions are as follows. (Fig. 8 (C))
Atmosphere PH ₃ 5% concentration (H ₂ dilution)
Sample temperature 350 degrees Pressure 0.02 to 1.00 Tor
r laser KrF excimer laser (wavelength 248nm)
Energy density 150 to 350 mJ / cm ² Number of pulses 10 shots

Similarly, by performing laser doping in a diborane atmosphere on a P-channel TFT (right side in the figure), a P-type region can be formed and a P-channel TFT can be formed.

Thereafter, an interlayer insulator 712 is formed in the same manner as in the prior art, a contact hole is provided, and an electrode
A wiring 713 was formed. Needless to say, the electrode / wiring material may be a single-layer metal or semiconductor film or a multilayer film such as titanium nitride and aluminum.

The transistor of this embodiment is a so-called belly channel type in which the surface of the channel formation region is not inverted even when a signal is applied to the gate, and a deeper region becomes a channel. For this reason, the gate insulating film is hardly broken by hot electrons or the like, and the reliability is improved.

In the present embodiment, the laser doping method is used when forming the buried channel. In addition, for example, the present invention can be used for the purpose of threshold voltage control. It will be clear from the description.

By using the present invention, a MOS device having a floating gate, for example, EPROM, E
An example in which an EPROM and a flash memory are manufactured is shown in FIG. First, the field insulator 751 is selectively formed on the (100) plane of the single crystal silicon substrate, and the gate electrode portion 752 is further formed.
, 753. A detailed structure of the gate electrode portion is shown in FIG. Where 7
61 is a gate oxide film, 762 is a polysilicon floating gate doped with phosphorus,
763 is a control gate made of polysilicon doped with phosphorus, and 764 is an insulating film covering them.
Preferably, the insulating film 764 is made of an oxide of a control gate and a floating gate. In order to oxidize these, an anodic oxidation method or a thermal oxidation method may be used.
The width of the gate electrode portion was 0.5 μm. When the anodic oxidation method is employed, two methods, wet or dry, are used, and for these, Japanese Patent Application No. 3-278705 (filed on September 30, 1991) and thermal oxidation are used. Japanese Patent Application No. 3-278706 (Heisei 3
The method described in the application filed on Sep. 30, 2010 may be used.

Thereafter, a mask material 754 is selectively formed, phosphorus is implanted into the silicon substrate by an ion implantation method using the mask material and the gate electrode portion as a mask, heated and diffused,
An N-type region 755 was formed. This N-type region was made to have a depth of about 0.2 μm. Further, as shown in FIG. 9A, the impurity region 755 formed at this time extends around the lower portion of the gate electrode portion.

Next, as shown in FIG. 9B, phosphorus-doped polysilicon wiring 756 is formed and used as a word line. However, if the resistance of the impurity region 755 is sufficiently small,
The impurity region 755 can be used as a word line without providing such polysilicon.

Furthermore, according to the present invention, phosphorous laser doping treatment is performed, and shallow (depth˜5
0 nm) impurity regions 757 and 758 were formed. In this example, doping of impurities was performed using the apparatus shown in FIG. As shown in FIG. 6 (B), a number of chambers (614 to 615) containing one wafer were flowed and irradiated with laser light. Typical doping conditions are as follows.
Atmosphere PH ₃ 5% concentration (H ₂ dilution)
Sample temperature Room temperature Pressure 0.02 to 1.00 Torr
Laser KrF excimer laser (wavelength 248nm)
Energy density 150 to 350 mJ / cm ² Number of pulses 10 shots

Through the above steps, a shallow impurity region was formed. Further, an interlayer insulator 759 was deposited by a conventional method, and contact holes and metal electrodes / wirings 760 and 761 were formed to form elements. In FIG. 9D, two EEPROM elements are described, and the wiring 7
60 and 761 are the respective bit lines.

In this embodiment, the shape of the impurity region is different on the left and right of the gate electrode portion. That is,
One is a deep impurity region 755 that wraps around to the bottom of the gate electrode, and the other is a shallow impurity region 757 in which there is no overlap at all, but rather an offset region is formed due to the oxide of the gate electrode portion. . The actual wraparound is 50 nm or less. As a result, when carriers are injected into the floating gate, they are injected from deep impurity regions as indicated by arrows in FIG.

FIG. 10 shows an example in which a MOSFET using a low concentration drain (LDD) structure is manufactured using the present invention. First, a field insulator 802 is formed on a single crystal silicon substrate 801 by a conventional method, and a gate insulating film 803 and a gate electrode 804 are deposited. Then, using the laser doping method of the present invention, phosphorus was doped to form a shallow (depth 50 nm) low-concentration N ⁻ -type impurity region 805.
(Fig. 10 (A))

Thereafter, a silicon oxide film 806 was deposited (FIG. 10B) and removed by anisotropic etching leaving the side wall portion 807 of the gate electrode. In this state, high concentration phosphorus ions were implanted by ion implantation to form an N ⁺ region 808. At this time, ahead of the N ^-
In the region 805, only the lower part of the side wall remains, and the LDD region 809 is formed. (Fig. 10 (C))

Finally, an interlayer insulator 810 and metal electrodes / wirings 811 were formed to complete the device. In this example, the LDD was formed by combining the conventional method and the doping method of the present invention. For example, Japanese Patent Application No. 3-238710 (filed on Aug. 26, 1991), which is an application of the present inventors. ,
Japanese Patent Application No. 3-238711 (filed on August 26, 1991)
Japanese Patent Application No. 3-238712 (filed on Aug. 26, 1991) may be used.

101 Substrate 102, 103 Diffusion region (source, drain)
104 Gate insulating film 105 Gate electrode 201 Substrate 202, 203 Diffusion region (source, drain)
204 Gate insulating film 205 Gate electrode

Claims (1)

A semiconductor including a first impurity region, a second impurity region, and a channel formation region formed between the first impurity region and the second impurity region;
A floating gate formed on the channel formation region; a control gate; an insulating film covering the floating gate and the control gate;
An interlayer insulating film formed on the semiconductor and the insulating film;
A wiring connected to the second impurity region through a contact hole formed in the interlayer insulating film,
The first impurity region overlaps the floating gate;
The second impurity region has no overlap with the floating gate,
The semiconductor device, wherein the second impurity region has a depth of 50 μm or less and a depth shallower than that of the first impurity region and is 0.1 μm or less.

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