JP2001203355A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having shallow impurity regions. SOLUTION: The semiconductor device comprises a semiconductor having first and second impurity regions and channel forming regions and gate electrode parts on the channel forming regions. The first impurity regions overlap the gate electrode parts, the depth of the second impurity region is less than that of the first impurity region and is 0.1 μm or less and the length of the channel forming region is 0.3 μm or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for performing a doping process in a process for manufacturing a semiconductor device such as a semiconductor integrated circuit, and a semiconductor device (element) manufactured by the above-described technology.

[0002]

2. Description of the Related Art Conventionally, a thermal diffusion method and an ion implantation method have been known as doping techniques. The thermal diffusion method is a method in which impurities are diffused into a semiconductor in a high-temperature atmosphere of 500 to 1200 degrees. The ion implantation method is a method in which ionized impurities are accelerated by an electric field and implanted into a predetermined place. However, in the ion implantation method, the crystal structure is remarkably destroyed by high-energy ions, the amorphous state or a state close to the amorphous state is obtained, and the electrical characteristics are remarkably deteriorated. In the ion implantation method, it is easier to control the impurity concentration than in the thermal diffusion method.
It has become an indispensable technology for manufacturing SI.

[0003]

However, the ion implantation method is not without its problems. The biggest problem has been the difficulty in controlling the diffusion of the implanted ions. This is especially true when the design rule is 0.5μ.
This is a major problem for so-called quarter-micron devices of less than m. In recent years, it has been required to form a shallow diffusion region (diffusion region) in which impurities are diffused. However, it is difficult to form a diffusion region having a depth of 0.1 μm or less with good reproducibility by ion implantation. there were. The above points will be described with reference to FIG.

[0004] The first problem is that ions implanted into a semiconductor are diffused in the lateral direction by secondary scattering due to ion implantation, and are thermally expanded to the surroundings by a heat treatment process. For.
Such an effect depends on the design rule (typically MOS
When the width of the gate electrode of the FET was 1.0 μm or more, there was almost no problem. However, below that, the diffusion portion due to the above-described effect caused the width of the gate electrode to be smaller than that of the gate electrode as shown in FIG. As a result, the gate electrode 205 and the diffusion regions (source and drain) 202 and 203 are geometrically overlapped. Such an overlap causes a parasitic capacitance between the gate electrode, the source, and the drain, and lowers the operation speed.

[0005] The second problem can be roughly divided into two.
One effect is due. One is the effect of diffusion due to thermal factors as pointed out in the first problem. For this reason,
It is difficult to make the thickness of the diffusion region 0.1 μm or less.
Another effect is remarkable when the semiconductor is crystalline, but is an effect of channeling in ion implantation. This is an effect that, when the light is perpendicularly incident on the crystal plane, the ions reach the deep part of the substrate because the ions are not scattered at all.

Conventionally, in order to avoid this channeling effect, ion implantation is performed with an inclination of several degrees with respect to the crystal plane. However, even with such a contrivance, the ions whose orbits are bent inside the semiconductor may meet the channeling conditions. Therefore, FIG.
As shown in FIG. 3B, ions enter deeply. In addition, when ions are implanted into a polycrystalline semiconductor, the crystal planes are random, and the depths of the ions are completely different.

There is another problem when using a polycrystalline semiconductor. That is, in a polycrystalline semiconductor, thermal diffusion of a doped impurity tends to progress through a grain boundary of a crystal, and therefore, as shown in FIG. 2C, doping cannot be performed uniformly. These problems have been difficult to solve by the conventional methods of ion implantation and recrystallization by heat treatment. Of course, the thermal diffusion method could not solve the problem at all.

The problems to be solved by the present invention are summarized as follows. That is, firstly, diffusion of impurities in the lateral direction is prevented, and secondly, the depth of the diffusion is controlled to be 0.1 μm or less, preferably 50 nm or less. An object of the present invention is to provide a method for solving at least one of these two problems in a part or all of a single crystal or a polycrystal or a semiconductor material equivalent thereto. By satisfying the above conditions, a MOS device having a channel length of 1.0 μm or less, typically 0.1 to 0.3 μm can be manufactured stably.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a high-purity reactive gas (impurity gas) containing an impurity imparting a conductivity type to a semiconductor, and a hydrogen-, fluorine-, helium-containing reactive gas. The sample semiconductor is doped with impurities by irradiating the surface of the sample semiconductor with pulsed laser light in an atmosphere diluted with a relatively stable gas such as argon. In this method, the impurity gas in the vicinity is decomposed or reacts with the semiconductor surface on the semiconductor surface heated instantaneously by laser irradiation, and only a very thin portion of the semiconductor surface is doped with the impurity. The thickness depends on the temperature at which the surface of the semiconductor is held, but can be 0.1 μm or less.

In such a reaction, thermal diffusion can be substantially eliminated by setting the pulse width of the laser beam to 1 μsec or less, preferably 100 nsec or less. Further, in the present invention, there is no channeling or secondary scattering which has become a problem in ion implantation.
Therefore, as shown in FIG. 1A, an extremely ideal diffusion region is formed, and the impurity concentration distribution in the depth direction is concentrated only at the required depth as shown in FIG. The distribution of impurities in the depth direction in the impurity regions formed in the semiconductor is shown by a distribution curve 106.
Although there is strictly lateral diffusion, its size is typically less than 50 nm and is negligible in real devices.

Further, even in a semiconductor material having a grain boundary, since there is no thermal influence, the diffusion region is not affected by the grain boundary as shown in FIG. In addition, in the present invention, since a non-thermal equilibrium state of heating by a pulsed laser is used, high-concentration impurity diffusion, which has been impossible in the related art, is possible.

In the present invention, a desired value of the impurity concentration can be obtained by adjusting the energy of the laser, the concentration of the impurity gas in the atmosphere, the semiconductor surface temperature, and the like. In the present invention, the semiconductor surface to which the impurity is to be diffused may be exposed or covered with another film. When covered with another film, impurities are blocked by the chemical and physical properties of the film, and as a result, the diffusion concentration and the diffusion depth in the semiconductor are controlled.

The impurity in the present invention is a trivalent impurity, typically B (boron) or the like, when a silicon semiconductor (silicon) is used as a semiconductor and P-type is to be imparted. Pentavalent impurities, typically P (phosphorus) or As
(Arsenic) or the like can be used. As a reactive gas containing these impurities, AsH ₃ , PH ₃ , BF ₃ ,
BCl ₃ , B (CH ₃ ) _{3 and the} like can be used.

As a semiconductor, in addition to a conventional wafer-like single-crystal silicon semiconductor, an amorphous silicon semiconductor thin film formed by a vapor phase growth method, a sputtering method, or the like is generally used for manufacturing a TFT. Used for Further, the present invention can be applied to a polycrystalline or single-crystal silicon semiconductor manufactured over an insulating substrate by liquid phase growth. Further, it is needless to say that the semiconductor is not limited to the silicon semiconductor, and may be another semiconductor.

It is useful to use a pulse oscillation type excimer laser device as the laser beam. this is,
This is because in the pulsed laser, the heating of the sample is instantaneous and is limited only to the surface, and does not affect the substrate. Heating with a continuous wave laser cannot achieve the above-mentioned non-thermal equilibrium state, and is a local heating. It may peel off. In this regard, in the pulse laser, the thermal relaxation time is overwhelmingly smaller than the reaction time of mechanical stress such as thermal expansion, and does not cause mechanical damage.

In particular, excimer laser light is ultraviolet light, is efficiently absorbed by many semiconductors such as silicon, and has a short pulse duration of 10 nsec.
Excimer lasers have already been used in experiments in which an amorphous silicon thin film is crystallized by laser irradiation to obtain a highly crystalline polycrystalline silicon thin film. The specific type of laser is ArF
Excimer laser (wavelength 193 nm), XeCl excimer laser (wavelength 308 nm), XeF excimer laser (wavelength 351 nm), KrF excimer laser (24
8 nm) or the like is appropriate.

In the present invention, the semiconductor surface may be heated or cooled. Since the diffusion of impurities can be promoted or suppressed by controlling the temperature of the semiconductor surface, those who carry out the present invention perform temperature control to obtain the target impurity concentration and diffusion depth. It is recommended.

In the present invention, in order to promote the decomposition of the impurity gas, it is also effective to convert the impurity gas into plasma using DC or AC electric energy. The electromagnetic energy applied for this purpose is 13.5
High frequency energy of 6 MHz is common. Due to the decomposition of the doping gas by the electromagnetic energy, doping can be efficiently performed even when a laser beam that cannot directly decompose the doping gas is used. The type of the electromagnetic energy is not limited to the frequency of 13.56 MHz. For example, if a microwave of 2.45 GHz is used, a higher activation rate can be obtained. Further, an ECR condition generated by an interaction between a microwave of 2.45 GHz and a magnetic field of 875 Gauss may be used. It is also effective to use light energy that can directly decompose the doping gas.

FIGS. 3 and 4 are conceptual diagrams of the apparatus of the present invention. FIG. 3 shows an apparatus provided with a substrate heating device, and FIG. 4 shows an apparatus provided with an electromagnetic device for generating plasma in addition thereto. Since these drawings are conceptual, it goes without saying that in an actual device,
Other components may be provided as necessary. Hereinafter, the method of use will be outlined.

In FIG. 3, a sample 304 is set on a sample holder 305. First, the chamber 301 is evacuated by an exhaust system 307 connected to an exhaust device. In this case, it is desirable to evacuate to as high a vacuum as possible. That is, atmospheric components such as carbon, nitrogen, and oxygen are generally not preferable for semiconductors. Such an element is taken into the semiconductor, but may reduce the activity of the impurity added at the same time. In addition, it impairs the crystallinity of the semiconductor and causes dangling bonds at grain boundaries. Therefore, it is desired to evacuate the inside of the chamber to 10 ^-6 torr or less, preferably 10 ^-8 torr or less.

It is also desirable to operate the heater 306 before and after the exhaust to drive out the atmospheric components adsorbed inside the chamber. As used in current vacuum equipment, it is also desirable to provide a spare chamber in addition to the chamber so that the chamber does not directly contact the atmosphere. As a matter of course, it is desirable to use a turbo-molecular pump or a cryopump with less contamination of carbon or the like as compared with a rotary pump or an oil diffusion pump.

After exhausting sufficiently, a reactive gas is introduced into the chamber by the gas system 308. The reactive gas may be composed of a single gas, or may be diluted with hydrogen, argon, helium, neon, or the like. The pressure may be atmospheric pressure or lower. These are selected in consideration of the type of the target semiconductor, the impurity concentration, the depth of the impurity region, the substrate temperature, and the like.

Next, a laser beam 303 is passed through a window 302.
Is irradiated on the sample. At this time, the sample is heated to a certain temperature by the heater. The laser beam is usually applied to one place at about 1 to 50 pulses. In a state where the energy variation of the laser pulse is extremely large,
When the number of pulses is too small, the probability of occurrence of a defect is large. On the other hand, irradiating too many pulses to one location is not desirable in terms of mass productivity (throughput). According to the knowledge of the present inventor, the above pulse number was appropriate from the viewpoint of mass productivity and the yield.

In this case, for example, when the pulse of the laser is 10
In the case of a specific rectangular shape of mm (x direction) × 30 mm (y direction), a laser pulse is applied to the same region by 1 mm.
A method of irradiating 0 pulses and moving to the next portion after the end may be adopted, but the laser may be moved by 1 mm in the x direction per pulse.

When the laser irradiation is completed, the inside of the chamber is evacuated, the sample is cooled to room temperature, and the sample is taken out. Thus, in the present invention, the doping process is extremely simple and fast. That is, in the case of a conventional ion implantation process, three steps of (1) formation of a doping pattern (resist coating, exposure, development), (2) ion implantation (or ion doping), and (3) recrystallization are required. Was. However, the present invention is completed in two steps of (1) formation of a doping pattern (resist coating, exposure, and development) and (2) laser irradiation.

The apparatus shown in FIG. 4 is almost the same as the apparatus shown in FIG. First, the exhaust system 407 is set inside the chamber 401.
And a reactive gas is introduced from the gas system 408. Then, the sample 404 on the sample holder 405 is irradiated with laser light 403 through the window 402. Then high frequency or alternating current (or direct current)
Power is supplied from the power supply 410 to the electrode 409 to generate plasma or the like inside the chamber, thereby activating the reactive gas. In the figure, the electrodes are shown as a capacitive coupling type, but may be an inductive (inductance) coupling type. Furthermore, the sample holder may be used as one electrode even if it is a capacitive coupling type. Further, at the time of laser irradiation, the sample may be heated by the heater 406.

FIG. 5 shows another doping apparatus according to the present invention. That is, a slit-shaped window 502 made of anhydrous quartz glass is provided in the chamber 501. The laser light is shaped into an elongated shape in accordance with the window. The laser beam is, for example, 10 mm × 300
mm. Note that the position of the laser beam is fixed. An exhaust system 507 and a gas system 508 for introducing a reactive gas are connected to the chamber.
A sample holder 505 is provided in the chamber, a sample 504 is placed thereon, and an infrared lamp (functioning as a heater) 506 is provided below the sample holder.
Is provided. The sample holder is movable and can move the sample in accordance with the laser shot.

As described above, when the mechanism for moving the sample is incorporated in the chamber, the thermal expansion of the sample holder caused by the heater causes a disorder, so that extreme care is required for temperature control. . In addition, since dust is generated by the sample transfer mechanism, maintenance in the chamber is troublesome.

FIG. 6A shows the state of another doping apparatus according to the present invention. That is, a window 602 made of anhydrous quartz glass is provided in the chamber 601. Unlike the case of the third embodiment, this window is wide enough to cover the entire surface of the sample 604. The chamber has an exhaust system 60
7, and a gas system 608 for introducing a reactive gas. Further, a sample holder 605 is provided in the chamber, and a sample 604 is placed thereon,
The sample holder has a built-in heater. The sample holder is fixed to the chamber. A chamber base 601a is provided at a lower portion of the chamber, and laser irradiation is sequentially performed by moving the entire chamber in accordance with a laser pulse. The laser beam has an elongated shape as in the case of FIG. For example, it was a rectangle of 5 mm × 100 mm. As in FIG. 5, the position of the laser beam is fixed. In FIG. 6, unlike FIG. 5, a mechanism for moving the entire chamber is employed. Therefore, there is no mechanical part in the chamber and no dust or the like is generated, so that maintenance is easy. Further, the transfer mechanism is hardly affected by the heat of the heater.

The example of FIG. 6 is superior to the example of FIG. 5 not only in the above points, but also in the following points. That is, in the method shown in FIG. 5, after the sample was put in the chamber, laser emission could not be performed until the sample was evacuated to a sufficient degree of vacuum. That is, there were many dead times. However, in the example of FIG. 6, a large number of chambers as shown in FIG. 6A are prepared, and each of them is sequentially rotated in the order of sample loading, evacuation, laser irradiation, and sample removal, as described above. No dead time occurs. Such a system is shown in FIG.

That is, the chambers 617 and 616 containing the unprocessed sample are directed by the continuous transfer mechanism 618 to the gantry 619 having a stage capable of precise movement during the evacuation process. Chamber 6 on stage
At 15, the laser light emitted from the laser device 611 and processed by the appropriate optical devices 612 and 613 is irradiated to the sample inside through the window. By moving the stage, the required laser irradiation chamber 6
14 is again sent to the next stage by the continuous transport mechanism 620, during which the heater in the chamber is turned off, evacuated and, after the temperature has fallen sufficiently, the sample is removed.

As described above, in the present embodiment, continuous processing can be performed, so that the waiting time for exhaust can be reduced and the throughput can be improved. of course,
In the case of FIG. 6, although the throughput is improved, a larger number of chambers are required than in the case of FIG. 5, so that it should be carried out in consideration of the mass production scale and investment scale.

As described above, in the examples of FIGS. 5 and 6, the shape of the laser beam is an elongated linear rectangle.
It may be rectangular or square. In this case, as shown in FIG. 7, a method of dividing a substrate such as a semiconductor wafer into an appropriate number of regions (32 in FIG. 7) and sequentially irradiating a laser may be adopted. . For example, if the repetition frequency of the laser is 200 Hz, the processing time for one location on the wafer is 0.1 second, and the time required for the wafer to move up, down, left, and right (arrows in FIG. 7) is 1 second. The processing time for one wafer is less than 10 seconds. If the wafer is automatically transferred, 20
Zero or more wafers can be processed. This productivity is not inferior to the conventional method.

Regarding the same laser doping apparatus, Japanese Patent Application Nos. 3-283981 (filed on Oct. 4, 1991), 3-290719 (filed on Oct. 8, 1991), and 4-100479 (Filed on March 26, 1991). According to the present invention, for example, a device having a channel length of 0.5 μm or less can be manufactured with good reproducibility, and a diffusion region (impurity region) having a depth of 0.1 μm or less can be formed. On the contrary, the present invention has advantages in forming a device under such conditions. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0035]

EXAMPLES Example 1 A CMOS circuit was formed on a single crystal silicon substrate by using the present invention. FIG. 8 shows the manufacturing procedure. First, (10) of the single crystal silicon substrate 701
On the 0) plane, a field insulator 702 was formed by a so-called LOCOS method, and further, boron was thermally diffused in a part of a region not covered with the field insulator to form a P-type well 703. In this state, a region other than the P-type well is covered with a mask material 704, and diborane (B
The ₂ H ₆₎ in an atmosphere containing 2 vol%, and the laser irradiation, the region from the surface of the P-type well to 50 nm, diffuse boron to form a region 705 of P ^+. (FIG. 8
(A))

In this case, as the mask material 704, a material having good laser resistance is preferable, but it is not necessary to be opaque to laser light. For example, silicon nitride and silicon oxide satisfy the above conditions. Further, a carbon film may be used.

Laser doping was performed using the apparatus shown in FIG. In the apparatus shown in FIG. 5, B ₂ H ₆ /
In an Ar atmosphere, the sample was irradiated with a laser beam without being heated, and boron (B) was doped. Laser is K
rF excimer laser (wavelength 248 nm, pulse width 2
0 nsec), and irradiation was performed at an energy density of 150 to 350 mJ / cm ² for 2 to 20 shots per one place. At this time, when the temperature of the sample is lowered to room temperature or lower, preferably to −50 ° C., diffusion of impurities is suppressed, and the depth of the P ⁺ region 705 doped with impurities can be reduced. However, it is not preferable to lower the temperature below the freezing point or boiling point of diborane.

Thereafter, the same operation was performed on the surface of the silicon substrate, and N ⁺ regions 706 were formed by doping phosphorus with phosphine. Thereafter, the gate oxide film 707 and the gate electrode 70 are formed as in the conventional case.
8 and 709 were formed. (FIG. 8 (B))

Thereafter, the region of the P-channel TFT (right side in the figure) was covered with a mask material 710, and doping was performed again using the laser doping apparatus shown in FIG. At this time, phosphion was used as an impurity gas, and the substrate temperature was further increased to 200 to 450 ° C.
The energy of the laser and the number of shots were within the range of the above conditions. At this time, since the sample is heated, the diffusion is larger than that in the previous doping, and the source and drain regions 711 are deeply doped with phosphorus to be N-type. On the other hand, the region below the gate electrode is not irradiated with the laser using the gate insulating film and the gate electrode as a mask, is not doped, and remains N ⁺ -type. Typical doping conditions are as follows. (FIG. 8C) Atmosphere PH ₃ 5% concentration (H ₂ dilution) Sample temperature 350 degrees Pressure 0.02 to 1.00 Torr Laser KrF excimer laser (wavelength 248 nm) Energy density 150 to 350 mJ / cm ² Number of pulses 10 shots

Similarly, a P-channel type TFT (right side in the figure)
Also, by performing laser doping in a diborane atmosphere, a P-type region was formed, and a P-channel TFT could be formed.

Thereafter, an interlayer insulator 712 is formed as in the conventional case, a contact hole is provided, and an electrode / wiring 713 is formed.
Was formed. It goes without saying that the material of the electrodes and wirings may be a single-layer metal or semiconductor film, or a multilayer film such as titanium nitride and aluminum.

The transistor of this embodiment is of a so-called buried channel type in which the surface of the channel forming region does not reverse even when a signal is applied to the gate, and the deeper region becomes the channel. Therefore, the gate insulating film is less likely to be broken by hot electrons or the like, and the reliability has been improved.

In this embodiment, a laser doping method is used to form the buried channel. However, it is also possible that the present invention can be used for controlling a threshold voltage. It will be clear from the description of the embodiments.

Embodiment 2 By using the present invention, a MOS device having a floating gate, for example, an EPRO
FIG. 9 shows an example in which M, EEPROM, and flash memory are manufactured. First, a field insulator 751 is selectively formed on a (100) plane of a single crystal silicon substrate, and gate electrode portions 752 and 753 are formed. A detailed structure of the gate electrode portion is illustrated in FIG. Here, 761
Is a gate oxide film, 762 is a phosphorus-doped polysilicon floating gate, 763 is a phosphorus-doped polysilicon control gate, and 764 is an insulating film covering them. Preferably, this insulating film 764 is formed of an oxide of a control gate and a floating gate. To oxidize these, an anodic oxidation method or a thermal oxidation method may be used. The width of the gate electrode is 0.
The thickness was 5 μm. In the case of employing the anodic oxidation method, two methods, a wet method and a dry method, are used. These methods are described in Japanese Patent Application No. 3-278705 (filed on September 30, 1991). , Japanese Patent Application No. 3-2
78706 (filed on September 30, 1991).

Thereafter, a mask material 754 is selectively formed, and the mask material and the gate electrode portion are used as a mask.
Phosphorus was implanted into a silicon substrate by an ion implantation method, and was diffused by heating to form an N-type region 755.
This N-type region was set to have a depth of about 0.2 μm. Further, as shown in FIG. 9A, the impurity region 755 formed at this time extends around the lower portion of the gate electrode portion.

Next, as shown in FIG. 9B, a wiring 756 made of polysilicon doped with phosphorus was formed and used as a word line. However, when the resistance of the impurity region 755 is sufficiently small, the impurity region 755 can be used as a word line without providing such polysilicon.

Further, according to the present invention, laser doping of phosphorus was performed to form shallow (depth to 50 nm) impurity regions 757 and 758. In this embodiment, doping of impurities was performed using the apparatus shown in FIG. As shown in FIG. 6 (B), a large number of chambers (614 to 615) each containing a single wafer were flowed, and the wafer was irradiated with laser light. Typical doping conditions are as follows. Atmosphere PH ₃ 5% concentration (H ₂ dilution) Sample temperature Room temperature Pressure 0.02 to 1.00 Torr Laser KrF excimer laser (wavelength 248 nm) Energy density 150 to 350 mJ / cm ² Number of pulses 10 shots

Through the above steps, a shallow impurity region was formed. Further, the interlayer insulator 7 is formed by a conventional method.
59, and a contact hole and a metal electrode / wiring 76
0 and 761 were formed to form an element. FIG. 9D shows two EEPROM elements, and the wiring 7
60 and 761 are the respective bit lines.

In this embodiment, the shape of the impurity region is different between the left and right sides of the gate electrode portion. That is, one is a deep impurity region 755 extending to the lower portion of the gate electrode, and the other is a shallow impurity region 757 in which an offset region is formed due to oxide of the gate electrode portion without any overlap at all. It is. The actual wrap around is less than 50 nm. As a result, carriers are implanted into the floating gate from deep impurity regions as shown by arrows in FIG.

Embodiment 3 FIG. 10 shows an example in which a MOSFET using a low-concentration drain (LDD) structure is manufactured by using the present invention. First, a field insulator 802 is formed on a single crystal silicon substrate 801 by a conventional method, and a gate insulating film 803 and a gate electrode 804 are deposited. And, using the laser doping method of the present invention,
A shallow (50 nm deep) low-concentration N ⁻ -type impurity region 805 was formed by doping with phosphorus. (FIG. 10A)

Thereafter, a silicon oxide film 806 is deposited (FIG. 1).
0 (B)), which was removed by anisotropic etching except for the side wall portion 807 of the gate electrode. Then, in this state, high-concentration phosphorus ions were implanted by ion implantation to form an N ⁺ region 808. At this time, ahead of the N ^-
In the region 805, only the lower portion of the side wall remains, and the LDD region 809 is formed.
Was formed. (FIG. 10 (C))

Finally, an interlayer insulator 810 and metal electrodes / wirings 811 were formed to complete the device. In this embodiment,
By combining the conventional method and the doping method of the present invention, L
DD was formed, for example, as an application of the present inventors,
Japanese Patent Application No. 3-238710 (filed on August 26, 1991),
Japanese Patent Application No. 3-238711 (filed on August 26, 1991)
A method such as Japanese Patent Application No. Hei 3-238712 (filed on August 26, 1991) may be used.

[0053]

According to the present invention, a channel length of 1.0 μm
Hereinafter, typically, a MOS device of 0.1 to 0.3 μm can be stably manufactured, and a shallow impurity region having a depth of 0.1 μm or less can be manufactured. In the above embodiment, a semiconductor device on single crystal silicon has been described. However, it goes without saying that the same may be applied to a device using polycrystalline silicon or the like. Thus, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 conceptually explains the effect of the present invention.

FIG. 2 illustrates a problem of the related art.

FIG. 3 shows a conceptual diagram of a semiconductor processing (impurity doping) apparatus of the present invention.

FIG. 4 is a conceptual diagram of a semiconductor processing (impurity doping) apparatus of the present invention.

FIG. 5 shows an example of a semiconductor processing (impurity doping) apparatus of the present invention.

FIG. 6 shows an example of a semiconductor processing (impurity doping) apparatus of the present invention.

FIG. 7 shows an example of the laser irradiation method of the present invention.

FIG. 8 illustrates an example of a method for manufacturing a semiconductor element using the present invention.

FIG. 9 illustrates an example of a method for manufacturing a semiconductor element using the present invention.

FIG. 10 illustrates an example of a method for manufacturing a semiconductor element using the present invention.

[Explanation of symbols]

 Reference Signs List 101 substrate 102, 103 diffusion region (source, drain) 104 gate insulating film 105 gate electrode 201 substrate 202, 203 diffusion region (source, drain) 204 gate insulating film 205 gate electrode

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[Procedure amendment]

[Submission date] January 9, 2001 (2001.1.9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/115 H01L 29/78 371 29/29/788 29/792

Claims (20)

[Claims] 1. A semiconductor device including a semiconductor including a first impurity region, a second impurity region, and a channel formation region, and a gate electrode portion on the channel formation region, wherein the first impurity region is A part of the gate electrode part, a depth of the second impurity region is smaller than a depth of the first impurity region and 0.1 μm or less, and a length of the channel formation region is 0 μm. A semiconductor device having a thickness of 3 μm or less. 2. A semiconductor device including a semiconductor including a first impurity region, a second impurity region, and a channel formation region, and a floating gate and a control gate on the channel formation region, wherein the first impurity region is Overlaps a part of the floating gate with an insulating film interposed therebetween, wherein the depth of the second impurity region is smaller than the depth of the first impurity region and 0.1 μm or less; A semiconductor device, wherein the length of the region is 0.3 μm or less. 3. A semiconductor including one first impurity region, two second impurity regions, and two channel forming regions between the one first impurity region and the two second impurity regions, and A semiconductor device including a gate electrode portion on each of the two channel formation regions, wherein the first impurity region overlaps a part of the gate electrode portion, and a depth of the second impurity region. Is a depth smaller than the depth of the first impurity region and 0.1 μm or less, and the length of the channel formation region is 0.3 μm or less. 4. A semiconductor including one first impurity region, two second impurity regions, and two channel forming regions between the one first impurity region and the two second impurity regions, and A semiconductor device including a floating gate and a control gate on each of the two channel formation regions, wherein the first impurity region overlaps a part of the floating gate via an insulating film; The depth of the impurity region is smaller than the depth of the first impurity region and 0.1 μm or less; and the length of the channel formation region is 0.3 μm or less. 5. The semiconductor device according to claim 2, wherein said floating gate and said control gate are silicon films. 6. The semiconductor device according to claim 1, wherein said second impurity region is connected to a bit line. 7. The semiconductor device according to claim 1, wherein the semiconductor is crystalline silicon. 8. The semiconductor device according to claim 1, wherein the semiconductor is a semiconductor substrate. 9. A semiconductor device including a first impurity region, a second impurity region, and a semiconductor including a first channel formation region, and a first semiconductor device including a first gate electrode portion on the first channel formation region. A second semiconductor device including a semiconductor including the first impurity region, the third impurity region, and a second channel formation region, and a second gate electrode portion on the second channel formation region; And a depth of the second impurity region and a depth of the third impurity region are smaller than a depth of the first impurity region. 10. A semiconductor including a first impurity region, a second impurity region, and a first channel formation region, and a first floating gate and a first control gate on the first channel formation region. A first semiconductor device; a semiconductor including the first impurity region, the third impurity region, and a second channel formation region; and a second floating gate and a second control gate on the channel formation region. A second semiconductor device, wherein the depth of the second impurity region and the depth of the third impurity region are smaller than the depth of the first impurity region. 11. A semiconductor device including a first impurity region, a second impurity region, and a semiconductor including a first channel formation region, and a first semiconductor device including a first gate electrode portion on the first channel formation region. A second semiconductor device including a semiconductor including the first impurity region, the third impurity region, and a second channel formation region, and a second gate electrode portion on the second channel formation region; Wherein the first impurity region overlaps a part of the first gate electrode part and a part of the second gate electrode part, and the depth of the second impurity region and the third A depth of the impurity region is smaller than a depth of the first impurity region. 12. A semiconductor including a first impurity region, a second impurity region, and a first channel formation region, and a first floating gate and a first control gate on the first channel formation region. A first semiconductor device; a semiconductor including the first impurity region, the third impurity region, and a second channel formation region; and a second floating gate and a second control gate on the channel formation region. A second semiconductor device, wherein the first impurity region overlaps a part of the first floating gate and a part of the second floating gate, and a depth of the second impurity region. And a depth of the third impurity region is smaller than a depth of the first impurity region. 13. The first floating gate and the second floating gate, and the first control gate and the second floating gate according to claim 12,
Wherein the control gate is a silicon film. 14. The semiconductor device according to claim 9, wherein said second impurity region and said third impurity region are connected to a bit line. 15. The semiconductor device according to claim 9, wherein a depth of said first impurity region is 0.1 μm or less. 16. A semiconductor device according to claim 9, wherein said semiconductor is crystalline silicon. 17. The semiconductor device according to claim 9, wherein the semiconductor is a semiconductor substrate. 18. The semiconductor device according to claim 1, wherein said semiconductor device is an EPROM. 19. The semiconductor device according to claim 1, wherein said semiconductor device is an EEPROM. 20. The semiconductor device according to claim 1, wherein the semiconductor device is a flash memory.