JP2010045247A - Silicon wafer and method of manufacturing silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon wafer having the effective density and size of a BMD for preventing the dislocation of a pattern by restraining slip dislocation caused in a particularly controversial device heat treatment process accompanied by the fining of a device wiring pattern, and to provide a method for manufacturing the silicon wafer. <P>SOLUTION: In this silicon wafer, assuming an oxygen concentration variation before and after deposit heat treatment for depositing an oxygen deposit as &Delta;O<SB>i</SB>(atoms/cm<SP>3</SP>)(JEIDA) and the density of the oxygen deposit detected by an RIE method as D (a piece/cm<SP>3</SP>), a relationship of &Delta;O<SB>i</SB>/(D&times;10<SP>6</SP>)&le;5 and D&ge;1&times;10<SP>10</SP>is satisfied. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a silicon wafer and a manufacturing method thereof, and more particularly to a silicon wafer and a manufacturing method thereof that can suppress slip generated during heat treatment.

  A semiconductor integrated circuit substrate material, such as a silicon wafer, is generally manufactured through a process of cutting and polishing a silicon single crystal grown by a Czochralski method (hereinafter referred to as CZ method).

In the CZ method, polycrystalline silicon is melted in a quartz crucible, and the silicon melt is pulled up while rotating. Oxygen melted from the quartz crucible is usually about 5 to 20 × 10 ¹⁷ atoms / cm ^{3 in the} silicon crystal. Included in supersaturated state. These supersaturated oxygens precipitate inside the silicon wafer as oxygen precipitates (Bulk Micro Defect: hereinafter referred to as BMD) which are crystal defects during the heat treatment in the device manufacturing process.
When this precipitate is generated in the device active region, it adversely affects device characteristics such as a reduction in junction leakage. On the other hand, when this precipitate is generated in the wafer bulk region other than the device active region, it captures metal elements mixed during the device process. Effective because it functions as a gettering site.

Here, in recent years, a phenomenon called pattern shift (nonlinear shift) has occurred in the manufacturing process of semiconductor elements.
In an exposure process for manufacturing a semiconductor element, a plurality of circuit patterns are superimposed and transferred onto a silicon wafer. At this time, when a circuit pattern is exposed again after a plurality of steps to be described later, a phenomenon in which a positional deviation between the already formed circuit pattern and the newly formed circuit pattern occurs is called pattern deviation.
When the overlay accuracy between the respective layers is deteriorated due to this pattern shift, the characteristics of the formed circuit are deteriorated, resulting in a decrease in yield due to defects.

Possible causes of pattern deviation include the following.
For example, in process processes such as etching, CVD (Chemical Vapor Deposition), and CMP (Chemical Mechanical Polishing), the silicon wafer is often distorted due to thermal expansion during polishing or heat treatment in the process. Therefore, when exposure processing is performed on a layer that has undergone such process steps, the distortion of the silicon wafer may be affected by non-linear deviation, that is, pattern deviation.

  Also, in the semiconductor device manufacturing process, heat treatment such as IG (Intrinsic Gettering), LOCOS (Local Oxidation of Silicon), well drive, oxidation, etc. is performed at about 400 to 1200 ° C. using a diffusion furnace or RTA (Rapid Thermal Annealing) furnace. Performed in the temperature range.

In such a heat treatment, so-called slip dislocation occurs in which the crystal is deformed along the slip surface due to stress due to the weight of the silicon wafer or stress due to temperature non-uniformity in the silicon wafer surface.
This slip dislocation causes a step of several nanometers to several microns on the surface of the silicon wafer and crosses the active region of the device, thereby increasing the junction leakage current and remarkably deteriorating the overlay accuracy. For this reason, slip dislocation is one of the major causes of yield reduction. In recent years, with the increase in the diameter of silicon wafers, slip generated during heat treatment has become a more serious problem, and it is important to suppress the occurrence of slip dislocations.

  In particular, in recent advanced processes, processes such as SLA (Spike Lamp Anneal) or FLA (Flash Lamp Anneal) have been introduced to activate the ion-implanted impurities, and the distribution of impurities in the depth direction is narrow. In order to control, heat treatment is performed such that the temperature is raised to a predetermined temperature very rapidly and cooled rapidly. For this reason, the thermal stress acting on the silicon wafer is increased, and slip dislocation is more likely to occur.

As a method of suppressing the slip dislocation, there is a method of suppressing the movement of dislocation by BMD existing inside the silicon wafer (see, for example, Patent Document 1).
The method described in Patent Document 1 is the temperature at the end of the high temperature heat treatment temperature before performing high temperature heat treatment for 10 to 600 minutes at a temperature of 1100 to 1350 ° C. in an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof. By performing pre-annealing, oxygen precipitates are grown to suppress the growth of slip dislocations.

WO2003 / 3441

This suppression of dislocation by BMD is a phenomenon of precipitation strengthening in which fine precipitate particles act as resistance to dislocation movement. If the BMD has a certain density or more, it is possible to effectively suppress slip movement. On the other hand, when the BMD size exceeds a certain size, dislocation occurs from the precipitate itself, and a precipitation softening phenomenon occurs in which the strength decreases.
Further, there is a relationship in which the average size decreases as the density of BMD increases. This is probably because supersaturated oxygen or more is required inside the silicon wafer in order to grow BMD, but when the density of BMD is high, the number of oxygen atoms that can be consumed per BMD is reduced. . For this reason, the process which can increase a density is required, suppressing the number of oxygen atoms per BMD below a fixed level.

  The present invention has been made in view of the above-described problems, and is effective for suppressing slip dislocation generated in a device heat treatment process, which is particularly problematic with the miniaturization of device wiring patterns, and preventing pattern displacement. An object of the present invention is to provide a silicon wafer having a density and size of BMD and a method for manufacturing the same.

To solve the above problems, the present invention provides a silicon ^{_{wafer, ΔO i (atoms / cm 3}} ) the oxygen concentration variation in the precipitation heat treatment before and after precipitating the oxygen precipitates (JEIDA), RIE (Reactive Ion Etching; The relationship of ΔO _i / (D × 10 ⁶ ) ≦ 5 and D ≧ 1 × 10 ¹⁰ is satisfied when the density of oxygen precipitates detected by the reactive ion etching method is D (pieces / cm ³ ). A silicon wafer is provided (claim 1).

ΔO _i (atoms / cm ³ ) (JEIDA) is the amount of oxygen concentration change before and after the precipitation heat treatment for precipitating oxygen precipitates as described above, and the density of oxygen precipitates detected by the RIE method is D (pieces / cm ³ ). If it is a silicon wafer satisfying the relationship of ΔO _i / (D × 10 ⁶ ) ≦ 5 and D ≧ 1 × 10 ¹⁰ , a desired small size BMD exists in the silicon wafer at a high density. Thus, the slip dislocation movement can be effectively suppressed. That is, the silicon wafer can have high resistance to slip dislocations generated during the heat treatment in the manufacturing process of the semiconductor element, and the occurrence of pattern deviation can be prevented.

The silicon wafer preferably has a carbon concentration in a range of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA).
Thus, in the case of a silicon wafer having a carbon concentration of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA), grown-in precipitation using a carbon-oxygen complex as a nucleus before the precipitation heat treatment. Nuclei may be formed. For this reason, in the precipitation heat treatment, the nucleation is further promoted, the density is high, and it can be facilitated by the silicon wafer on which the BMD with a small number of oxygen atoms per one is formed. is there.

Further, the present invention is a method for producing a silicon wafer, in which a silicon semiconductor substrate is cut out from a silicon single crystal grown by the Czochralski method, subjected to precipitation heat treatment, and measured by the RIE method. When the density D of oxygen precipitates is 1 × 10 ¹⁰ (pieces / cm ³ ) or more and the amount of change in oxygen concentration before and after the precipitation heat treatment is ΔO _i (atoms / cm ³ ) (JEIDA), ΔO _i / (D × A method for producing a silicon wafer is provided, wherein an oxygen precipitate satisfying a relationship of 10 ⁶ ) ≦ 5 is deposited.

When the density D measured by the RIE method is 1 × 10 ¹⁰ (pieces / cm ³ ) or more and the amount of change in oxygen concentration before and after the precipitation heat treatment is ΔO _i (atoms / cm ³ ) (JEIDA), ΔO _i / (D × 10 ⁶ ) ≦ 5 Precipitation heat treatment for precipitating oxygen precipitates satisfying the relationship effectively suppresses the movement of slip dislocations generated in the device manufacturing process, particularly the RTA process, inside the silicon wafer. BMD of the density and size which can be made can be deposited. Therefore, it can be set as the silicon wafer which can suppress generating a pattern shift.

Moreover, as said precipitation heat processing, it is preferable to perform the 1st heat processing hold | maintained at 500-700 degreeC for 1 hour or more, and to perform 1000 degreeC or more 2nd heat treatment after that.
As a precipitation heat treatment for precipitating BMD effective in suppressing slip dislocation, a first heat treatment is performed at a temperature at which nucleation in a silicon wafer is relatively likely to occur, for example, at 500 to 700 ° C. for 1 hour or more, and then 1000 A step of performing a second heat treatment at a temperature of ° C or higher is effective.
As described above, the first heat treatment promotes nucleation in the silicon wafer by setting the temperature condition to facilitate nucleation. Furthermore, BMD can be precipitated in a silicon wafer by performing a high-temperature heat treatment in the above-described temperature range as a second heat treatment in order to precipitate oxygen.

Further, as the precipitation heat treatment, it is preferable to perform a heat treatment that is performed in a heat treatment furnace at 500 to 700 ° C., heated at a rate of 3 ° C./min or less, and held at 1000 ° C. or more and 1 hour or less. .
In this way, the silicon wafer is put into a heat treatment furnace at 500 to 700 ° C., and the temperature is gradually raised at a rate of 3 ° C./min or less, so that BMD precipitation nuclei are efficiently formed in the silicon wafer. And BMD effective for suppression of slip dislocation can be deposited by holding | maintaining at 1000 degreeC or more after that for 1 hour or less after that.

Also, performed just before the precipitation heat treatment, a rapid elevation heat treatment _furnace, N _2, NH 3, Ar, a heat treatment of holding 1100 ° C. or higher than 10 seconds in an atmosphere containing at least one or more of _{H 2} (Claim 6).
The vacancy concentration in the silicon wafer can be increased by performing the pre-heat treatment under the above conditions immediately before the precipitation heat treatment. The presence of these vacancies at a high density further promotes the formation of BMD precipitation nuclei in the subsequent precipitation heat treatment. Thereby, a silicon wafer on which BMD satisfying the above-described density and condition is formed can be obtained more efficiently, and a silicon wafer that can further prevent pattern deviation can be manufactured.

Moreover, it is preferable to perform the heat processing hold | maintained at 1150 degreeC or more for 1 hour or more just before performing the said precipitation heat processing (Claim 7).
By this heat treatment, dissolution of the grown-in precipitation nuclei can be suppressed, whereby the formation of the precipitation nuclei can be promoted by the subsequent precipitation heat treatment, and the silicon wafer on which BMD satisfying the desired relationship is precipitated is more efficient. Can get well.

Further, the Czochralski concentration of carbon in the silicon single crystal during growing by method ^{2 × 10 16 ~10 × 10 16} (atoms / cm 3) is preferably doped so as to (JEIDA) (claim 8) .
Grown-in precipitation nuclei with carbon-oxygen complexes as nuclei by doping carbon when growing silicon single crystals by the CZ method so that the resulting silicon wafer has a carbon concentration range as described above. The BMD can be more easily precipitated by precipitation heat treatment. Thereby, the formation of BMD precipitation nuclei in the subsequent precipitation heat treatment can be promoted.

As described above, oxygen precipitates detected by the RIE method exist in the interior of 1 × 10 ¹⁰ (pieces / cm ³ ) or more, and the oxygen concentration change ΔO _i (atoms / cm ³ ) before and after the oxygen precipitation heat treatment. ) (JEIDA) and when defining the density D of the oxygen precipitates (number / cm ^3), if a silicon wafer, such as formula ^{_{ΔO i / (D × 10 6}} ) is 5 or less, the heat treatment of the device process It is possible to suppress the movement of the generated slip dislocation, that is, to reduce the pattern deviation caused by the slip dislocation. Further, the occurrence of slip dislocation due to BMD can be suppressed. For this reason, the yield at the time of device manufacture can be made higher than before.

Hereinafter, the present invention will be described more specifically.
As described above, a silicon wafer having a BMD density and size effective to suppress slip dislocations generated in a device heat treatment process, which is particularly problematic with the miniaturization of device wiring patterns, and to prevent pattern displacement, Development of the manufacturing method was awaited.

  Therefore, the present inventor has intensively studied whether or not a silicon wafer having slip resistance can be obtained by adjusting the BMD density and size inside the wafer to a specific range.

As a result, the present inventors, the oxygen concentration variation before and after precipitation heat treatment to precipitate oxygen precipitate ^{_{ΔO i (atoms / cm 3)}} (JEIDA), the density of BMD which is detected by the RIE method D (number / cm ³ ), if it is a silicon wafer that satisfies the relationship of ΔO _i / (D × 10 ⁶ ) ≦ 5 and D ≧ 1 × 10 ¹⁰ , it can be a silicon wafer having slip (= pattern deviation) resistance. And the present invention was completed.

Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.
In the silicon wafer of the present invention, the amount of change in oxygen concentration before and after the BMD precipitation heat treatment was ΔO _i (atoms / cm ³ ) (JEIDA), and the density of BMD detected by the RIE method was D (pieces / cm ³ ). sometimes, it satisfies the relationship of ^{_{ΔO i / (D × 10 6}} ) ≦ 5, the relationship D ≧ 1 × ^{10 10} simultaneously.

As described above, if the BMD density D after the precipitation heat treatment is present in the wafer at a high density of 1 × 10 ¹⁰ (pieces / cm ³ ) or more as measured by the RIE method, the heat treatment in the device process is performed. The movement of the generated slip dislocation can be strongly suppressed. Further, if the amount of change in oxygen concentration before and after the BMD precipitation heat treatment is ΔO _i (atoms / cm ³ ) (JEIDA), if the value defined by ΔO _i / (D × 10 ⁶ ) is 5 or less, BMD1 The amount of oxygen atoms per unit can be reduced, in other words, a small-sized BMD can be present. Thereby, it is possible to suppress the occurrence of dislocation from the BMD itself.
With the above effects, it is possible to suppress the movement of dislocations typified by slips generated during heat treatment in the device process, and to suppress the generation of dislocations from the BMD itself, thereby generating pattern deviation in the exposure process. It can be set as the silicon wafer which can suppress strongly.

Here, as a conventional method for evaluating BMD, selective etching using chemicals is widely known. However, since it cannot be detected unless the defect size is 1 μm or more, the BMD size generated due to the recent low-temperature device process. In a situation where is small, sensitivity is lacking.
Moreover, this end a method is to observe the etch pits formed by selective etching with a microscope, the observation field of view is narrow and 200 [mu] m □ degree at most, the BMD density is detected and not 2 × 10 7 ^(pieces / cm ³⁾ or more I can't. In this case, in order to increase the detection sensitivity with respect to the BMD density, the cumulative observation area may be increased by multipoint measurement or observation while scanning the wafer. However, this is not convenient because it increases the measurement time.

As a method for detecting BMD with higher sensitivity than selective etching, there is an infrared scattering method using an infrared laser, and the limit of the defect size that can be detected is about 20 nm. However, since this method uses infrared scattering, BMD cannot be detected unless the BMD density is 1 × 10 ⁷ (pieces / cm ³ ) or more. Furthermore, if it is 1 × 10 ¹⁰ (pieces / cm ³ ) or more, there is a problem that it becomes impossible to classify individual BMDs due to scattering, and density cannot be measured.

However, in the case of the RIE method (for example, see Japanese Patent Application Laid-Open No. 2005-257576) in which the substrate or the predetermined layer is etched using anisotropic etching having a high selectivity with respect to crystal defects as in the present invention, the etching residue The density can be obtained by observing the number of the high density BMDs of 1 × 10 ¹⁰ (pieces / cm ³ ) or more.

Here, the RIE method will be explained.
As a method of evaluating while applying a small resolution in the depth direction of crystal defects containing semiconductor single crystal silicon oxide in the substrate (hereinafter referred to as SiO _x), a method is known, for example, disclosed in Japanese Patent No. 3451955 ing. This method evaluates crystal defects by performing highly selective anisotropic etching such as reactive ion etching at a constant thickness on the main surface of the substrate and detecting the remaining etching residue. is there.

Since the etching rate is different between the crystal defect forming region containing SiOx and the non-forming region not containing (the former has a lower etching rate), when the above etching is performed, the main surface of the substrate contains SiOx. Conical protrusions with crystal defects as vertices remain.
In this method, crystal defects are emphasized in the form of protrusions by anisotropic etching, and even minute defects can be easily detected.

Hereinafter, a specific procedure of the RIE method will be described with reference to FIG. 2 taking the crystal defect evaluation procedure disclosed in Japanese Patent No. 3451955 as an example.
The silicon wafer 10 shown in FIG. 2 (a), oxygen precipitates oxygen dissolved in the supersaturated precipitated as SiO _x in the silicon wafer 10 (BMD20) is formed by heat treatment.
When this silicon wafer 10 is used as a sample and crystal defects are evaluated by the RIE method, a silicon wafer is used in a halogen-based mixed gas (eg, HBr / Cl ₂ / He + O ₂ ) atmosphere using, for example, a commercially available RIE apparatus. Etching is performed from the main surface of the silicon wafer 10 by anisotropic etching with a high selection ratio with respect to the BMD 20 included in the silicon wafer 10. Then, as shown in FIG. 2 (b), a conical protrusion resulting from the BMD 20 is formed as an etching residue (hillock) 30. Crystal defects can be evaluated based on the hillock 30.
For example, if the number of hillocks 30 obtained is counted, the density of the BMD 20 in the silicon wafer 10 in the etched range can be obtained.

Further, the decrease in oxygen concentration due to the heat treatment is caused by the precipitation of oxygen dissolved in silicon beyond the solid solubility limit and the diffusion out of the wafer by outward diffusion. That is, except for the region where oxygen disappears due to out-diffusion, it can be considered that the decrease in oxygen is consumed by BMD formation, and the BMD size is relatively determined from the BMD density and oxygen concentration change amount. It becomes possible to quantify. Therefore, the value obtained by dividing the oxygen concentration change amount ΔOi by the BMD density D is defined as the BMD size. Incidentally, are multiplied by ¹⁰⁶ to density D is one convenient for easy understanding of the numerical value obtained.

Here, the silicon wafer may have a carbon concentration in the range of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA).
As described above, if the carbon concentration in the silicon wafer is in the above range, it is assumed that a grown-in precipitation nucleus having a carbon-oxygen complex as a nucleus is formed in the wafer before the precipitation heat treatment. By this Grown-in precipitation nucleus, BMD can be more easily precipitated, and a silicon wafer more resistant to slip (pattern shift) can be obtained.

  Next, the method for producing a silicon wafer according to the present invention will be described below, but the present invention is not limited to this.

First, a silicon single crystal is grown by the CZ method. The growing conditions at this time are not particularly limited, and may be general conditions.
Thereafter, a silicon semiconductor substrate is cut out from the grown silicon single crystal. This cutting process can also be made into a general condition, for example, can be sliced with a cutting device such as an inner peripheral slicer or a wire saw.
Thereafter, it is desirable to perform at least one of lapping, etching, and polishing.

Here, a silicon single crystal can be grown by adding a dopant such that carbon has a concentration of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA).
As described above, the carbon is grown in the silicon single crystal by the CZ method by adding the dopant so that the concentration becomes 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA). Grown-in precipitation nuclei with carbon-oxygen complexes as nuclei can be formed inside the formed silicon wafer. Then, nucleation and precipitation of BMD in the subsequent precipitation heat treatment are promoted, a silicon wafer that satisfies a desired condition can be obtained efficiently, and it is more effective in preventing pattern deviation.

Thereafter, precipitation heat treatment is performed. Thus, a silicon wafer is manufactured.
According to the silicon wafer manufacturing method of the present invention, slip dislocations that cause pattern deviation, which is one of the causes of product defects, are prevented from occurring on the wafer surface when transferring device wiring patterns in an overlapping manner. A silicon wafer can be obtained. For this reason, the silicon wafer which can manufacture a semiconductor device with a sufficient yield can be obtained.

Here, as this precipitation heat treatment, a first heat treatment can be performed at 500 to 700 ° C. for 1 hour or more, and then a second heat treatment at 1000 ° C. or more can be performed.
The first heat treatment is preferably performed under a temperature condition that facilitates nucleation, and the above-described temperature range is optimal. If the first heat treatment is within this temperature range, the nucleation rate can be increased. That is, if it is 500 degreeC or more, since the size of BMD can fully be grown and it can suppress disappearing by the following 2nd heat processing, a predetermined BMD density can be obtained. Moreover, if it is 700 degrees C or less, since it can prevent that many oxygen precipitation nuclei (Grown-in precipitation nuclei) which precipitate in a crystal growth stage will lose | disappear, a desired BMD density can be obtained easily.
And by the second heat treatment at 1000 ° C. or more, BMD having a density range and size that can increase the slip resistance of the silicon wafer can be deposited inside the wafer, and therefore slip dislocations move during the heat treatment in the device process. Can be suppressed. Therefore, it can be set as the silicon wafer which can also suppress generation | occurrence | production of a pattern shift.

Further, as the precipitation heat treatment, the heat treatment can be performed in a condition where the heat treatment furnace is charged at 500 to 700 ° C., heated at a rate of 3 ° C./min or less, and kept at 1000 ° C. or more and 1 hour or less.
If the heating rate is 3 ° C./min or less after being charged into a heat treatment furnace at 500 to 700 ° C., BMD can be grown to a sufficient size, and the BMD is precipitated by maintaining the high temperature thereafter. It is possible to obtain a silicon wafer on which BMDs of the density and size are formed.

Furthermore, immediately before the precipitation heat treatment, as a pre-heat treatment, in a rapid heating / cooling heat treatment furnace (RTA furnace), in an atmosphere containing at least one of N ₂ , NH ₃ , Ar, and H ₂ , the temperature is increased to 1100 ° C. or higher for 10 seconds. The above heat treatment can be performed.
By performing the pre-heat treatment under such conditions, the vacancy concentration in the silicon wafer can be increased. If the vacancy concentration increases, nucleation and BMD precipitation are promoted in the subsequent precipitation heat treatment. As a result, a silicon wafer having high slip resistance can be obtained efficiently, and a silicon wafer that is more effective in preventing pattern deviation can be manufactured.

And as this pre-heat treatment, a heat treatment under the condition of holding at 1150 ° C. or higher for 1 hour or more, which is a condition different from the pre-heat treatment can be performed.
By performing such pre-heat treatment, dissolution of the grown-in precipitation nuclei can be suppressed, and thereby a silicon wafer satisfying a desired condition can be obtained more efficiently, and a silicon wafer having high resistance to pattern deviation can be reliably obtained. It can be obtained with good yield.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Examples 1-16, Comparative Examples 1-9)
First, a silicon semiconductor substrate was cut out from a silicon single crystal grown by the CZ method, and 23 silicon semiconductor substrates were prepared (Examples 1-9, 11-15, and Comparative Examples 1-9). At this time, the diameter of the silicon semiconductor substrate was 200 mm, and the conductivity type was p-type. The resistivity was 8-12 Ω · cm, and the initial oxygen concentration was 7-8 × 10 ¹⁷ (atoms / cm ³ ) (JEIDA).
The above silicon single crystal is grown under the same conditions except that a dopant is used so that the carbon concentration is 5 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA). Two semiconductor substrates were obtained (Examples 10 and 16).

  Next, precipitation heat treatment described in Table 1 or Table 2 was performed on a total of 25 prepared silicon semiconductor substrates. Details of the precipitation heat treatment are shown in Tables 1 and 2. In addition, the silicon semiconductor substrates of Examples 8, 9, 14, and 15 were subjected to heat treatment under the conditions described in Tables 1 and 2 as pre-heat treatment immediately before the precipitation heat treatment. As a result, a total of 25 silicon wafers were obtained.

  An exposure process was performed on 25 silicon wafers manufactured by the above-described method, and how much pattern deviation occurred was evaluated by the following method.

First, a resist film was applied to the surface of the silicon wafer from which the oxynitride film formed during the precipitation heat treatment was removed, and exposure and development were performed with an exposure apparatus. Thereafter, 300 nm was etched from the surface by the RIE method. Thereafter, the resist was removed by washing with sulfuric acid and water to obtain a patterned wafer.
In order to intentionally introduce the slip, the slip was introduced into the silicon wafer by quenching from a state of being held at a temperature of 1000 ° C. or higher as a heat treatment for introducing the slip.
Thereafter, resist coating, exposure, and development were performed again, and the overlay accuracy of the specific pattern formed by the first and second photolithography was measured by the overlay accuracy measurement program.

Moreover, the BMD density evaluation after heat processing was implemented by RIE method. Further, the oxygen concentration in the silicon wafer before and after the precipitation heat treatment was evaluated by FTIR (Fourier Transform Infrared), and the change amount ΔO _i (atoms / cm ³ ) (JEIDA) of the oxygen concentration before and after the precipitation heat treatment was obtained.
The data obtained from the above are also shown in Tables 1 and 2.

  Note that the level of pattern deviation, which is a major problem in the device process, is set to 60 nm or more at 3σ. If it exceeds 60 nm, the characteristics of the formed circuit deteriorate and the possibility of failure becomes high. Therefore, in Tables 1 and 2, for those in which 3σ exceeds 60 nm, the column of good / bad resistance to pattern deviation is marked with “x”. Similarly, in the range of 20 to 60 nm, ◯ and in less than 20 nm were evaluated as ◎, and it was determined that there was little influence on the occurrence of defects in the device manufacturing process.

As shown in Tables 1 and 2, the silicon wafers of Examples 1 to 16 satisfying ΔO _i / (D × 10 ⁶ ) ≦ 5 and D ≧ 1 × 10 ¹⁰ at the same time have a pattern shift level of 50 nm. It was as follows and was found to have good slip resistance. Particularly, the silicon wafers of Examples 8, 9, 14, and 15 subjected to the pre-heat treatment and Examples 10 and ¹⁶ doped with carbon of 5 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA) are very good. Exhibited resistance to pattern shift.
In contrast, the silicon wafers of Comparative Examples 4 and 9 that do not satisfy only ΔO _i / (D × 10 ⁶ ) ≦ 5, or the silicon wafers of Comparative Examples 1 and 5 that do not satisfy only D ≧ 1 × 10 ¹⁰ , The silicon wafers of Comparative Examples 2 and 3 that are not satisfied at the same time have both pattern deviations exceeding 60 nm. When such silicon wafers are used, the pattern deviations in the device process are large and the yield is expected to deteriorate greatly. Is done.

Moreover, the X-ray topography observation was performed on the silicon wafers of Example 1 which had good resistance to pattern deviation and Comparative Example 2 which was bad. The result is shown in FIG. 1A shows a silicon wafer of Example 1, and FIG. 1B shows a silicon wafer of Comparative Example 2.
As shown in FIG. 1A, the silicon wafer of Example 1 had almost no dislocations in the plane thereof, and the wafer plane was uniform. From this, it was found that even when slip introduction treatment was performed, dislocation did not appear on the wafer surface because the movement of slip dislocation was suppressed by BMD in the silicon wafer. On the other hand, as shown in FIG. 1B, the silicon wafer of Comparative Example 2 is a silicon wafer in which many crystal defects are generated in the outer peripheral portion and the movement of slip dislocations is not completely suppressed. I found out.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

It is the figure which showed the X-ray topography of the silicon wafer after the precipitation heat processing of Example 1 and Comparative Example 2. FIG. (A) is a silicon wafer of Example 1, and (b) is a silicon wafer of Comparative Example 2. It is explanatory drawing explaining the outline of RIE method.

Explanation of symbols

  10 ... silicon wafer, 20 ... BMD, 30 ... hillock.

Claims (8)

A silicon wafer,
When the amount of oxygen concentration change before and after the precipitation heat treatment for precipitating oxygen precipitates is ΔO _i (atoms / cm ³ ) (JEIDA), and the density of oxygen precipitates detected by the RIE method is D (pieces / cm ³ ), silicon wafer, characterized in that ^{_{ΔO i / (D × 10 6}} ) ≦ 5, and satisfies the relation of D ≧ 1 × ^{10 10.} 2. The silicon wafer according to claim 1, wherein the silicon wafer has a carbon concentration in a range of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA). A silicon wafer manufacturing method comprising:
A silicon semiconductor substrate is cut out from a silicon single crystal grown by the Czochralski method,
The silicon semiconductor substrate is subjected to a precipitation heat treatment, the density D measured by the RIE method is 1 × 10 ¹⁰ (pieces / cm ³ ) or more, and the oxygen concentration change amount before and after the precipitation heat treatment is ΔO _i (atoms / cm ³ ). A method for producing a silicon wafer, wherein an oxygen precipitate satisfying a relationship of ΔO _i / (D × 10 ⁶ ) ≦ 5 when (JEIDA) is used.   4. The method for producing a silicon wafer according to claim 3, wherein as the precipitation heat treatment, a first heat treatment is performed at 500 to 700 ° C. for 1 hour or more, and then a second heat treatment at 1000 ° C. or more is performed.   4. The precipitation heat treatment is performed by putting in a heat treatment furnace at 500 to 700 [deg.] C., heating at a rate of 3 [deg.] C./min or less, and holding at 1000 [deg.] C. or more and 1 hour or less. Silicon wafer manufacturing method. Immediately before the precipitation heat treatment, a rapid elevation heat treatment furnace, N _2, NH 3, _Ar, and performing heat treatment of holding 1100 ° C. or higher than 10 seconds in an atmosphere containing at least one or more of H ₂ 6. The method for producing a silicon wafer according to claim 3, wherein the silicon wafer is produced.   The method for producing a silicon wafer according to any one of claims 3 to 5, wherein a heat treatment is performed at 1150 ° C or higher for 1 hour or longer immediately before the precipitation heat treatment. The silicon single crystal is doped with carbon so as to have a concentration of 2 × 10 ¹⁶ to 10 × 10 ¹⁶ (atoms / cm ³ ) (JEIDA) when grown by the Czochralski method. Item 8. The method for manufacturing a silicon wafer according to any one of Items 7 to 8.

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