JP2010034162A - Method of manufacturing solar cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a solar cell that suppresses mixture of impurities into a substantially-intrinsic amorphous semiconductor layer and deterioration in productivity of solar cells. <P>SOLUTION: In the method, an n-type single-crystal silicon wafer 21 is placed on a first placing surface 50A of a first substrate tray 50 covered by an i-type amorphous silicon layer 28, in a step of forming an HIT-structure. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a solar cell including a crystalline semiconductor substrate.

  Conventionally, a so-called HIT (Heterojunction with Intrinsic Thin-Layer) type solar cell that can improve photoelectric conversion efficiency by improving semiconductor junction characteristics is known. In a HIT type solar cell, there is substantially no gap between a semiconductor junction formed by a crystalline semiconductor substrate of one conductivity type (for example, n-type) and an amorphous semiconductor layer of another conductivity type (for example, p-type). Intrinsically, an amorphous semiconductor layer is inserted.

  In general, a substantially intrinsic amorphous semiconductor layer and another conductive type amorphous semiconductor layer are sequentially formed on a crystalline semiconductor substrate by a CVD (Chemical Vapor Deposition) method (for example, , See Patent Document 1).

Here, the crystalline semiconductor substrate is stored in a reaction container in a state of being placed on a substrate tray (see, for example, Patent Document 2). Such a substrate tray is usually washed repeatedly to remove a semiconductor layer deposited on a mounting surface after being repeatedly used a plurality of times.
JP 2003-324209 A JP 2005-327995 A

  However, when a substantially intrinsic amorphous semiconductor layer is formed on a crystalline semiconductor substrate, impurities (dopants) contained in the semiconductor layer deposited on the mounting surface of the substrate tray are substantially intrinsic. It will be mixed into the amorphous semiconductor layer.

  Specifically, a semiconductor layer in which an amorphous semiconductor layer of another conductivity type forms the outermost surface is deposited on a mounting surface of a substrate tray that has been used a plurality of times in the CVD method. When a substantially intrinsic amorphous semiconductor layer is formed by placing a crystalline semiconductor substrate on such a placement surface, a non-conductive type non-conductive layer is formed on the substantially intrinsic amorphous semiconductor layer. Impurities added to the crystalline semiconductor layer are mixed. Therefore, it has been difficult to perform valence electron control with high accuracy in the process of forming a substantially intrinsic amorphous semiconductor layer.

  On the other hand, if the number of cleanings of the substrate tray is increased in order to suppress such impurity contamination, the productivity of the solar cell is lowered.

  The present invention has been made in view of the above-described situation, and manufacture of a solar cell capable of suppressing contamination of impurities into a substantially intrinsic amorphous semiconductor layer and a decrease in productivity of the solar cell. It aims to provide a method.

  A method of manufacturing a solar cell according to a feature of the present invention includes a step of placing a crystalline semiconductor substrate having one conductivity type on a placement surface of a substrate tray, and a placement on which the crystalline semiconductor substrate is placed. A step of forming a substantially intrinsic amorphous semiconductor layer on the surface by a CVD method, and another conductivity type by a CVD method on one mounting surface on which the crystalline semiconductor substrate is mounted A step of forming an amorphous semiconductor layer, wherein the mounting surface is covered with a substantially intrinsic amorphous semiconductor layer in the step of mounting the crystalline semiconductor substrate on the mounting surface. It is a summary.

  According to the method for manufacturing a solar cell according to the feature of the present invention, when a substantially intrinsic amorphous semiconductor layer is formed on a single mounting surface by CVD, impurities are formed on the single mounting surface. Even when a semiconductor layer including the semiconductor layer is deposited, impurities can be prevented from being knocked out of the semiconductor layer. Therefore, it is possible to suppress deterioration of the characteristics of the substantially intrinsic amorphous semiconductor layer and to perform valence electron control with high accuracy in the process of forming the substantially intrinsic amorphous semiconductor layer. It becomes. Moreover, since the frequency | count of washing | cleaning of a substrate tray can be decreased, productivity of a solar cell can be improved.

  In a feature of the present invention, the method may include a step of forming a substantially intrinsic amorphous semiconductor layer by a CVD method on another placement surface provided on the opposite side of the placement surface of the substrate tray. Good.

  In the feature of the present invention, a step of placing another crystalline semiconductor substrate different from the crystalline semiconductor substrate on the other placement surface, and a CVD on the other placement surface on which the other crystalline semiconductor substrate is placed. A step of forming a substantially intrinsic amorphous semiconductor layer by a method, and an amorphous material having another conductivity type by a CVD method on another placement surface on which another crystalline semiconductor substrate is placed. Forming a semiconductor layer.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the solar cell which can suppress mixing of the impurity into a substantially intrinsic amorphous semiconductor layer and the productivity fall of a solar cell can be provided.

  Hereinafter, a catalytic CVD apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

  However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones. Therefore, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(Configuration of solar cell)
Below, the structure of the solar cell which concerns on embodiment of this invention is demonstrated, referring drawings. FIG. 1 is a plan view of a solar cell 10 according to an embodiment of the present invention. 2 is a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 1, the solar cell 10 includes a photoelectric conversion unit 20, a plurality of thin wire electrodes 30, and a connection electrode 40.

  The photoelectric conversion unit 20 has a semiconductor pn junction or a semiconductor pin junction formed using a semiconductor substrate, and generates photogenerated carriers by receiving light. The photogenerated carrier refers to holes and electrons generated by absorption of sunlight into the photoelectric conversion unit 20. The photoelectric conversion unit 20 includes a semiconductor substrate made of a crystalline semiconductor material such as single crystal Si or polycrystalline Si. In the present embodiment, the photoelectric conversion unit 20 reduces defects at the interface by sandwiching a substantially intrinsic amorphous silicon layer between the single crystal silicon wafer and the amorphous silicon layer, and thus heterogeneity. It has a so-called HIT structure with improved bonding interface characteristics. Specifically, as shown in FIG. 2, the photoelectric conversion unit 20 includes an i-type amorphous silicon layer 22 and a p-type amorphous silicon sequentially formed on one main surface of an n-type single crystal silicon wafer 21. The layer 23 and the ITO layer 24, and the i-type amorphous silicon layer 25, the n-type amorphous silicon layer 26, and the ITO layer 27 are sequentially formed on the other main surface of the n-type single crystal silicon wafer 21. Each amorphous silicon layer can be formed by a CVD method.

  The multiple thin wire electrodes 30 are electrodes that collect photogenerated carriers from the photoelectric conversion unit 20. As shown in FIG. 1, the plurality of fine wire electrodes 30 are formed over substantially the entire light receiving surface of the photoelectric conversion unit 20. The plurality of thin wire electrodes 30 may be formed of a resin-type conductive paste using a resin material as a binder and conductive particles such as silver particles as a filler, or a sintered-type conductive paste (so-called ceramic paste). it can. The dimension, shape, and number of each thin wire electrode 30 can be set to an appropriate number in consideration of the size and physical properties of the photoelectric conversion unit 20. For example, about 50 thin wire electrodes 30 can be formed on the photoelectric conversion unit 20 of about 100 mm square.

  The connection electrode 40 is an electrode to which a wiring material (not shown) for electrically connecting the solar cells 10 to each other is connected. As shown in FIG. 2, the connection electrode 40 is formed along a predetermined direction. The connection electrode 40 can be formed using the same material as the plurality of thin wire electrodes 30. In addition, the dimension, shape, and number of the connection electrodes 40 can be set to an appropriate number in consideration of the size and physical properties of the photoelectric conversion unit 20.

(Method for manufacturing solar cell)
Next, the manufacturing method of the solar cell which concerns on embodiment of this invention is demonstrated, referring drawings. In the following description, the BSF structure is formed after the HIT structure is formed for each semiconductor substrate (n-type single crystal silicon wafer 21).

1. Formation of HIT structure <First time>
FIG. 3 is a perspective view of the first substrate tray 50 for fixing the n-type single crystal silicon wafer 21. 4 is a cross-sectional view taken along line BB in FIG.

  First, as shown in FIG. 3, a plurality of n-type single crystal silicon wafers 21 are placed on a first substrate tray 50 formed of an aluminum plate or a stainless steel plate. Specifically, as shown in FIG. 4, the first substrate tray 50 includes a first placement surface 50A, a second placement surface 50B, and a plurality of recesses 50C. The crystalline silicon wafer 21 is fixed in a recess 50C formed on the first placement surface 50A. The n-type single crystal silicon wafer 21 may be fixed by a fixture or by electrostatic adsorption.

Next, an i-type amorphous silicon layer 22 is formed on one main surface of the n-type single crystal silicon wafer 21 by PECVD (plasma enhanced chemical vapor deposition). Specifically, as shown in FIG. 5, the two electrodes 70 provided in the vacuum chamber 60 and the two first substrate trays 50 are opposed to each other. Subsequently, silane gas (SiH ₄ ) and hydrogen gas (H ₂ ) as a dilution gas are introduced into the vacuum chamber 60, and substantially have a thickness (a few nm to about 25 nm) that does not substantially contribute to power generation. An intrinsic i-type amorphous silicon layer 22 is formed. Here, as shown in FIG. 5, since plasma is generated in the processing space R, the i-type amorphous silicon layer 22 is formed on the substantially entire first placement surface 50 </ b> A of the first substrate tray 50.

Next, a p-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22 by PECVD. Specifically, as shown in FIG. 6, the two electrodes 71 provided in the vacuum chamber 61 and the two first substrate trays 50 are opposed to each other. Subsequently, silane gas, hydrogen gas, and diborane gas (B ₂ H ₆ ) as a dopant gas are introduced into the vacuum chamber 61 to form a p-type amorphous silicon layer 23 having a thickness of about 10 nm. As a result, a HIT structure in which a substantially intrinsic i-type amorphous silicon layer 22 is interposed between the n-type single crystal silicon wafer 21 and the p-type amorphous silicon layer 23 is formed. Here, as shown in FIG. 6, since plasma is formed in the processing space R, the p-type amorphous silicon layer 23 is formed on substantially the entire first placement surface 50 </ b> A of the first substrate tray 50. In this process, the catalyst wire 80 shown in FIG. 6 is not used.

  Subsequently, the n-type single crystal silicon wafer 21 (hereinafter referred to as “HIT wafer W1”) on which the i-type amorphous silicon layer 22 and the p-type amorphous silicon layer 23 are formed is removed from the first substrate tray 50. Then, the process proceeds to a BSF structure forming process to be described later.

<Second time>
Next, the first substrate tray 50 is turned upside down and a plurality of new n-type single crystal silicon wafers 21 are placed in the recesses 50C formed on the second placement surface 50B as shown in FIG. . Note that the i-type amorphous silicon layer 22 and the p-type amorphous silicon layer 23 are sequentially deposited on the first placement surface 50A of the first substrate tray 50 other than the recess 50C.

  Next, an i-type amorphous silicon layer 22 is formed on one main surface of each n-type single crystal silicon wafer 21 according to the above-described formation method.

  Subsequently, a p-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22 in accordance with the formation method described above. Here, in the present embodiment, in parallel with the step of forming the p-type amorphous silicon layer 23, i-type amorphous is formed on the first placement surface 50A of the first substrate tray 50 by the catalytic CVD method. A quality silicon layer is formed.

  Specifically, as shown in FIG. 6, the catalyst wire 80 provided between the two first substrate trays 50 is energized to raise the temperature (about 1700 ° C.) and introduce silane gas and hydrogen gas. . Accordingly, the source gas is thermally decomposed in the processing space S, and the i-type amorphous silicon layer 28 is formed on the first placement surface 50 </ b> A of the first substrate tray 50. That is, the i-type amorphous silicon layer 22 and the p-type amorphous silicon layer 23 deposited on the first placement surface 50 </ b> A of the first substrate tray 50 are covered with the i-type amorphous silicon layer 28.

  Subsequently, the HIT wafer W1 is removed from the first substrate tray 50, and the process proceeds to a BSF structure forming process described later.

<3rd>
Next, the first substrate tray 50 is turned upside down and a plurality of new n-type single crystal silicon wafers 21 are placed in the recesses 50C formed on the first placement surface 50A as shown in FIG. .

  As described above, the first placement surface 50A of the first substrate tray 50 is covered with the i-type amorphous silicon layer 28. Accordingly, the n-type single crystal silicon wafer 21 is placed on the i-type amorphous silicon layer 28. On the other hand, the i-type amorphous silicon layer 22 and the p-type amorphous silicon layer 23 are sequentially deposited on the second placement surface 50B of the first substrate tray 50 other than the recess 50C.

  Next, an i-type amorphous silicon layer 22 is formed on one main surface of each n-type single crystal silicon wafer 21 according to the above-described formation method.

  Subsequently, a p-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22 in accordance with the formation method described above. Here, in parallel with the step of forming the p-type amorphous silicon layer 23, the i-type amorphous silicon layer 28 is formed on the second placement surface 50 </ b> B of the first substrate tray 50 according to the above-described formation method. Form. As a result, the i-type amorphous silicon layer 22 and the p-type amorphous silicon layer 23 deposited on the second placement surface 50B of the first substrate tray 50 are covered with the i-type amorphous silicon layer 28. .

  Subsequently, the HIT wafer W1 is removed from the first substrate tray 50, and the process proceeds to a BSF structure forming process described later.

<After the 4th time>
The fourth and subsequent steps can be performed in the same manner as the third HIT structure forming step described above. That is, the first substrate tray 50 is turned upside down, and a new n-type single crystal silicon wafer 21 is placed on the i-type amorphous silicon layer 28 as shown in FIG. Subsequently, the i-type amorphous silicon layer 22, the p-type amorphous silicon layer 23, and the i-type amorphous silicon layer 28 are formed.

  It is desirable to clean the first substrate tray 50 after repeatedly forming the HIT structure a predetermined number of times.

2. Formation of BSF structure <First>
First, as shown in FIG. 10, the HIT wafer W <b> 1 is placed on the first placement surface 51 </ b> A of the second substrate tray 51 with the other main surface of the n-type single crystal silicon wafer 21 facing up. The second substrate tray 51 has the same configuration as the first substrate tray 50, and the HIT wafer W1 is fixed in the recess 51C formed on the first placement surface 51A.

  Next, the i-type amorphous silicon layer 25 is formed on the other main surface of the n-type single crystal silicon wafer 21 by the same formation method as the i-type amorphous silicon layer 22 described above.

Next, an n-type amorphous silicon layer 26 is formed on the i-type amorphous silicon layer 25 by PECVD. Specifically, as shown in FIG. 11, the two electrodes 72 provided in the vacuum chamber 62 and the two second substrate trays 51 are opposed to each other. Subsequently, silane gas, a phosphine gas as a hydrogen gas and dopant gas (PH ₃₎ was introduced into the vacuum chamber 62 to form an n-type amorphous silicon layer 26 having a thickness of approximately 10 nm. As a result, a BSF structure is formed in which a substantially intrinsic i-type amorphous silicon layer 25 and an n-type amorphous silicon layer 26 are sequentially formed on the n-type single crystal silicon wafer 21. Here, as shown in FIG. 11, since plasma is formed in the processing space R, the n-type amorphous silicon layer 26 is formed on substantially the entire first placement surface 51 </ b> A of the second substrate tray 51. In this process, the catalyst wire 81 shown in FIG. 11 is not used.

  Subsequently, the HIT wafer W1 (hereinafter referred to as “BSF wafer W2”) on which the i-type amorphous silicon layer 25 and the n-type amorphous silicon layer 26 are formed is removed from the second substrate tray 51, and ITO described later Move on to layer formation process.

<Second time>
Next, the second substrate tray 51 is turned upside down, and a plurality of new n-type single crystal silicon wafers 21 are placed in the recesses 51C formed on the second placement surface 51B, as shown in FIG. . Note that the i-type amorphous silicon layer 25 and the n-type amorphous silicon layer 26 are sequentially deposited on the first placement surface 51A of the second substrate tray 51 other than the recess 51C.

  Next, an i-type amorphous silicon layer 25 is formed on one main surface of each n-type single crystal silicon wafer 21 in accordance with the formation method described above.

  Subsequently, an n-type amorphous silicon layer 26 is formed on the i-type amorphous silicon layer 25 in accordance with the formation method described above. Here, in the present embodiment, in parallel with the step of forming the n-type amorphous silicon layer 26, i-type amorphous is formed on the first placement surface 51A of the second substrate tray 51 by the catalytic CVD method. A quality silicon layer is formed.

  Specifically, as shown in FIG. 11, the catalyst wire 80 provided between the two second substrate trays 51 is energized to raise the temperature (about 1700 ° C.) and introduce silane gas and hydrogen gas. . Thereby, the source gas is thermally decomposed in the processing space S, and the i-type amorphous silicon layer 29 is formed on the first placement surface 51 </ b> A of the second substrate tray 51. That is, the i-type amorphous silicon layer 25 and the n-type amorphous silicon layer 26 deposited on the first placement surface 51A of the second substrate tray 51 are covered with the i-type amorphous silicon layer 29.

  Subsequently, the BSF wafer W2 is removed from the second substrate tray 51, and the process proceeds to an ITO layer forming step to be described later.

<3rd>
Next, the second substrate tray 51 is turned upside down, and a plurality of new n-type single crystal silicon wafers 21 are placed in the recesses 51C formed on the first placement surface 51A as shown in FIG. .

  As described above, the first placement surface 51 </ b> A of the second substrate tray 51 is covered with the i-type amorphous silicon layer 29. Accordingly, the HIT wafer W1 is placed on the i-type amorphous silicon layer 29. On the other hand, the i-type amorphous silicon layer 25 and the n-type amorphous silicon layer 26 are sequentially deposited on the second placement surface 51B of the second substrate tray 51 other than the recess 51C.

  Next, an i-type amorphous silicon layer 25 is formed on the other main surface of each n-type single crystal silicon wafer 21 in accordance with the formation method described above.

  Subsequently, an n-type amorphous silicon layer 26 is formed on the i-type amorphous silicon layer 25 in accordance with the formation method described above. Here, in parallel with the step of forming the n-type amorphous silicon layer 26, the i-type amorphous silicon layer 29 is formed on the second placement surface 51B of the second substrate tray 51 in accordance with the above-described formation method. Form. As a result, the i-type amorphous silicon layer 25 and the n-type amorphous silicon layer 26 deposited on the second placement surface 51B of the second substrate tray 51 are covered with the i-type amorphous silicon layer 29. .

  Subsequently, the BSF wafer W2 is removed from the second substrate tray 51, and the process proceeds to an ITO layer forming step to be described later.

<After the 4th time>
The fourth and subsequent steps can be performed in the same manner as the third HIT structure forming step described above. That is, the second substrate tray 51 is turned upside down, and a new HIT wafer W1 is placed on the i-type amorphous silicon layer 29 as shown in FIG. Subsequently, an i-type amorphous silicon layer 25, an n-type amorphous silicon layer 26, and an i-type amorphous silicon layer 29 are formed.

  It is desirable that the second substrate tray 51 be cleaned after the formation of the BSF structure is repeated a predetermined number of times.

3. Formation of ITO Layer Next, an ITO layer 24 and an ITO layer 27 having a thickness of about 100 nm are formed on each BSF wafer W2 by sputtering or the like. Thus, the solar cell 10 according to this embodiment is manufactured.

(Function and effect)
In the solar cell manufacturing method according to the present embodiment, the n-type single crystal silicon wafer 21 is formed on the first substrate tray 50 covered with the i-type amorphous silicon layer 28 in the third and subsequent formations of the HIT structure. 1 is placed on the placement surface 50A.

  Therefore, when the i-type amorphous silicon layer 22 is formed on the first placement surface 50A (one main surface of the n-type single crystal silicon wafer 21) by the CVD method, it is deposited on the first placement surface 50A. It is possible to suppress the dopant from being knocked out of the p-type amorphous silicon layer 23 formed. For this reason, it is possible to suppress deterioration of the characteristics of the i-type amorphous silicon layer 22 and to perform valence electron control with high accuracy in the process of forming the i-type amorphous silicon layer 22.

  Here, conventionally, it is necessary to frequently wash the first substrate tray 50 in order to suppress the mixing of the dopant. On the other hand, according to the method for manufacturing a solar cell according to the present embodiment, it is possible to suppress the dopant from being knocked out of the p-type amorphous silicon layer 23, so that the number of times of cleaning the first substrate tray 50 can be reduced. it can. As a result, the productivity of the solar cell 10 can be improved.

  In the method for manufacturing a solar cell according to this embodiment, the HIT wafer W1 is first mounted on the second substrate tray 51 covered with the i-type amorphous silicon layer 29 in the third and subsequent formations of the BSF structure. It is mounted on the mounting surface 51A.

  Therefore, when the i-type amorphous silicon layer 25 is formed on the first placement surface 51A (the other main surface of the n-type single crystal silicon wafer 21) by the CVD method, it is deposited on the first placement surface 51A. It is possible to suppress the dopant from being knocked out of the n-type amorphous silicon layer 26 thus formed. Therefore, it is possible to suppress the deterioration of the characteristics of the i-type amorphous silicon layer 25 and to perform valence electron control with high accuracy in the process of forming the i-type amorphous silicon layer 25.

  Moreover, since the frequency | count of washing | cleaning of the 2nd board | substrate tray 51 can be reduced as above-mentioned, productivity of a solar cell can be improved.

(Other embodiments)
Although the present invention has been described according to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the embodiment described above, the i-type amorphous silicon layer 28 and the i-type amorphous silicon layer 29 are formed by the catalytic CVD method, but the present invention is not limited to this. For example, the i-type amorphous silicon layer 28 and the i-type amorphous silicon layer 29 may be formed by PECVD.

  In the above-described embodiment, the i-type amorphous silicon layer 28 is formed in parallel with the step of forming the p-type amorphous silicon layer 23. However, the present invention is not limited to this. For example, the i-type amorphous silicon layer 28 may be formed in parallel with the step of forming the i-type amorphous silicon layer 22 or after the step of forming the p-type amorphous silicon layer 23.

  In the above-described embodiment, the i-type amorphous silicon layer 29 is formed in parallel with the step of forming the n-type amorphous silicon layer 26. However, the present invention is not limited to this. For example, the i-type amorphous silicon layer 29 may be formed in parallel with the step of forming the i-type amorphous silicon layer 25 or after the step of forming the n-type amorphous silicon layer 26.

  In the above-described embodiment, the wafer is placed on the placement surface covered with the i-type amorphous silicon layer in the formation process of both the HIT structure and the BSF structure. In the process, the wafer may be placed on a placement surface covered with an i-type amorphous silicon layer.

  In the above-described embodiment, each amorphous silicon layer is formed in a separate vacuum chamber. However, each amorphous silicon layer may be formed in one vacuum chamber.

  In the above-described embodiment, the plurality of fine wire electrodes 30 and the connection electrodes 40 are formed in a comb shape. However, the present invention is not limited to this. The present invention does not limit the shape or the like of the electrode formed on the photoelectric conversion unit 20.

It is a top view of the solar cell 10 which concerns on embodiment of this invention. It is sectional drawing in the AA of FIG. It is a perspective view of the 1st substrate tray 50 concerning the embodiment of the present invention. It is sectional drawing in the BB line of FIG. It is a figure which shows the structure of the vacuum chamber 60 which concerns on embodiment of this invention. It is a figure which shows the structure of the vacuum chamber 61 which concerns on embodiment of this invention. It is a figure for demonstrating the formation method of the HIT structure which concerns on embodiment of this invention (the 1). It is a figure for demonstrating the formation method of the HIT structure which concerns on embodiment of this invention (the 2). It is a figure for demonstrating the formation method of the HIT structure which concerns on embodiment of this invention (the 3). It is a figure for demonstrating the formation method of the BSF structure which concerns on embodiment of this invention (the 1). It is a figure which shows the structure of the vacuum chamber 62 which concerns on embodiment of this invention. It is a figure for demonstrating the formation method of the BSF structure which concerns on embodiment of this invention (the 2). It is a figure for demonstrating the formation method of the BSF structure which concerns on embodiment of this invention (the 3). It is a figure for demonstrating the formation method of the BSF structure which concerns on embodiment of this invention (the 4).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Solar cell, 20 ... Photoelectric conversion part, 21 ... n-type single crystal silicon wafer, 22 ... i-type amorphous silicon layer, 23 ... p-type amorphous silicon layer, 24 ... ITO layer, 25 ... i-type non- Crystalline silicon layer, 26 ... n-type amorphous silicon layer, 27 ... ITO layer, 28,29 ... i-type amorphous silicon layer, 30 ... fine wire electrode, 40 ... connecting electrode, 50 ... first substrate tray, 50A ... first placement surface, 50B ... second placement surface, 50C ... concave, 51 ... second substrate tray, 51A ... first placement surface, 51B ... second placement surface, 51C ... concave, 60-62 ... Vacuum chamber, 70-72 ... Electrodes, 80,81 ... Catalyst wire

Claims (3)

Placing a crystalline semiconductor substrate having one conductivity type on one placement surface of a substrate tray;
Forming a substantially intrinsic amorphous semiconductor layer by CVD on the one mounting surface on which the crystalline semiconductor substrate is mounted;
Forming an amorphous semiconductor layer having another conductivity type by a CVD method on the one mounting surface on which the crystalline semiconductor substrate is mounted,
In the step of mounting the crystalline semiconductor substrate on the one mounting surface,
The method of manufacturing a solar cell, wherein the one mounting surface is covered with a substantially intrinsic amorphous semiconductor layer. The method includes forming a substantially intrinsic amorphous semiconductor layer by a CVD method on another mounting surface provided on the opposite side of the one mounting surface of the substrate tray. 1. A method for producing a solar cell according to 1. Placing another crystalline semiconductor substrate different from the crystalline semiconductor substrate on the other placement surface;
Forming a substantially intrinsic amorphous semiconductor layer by a CVD method on the other placement surface on which the other crystalline semiconductor substrate is placed;
And a step of forming an amorphous semiconductor layer having another conductivity type by a CVD method on the other placement surface on which the other crystalline semiconductor substrate is placed. The manufacturing method of the solar cell of description.

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