JP2010028809A - 位相同期ループの出力ｖｃｏにおいて５０％デューティサイクルを達成するための方法および装置 - Google Patents

位相同期ループの出力ｖｃｏにおいて５０％デューティサイクルを達成するための方法および装置 Download PDF

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Publication number
JP2010028809A
JP2010028809A JP2009161829A JP2009161829A JP2010028809A JP 2010028809 A JP2010028809 A JP 2010028809A JP 2009161829 A JP2009161829 A JP 2009161829A JP 2009161829 A JP2009161829 A JP 2009161829A JP 2010028809 A JP2010028809 A JP 2010028809A
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Japan
Prior art keywords
duty cycle
clock signal
transistor
differential
signal
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JP2009161829A
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English (en)
Japanese (ja)
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JP2010028809A5 (enExample
Inventor
James Douglas Seefeldt
ジェームズ・ダグラス・シーフェルト
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Honeywell International Inc
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Honeywell International Inc
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Publication of JP2010028809A publication Critical patent/JP2010028809A/ja
Publication of JP2010028809A5 publication Critical patent/JP2010028809A5/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplifiers (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2009161829A 2008-07-11 2009-07-08 位相同期ループの出力ｖｃｏにおいて５０％デューティサイクルを達成するための方法および装置 Pending JP2010028809A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/171,805 US7965118B2 (en) 2008-07-11 2008-07-11 Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop

Publications (2)

Publication Number Publication Date
JP2010028809A true JP2010028809A (ja) 2010-02-04
JP2010028809A5 JP2010028809A5 (enExample) 2012-08-16

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JP2009161829A Pending JP2010028809A (ja) 2008-07-11 2009-07-08 位相同期ループの出力ｖｃｏにおいて５０％デューティサイクルを達成するための方法および装置

Country Status (3)

Country Link
US (1) US7965118B2 (enExample)
EP (1) EP2144373A1 (enExample)
JP (1) JP2010028809A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016059038A (ja) * 2014-09-04 2016-04-21 富士通株式会社 差動信号をシングルエンド信号に変換する回路及び方法
JP2017521009A (ja) * 2014-07-07 2017-07-27 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 高速アナログコンパレータ

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7839195B1 (en) * 2009-06-03 2010-11-23 Honeywell International Inc. Automatic control of clock duty cycle
US20120154021A1 (en) * 2010-12-20 2012-06-21 Amita Chandrakant Patil Integrated circuit and method of fabricating same
KR20130096495A (ko) 2012-02-22 2013-08-30 삼성전자주식회사 반도체 장치의 버퍼 회로
US9148135B2 (en) * 2012-06-26 2015-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Real time automatic and background calibration at embedded duty cycle correlation
US8872562B2 (en) * 2013-03-21 2014-10-28 Kabushiki Kaisha Toshiba Semiconductor device
US9019014B2 (en) * 2013-07-29 2015-04-28 King Fahd University Of Petroleum And Minerals Programmable multi-gain current amplifier
CN108037345B (zh) * 2017-09-27 2020-08-04 北京集创北方科技股份有限公司 信号处理方法、装置、存储介质和处理器
US11165431B1 (en) * 2020-12-09 2021-11-02 Analog Devices, Inc. Techniques for measuring slew rate in current integrating phase interpolator
CN115603710A (zh) * 2022-10-25 2023-01-13 四川和芯微电子股份有限公司（Cn） 占空比校正电路

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JPH07183775A (ja) * 1993-12-22 1995-07-21 Kawasaki Steel Corp 波形整形回路
US5572158A (en) * 1994-02-15 1996-11-05 Rambus, Inc. Amplifier with active duty cycle correction
JPH11127142A (ja) * 1997-10-20 1999-05-11 Fujitsu Ltd タイミング回路
JP2000068797A (ja) * 1998-08-24 2000-03-03 Mitsubishi Electric Corp デューティ比補正回路及びクロック生成回路
US6169434B1 (en) * 1997-09-05 2001-01-02 Rambus Inc. Conversion circuit with duty cycle correction for small swing signals, and associated method
US20050225370A1 (en) * 2004-04-08 2005-10-13 Infineon Technologies Ag Circuit arrangement for regulating a parameter of an electrical signal
JP2007174669A (ja) * 2005-12-21 2007-07-05 Internatl Business Mach Corp <Ibm> 差動クロック信号のデューティサイクル歪みを補正する回路および方法

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US4496856A (en) 1982-07-21 1985-01-29 Sperry Corporation GaAs to ECL level converter
US4533842A (en) 1983-12-01 1985-08-06 Advanced Micro Devices, Inc. Temperature compensated TTL to ECL translator
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US4968905A (en) 1989-08-25 1990-11-06 Ncr Corporation Temperature compensated high speed ECL-to-CMOS logic level translator
JP2549743B2 (ja) 1990-03-30 1996-10-30 株式会社東芝 出力回路
US5034635A (en) 1990-03-30 1991-07-23 Texas Instruments Incorporated Positive to negative voltage translator circuit and method of operation
US6104229A (en) 1996-05-02 2000-08-15 Integrated Device Technology, Inc. High voltage tolerable input buffer and method for operating same
US6563342B1 (en) 2001-12-20 2003-05-13 Honeywell International, Inc. CMOS ECL output buffer
US6535017B1 (en) 2001-12-20 2003-03-18 Honeywell International Inc. CMOS ECL input buffer
GB0413152D0 (en) 2004-06-14 2004-07-14 Texas Instruments Ltd Duty cycle controlled CML-CMOS converter
US7345931B2 (en) * 2005-08-01 2008-03-18 Infineon Technologies Ag Maintaining internal voltages of an integrated circuit in response to a clocked standby mode
KR100715158B1 (ko) 2005-12-13 2007-05-10 삼성전자주식회사 동작특성 및 동작전압을 개선하는 듀티보정 증폭회로
US7688110B2 (en) 2008-01-07 2010-03-30 Honeywell International, Inc. System for providing a complementary metal-oxide semiconductor (CMOS) emitter coupled logic (ECL) equivalent input/output (I/O) circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183775A (ja) * 1993-12-22 1995-07-21 Kawasaki Steel Corp 波形整形回路
US5572158A (en) * 1994-02-15 1996-11-05 Rambus, Inc. Amplifier with active duty cycle correction
US6169434B1 (en) * 1997-09-05 2001-01-02 Rambus Inc. Conversion circuit with duty cycle correction for small swing signals, and associated method
JPH11127142A (ja) * 1997-10-20 1999-05-11 Fujitsu Ltd タイミング回路
JP2000068797A (ja) * 1998-08-24 2000-03-03 Mitsubishi Electric Corp デューティ比補正回路及びクロック生成回路
US20050225370A1 (en) * 2004-04-08 2005-10-13 Infineon Technologies Ag Circuit arrangement for regulating a parameter of an electrical signal
JP2007174669A (ja) * 2005-12-21 2007-07-05 Internatl Business Mach Corp <Ibm> 差動クロック信号のデューティサイクル歪みを補正する回路および方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017521009A (ja) * 2014-07-07 2017-07-27 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 高速アナログコンパレータ
JP2016059038A (ja) * 2014-09-04 2016-04-21 富士通株式会社 差動信号をシングルエンド信号に変換する回路及び方法

Also Published As

Publication number Publication date
US20100007393A1 (en) 2010-01-14
US7965118B2 (en) 2011-06-21
EP2144373A1 (en) 2010-01-13

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