JP2010027678A - Method of manufacturing semiconductor device, and substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that makes specifications of a substrate, mounted with an IC element, common while suppressing an increase in restrictions imposed on the IC element, and to provide a substrate and a method of manufacturing the same. <P>SOLUTION: The method of manufacturing the semiconductor device includes a process of preparing the substrate 50 which has an upper surface and a lower surface facing the opposite side from the upper surface and also has a plurality of posts 40 arrayed to form a plurality of columns longitudinally and a plurality of rows laterally in plan view, a process of fixing the IC element to an upper surface of a first post 40, a process of electrically connecting the IC element 51 to an upper surface of a second post 40 using a gold wire 53, a process of sealing the IC element 51 and gold wire 53 with a mold resin 61, and a process of arranging marks 63a to 63h in an outer peripheral region enclosing the plurality of posts 40. In the process of forming the marks 63a to 63h, the marks 63a to 63h are arranged such that distances between the marks 63a to 63h and posts 40 closest to the marks 63a to 63h are equal to or integral multiples of the pitch of the posts 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, a substrate, and a method for manufacturing the same.

Semiconductor packages are roughly classified into a peripheral type in which external terminals are arranged around the package and an area type in which external terminals are arranged on the lower surface of the package. The peripheral type is a package represented by DIP, SOP, and QFP as shown in FIGS. As shown in FIG. 28 (d), the peripheral type has an IC element 210 mounted on a chip mounting portion called a die pad 201, and the electrodes on the IC element 210 and the leads 203 of the lead frame are connected by a gold wire or the like. Thereafter, a part of the outer periphery of the lead 203 is left, and all other parts are sealed with resin. The portion of the lead 203 inside the resin package is called an internal terminal, and the portion outside the resin package is also called an external terminal.
The area type is a package typified by BGA as shown in FIGS. 29A and 29B and FIGS. 30A and 30B. The device 210 is manufactured by mounting the device 210, electrically connecting the substrate 211 and the IC device 210 with gold wires, solder, or gold bumps, and further sealing the IC device 210 and the like with resin. As shown in FIGS. 29A and 29B, a substrate 211 and an IC element 210 connected by a gold wire 213 is also called a gold wire type BGA.

As shown in FIGS. 30A and 30B, a substrate 211 and an IC element 210 connected by a bump 223 is also called a bump type BGA. In particular, some bump type BGAs do not perform resin sealing as shown in FIGS. 30 (a) and 30 (b). As shown in FIGS. 29A to 30B, the area-type external terminal is not a lead but an electrode (or solder ball) 225 mounted on the lower surface of the substrate 211.
Further, in recent years, as shown in FIGS. 31 (a) to 31 (i), after an electric pole-like terminal 233 and a die pad 235 are formed on a metal plate 231 by electroplating, an IC element 210 is mounted on the die pad 235. Then, the IC element 210 and the terminal 233 are connected by the gold wire 213, and then the resin sealing is performed, and the metal plate 231 is peeled off from the resin molding portion 236 to be cut into individual products. .

  More specifically, in FIGS. 31A and 31B, first, a resist is applied on the metal plate 231 and subjected to exposure and development processing to form a resist pattern 237. Next, as shown in FIG. 31 (c), for example, copper is formed by electroplating on the upper surface of the metal plate 231 exposed from below the resist pattern 237, and the pole-shaped terminals 233 and the die pad 235 are formed. The resist pattern is removed as shown in FIG. Next, as shown in FIG. 31E, an IC element 210 is mounted on a die pad 235 formed by electroplating, and wire bonding is performed. Then, as shown in FIG. 31F, the IC element 210 and the gold wire 213 are sealed with resin. Next, as shown in FIG. 31 (g), the metal plate 231 is peeled off from the resin molding portion 236. Then, as shown in FIGS. 31 (h) and (i), the resin molding portion 236 is cut into individual products to complete the package.

Further, in Patent Document 1, after half-etching one surface of the support portion of the flat lead frame, an IC element is mounted on the die pad of the lead frame, and then wire bonding and resin sealing are performed. Then, a technique for completing a peripheral package is disclosed by grinding the other surface of the support portion whose one surface is half-etched to remove the support portion. Patent Document 2 discloses a technique for improving the versatility of an area-type package by arranging wirings radially from the center of a substrate to the outside in a plan view.
Furthermore, Patent Document 3 discloses a technique for dicing a sealing resin or the like.
JP-A-2-240940 JP 2004-281486 A JP 2006-108343 A

  In the conventional technology, in any of the peripheral type package, the area type package, the package shown in FIGS. 31A to 31I, and the package described in Patent Document 1, a die pad or an interposer is used as the IC element mounting surface. A board is required, depending on the size of the IC element and the number of external outputs from the IC element (ie the number of leads or the number of balls). I needed a photomask. In particular, in a small quantity and a wide variety of products, it is necessary to have a large number of lead frames or substrates or photomasks in accordance with the production of the products, which hinders the reduction of manufacturing costs.

Moreover, in patent document 2, the area type | mold package corresponding to large and small chip size is achieved by arrange | positioning wiring radially from the center of a board | substrate to the outer side. However, in this technique, it is necessary to arrange the pad terminal of the IC element so as to be surely overlapped with the wiring extending radially from the center of the substrate in a plan view, so that the degree of freedom in designing the pad terminal layout is low. That is, the versatility of the package is increased, but on the other hand, the restrictions imposed on the IC element are also increased.
Accordingly, the present invention has been made in view of such circumstances, and a substrate capable of sharing the specifications of a substrate on which an IC element is mounted while suppressing an increase in restrictions imposed on the IC element, and its manufacture It is an object to provide a method, a semiconductor device, and a manufacturing method thereof.

(1) Semiconductor Device Manufacturing Method A semiconductor device manufacturing method according to one embodiment of the present invention includes a first surface and a second surface facing away from the first surface. Preparing a substrate having a plurality of metal columns arranged in a plurality of columns in the vertical direction and a plurality of rows in the horizontal direction, and the first metal column of the plurality of metal columns The step of fixing the IC element on the first surface, and the first surface of the second metal column among the plurality of metal columns and the IC element are electrically connected using a conductive member. A step of sealing the IC element and the conductive member with a resin, and forming a first mark and a second mark in an outer peripheral region surrounding the plurality of metal pillars, In the step of forming a plurality of marks, the first mark and the plurality of metal struts are formed. That is, the distance between the metal strut closest to the first mark is equal to or an integral multiple of the distance between adjacent metal struts of the plurality of metal struts, and the second mark and the plurality of metal struts. The distance between the metal struts closest to the second mark among the metal struts is equal to or an integral multiple of the distance between the adjacent metal struts. A mark is arranged.

  With such a method, a plurality of metal columns can be used as a die pad for mounting an IC element or as an external terminal of the IC element, and a fixed region (hereinafter referred to as an IC element fixing region) that is arbitrarily set. The metal support can be used as a die pad or an external terminal depending on the shape and size of the IC fixing region. For this reason, it is not necessary to prepare a unique die pad, a unique lead frame, and a unique substrate (such as an interposer) for each type of IC element to assemble a semiconductor device. For various types of IC elements, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout (arrangement position) of the pad terminals. Therefore, the manufacturing cost of the semiconductor device can be reduced. Further, for example, a resin cutting line can be recognized based on a plurality of marks, and the resin can be cut along the recognized cutting line.

In the method of manufacturing a semiconductor device according to one aspect of the present invention, in the step of forming the plurality of marks, the first mark is formed on an extension of the first column of the plurality of columns. It is characterized by this.
According to such a method, the formation position of the first mark can be recognized using the metal support column located at the end of an arbitrary row as a mark, and the first mark can be formed at the recognized position. The first mark can be accurately formed at a preset position in the outer peripheral region surrounding the plurality of metal columns. Further, for example, by using a dicing blade, the metal columns arranged in an arbitrary row can be removed by cutting together with the resin, and the metal columns can be prevented from being exposed on the resin cut surface. Since the side surface of the metal support can be covered with resin, and a structure in which moisture or the like hardly enters the contact interface between the metal support and the resin, the reliability of the semiconductor device can be improved.

In the method for manufacturing a semiconductor device according to one aspect of the present invention, in the step of forming the plurality of marks, the second mark is formed on an extension of the first row of the plurality of rows. It is characterized by this.
With such a method, the formation position of the second mark can be recognized using the metal column located at the end of an arbitrary row as a mark, and the second mark can be formed at the recognized position. The second mark can be accurately formed at a preset position in the outer peripheral region surrounding the plurality of metal columns. Further, for example, by using a dicing blade, the metal columns arranged in an arbitrary row can be removed together with the resin, and the metal columns can be prevented from being exposed on the resin cut surface. Since the side surface of the metal support can be covered with resin, and a structure in which moisture or the like hardly enters the contact interface between the metal support and the resin, the reliability of the semiconductor device can be improved.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: measuring a lateral distance between the first mark and the second mark to obtain a first measurement value; A step of calculating a first difference between a design value of a lateral distance between the first mark and the second mark and the first measurement value; and the resin based on the first difference The method further includes a step of recognizing a first cutting line and a step of cutting the resin along the first cutting line.
The method for manufacturing a semiconductor device according to an aspect of the present invention includes a step of measuring a vertical distance between the first mark and the second mark to obtain a second measurement value; A step of calculating a second difference between a design value of a longitudinal distance between the first mark and the second mark and the second measurement value; and the resin based on the second difference The method further includes a step of recognizing a second cutting line and a step of cutting the resin along the second cutting line.

  With such a method, manufacturing errors occur in each process, such as the substrate manufacturing process, die attach process, wire bonding process, resin sealing process, etc., and even if these are accumulated, it is planned. The resin can be cut along the cutting line. For example, even when manufacturing errors are accumulated, the metal struts that overlap the cutting line can be removed together with the resin, and the metal struts can be prevented from being exposed on the resin cut surface.

  In the method for manufacturing a semiconductor device according to one embodiment of the present invention, in the step of forming the first mark and the second mark, at least one of the first mark and the second mark is used. A through hole is formed in the resin in the outer peripheral region. If it is such a method, a mark can be formed by excavating resin from an upper surface to a lower surface, for example using a drill. Since a plurality of marks can be easily formed using general-purpose means such as a drill, it is possible to contribute to a reduction in manufacturing cost of the semiconductor device.

  In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a first surface and a second surface facing the opposite side of the first surface, and includes a plurality of rows and a plurality of rows in a vertical direction in plan view. A plurality of metal struts arranged so as to form a plurality of rows in a direction, and an outer periphery surrounding the plurality of metal struts having a first surface and a second surface facing away from the first surface A first mark and a second mark formed in a region of the first, and a distance between the first mark and a metal column closest to the first mark among the plurality of metal columns is The distance between adjacent metal columns among the plurality of metal columns is equal to or an integral multiple of the distance between the second mark and the metal column closest to the second mark among the plurality of metal columns. The first distance is equal to or an integral multiple of the distance between the adjacent metal columns. Preparing a substrate on which the first mark and the second mark are disposed, fixing an IC element on the first surface of the first metal column among the plurality of metal columns, and the plurality A step of electrically connecting the first surface of the second metal column of the metal columns to the IC element using a conductive member, and sealing the IC element and the conductive member with resin. And the step of sealing with the resin is characterized in that the resin is molded so that the second surfaces of the plurality of marks are exposed from the resin.

  With such a method, a plurality of metal pillars can be used as a die pad for mounting an IC element or as an external terminal of the IC element, and the shape and size of an IC fixing region that is arbitrarily set Accordingly, a plurality of metal columns can be used properly as die pads or external terminals. For this reason, it is not necessary to assemble a semiconductor device by preparing a unique die pad, a unique lead frame, and a unique substrate for each type of IC element. For various types of IC elements, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout of the pad terminals. Therefore, the manufacturing cost of the semiconductor device can be reduced. Further, for example, a resin cutting line can be recognized based on a plurality of marks, and the resin can be cut along the recognized cutting line.

(2) Substrate A substrate according to one embodiment of the present invention includes a first surface and a second surface facing the side opposite to the first surface, and includes a plurality of rows and a plurality of rows in the vertical direction in plan view. A plurality of metal columns arranged so as to form a plurality of rows in a direction; and a first mark and a second mark formed in an outer peripheral region surrounding the plurality of metal columns. The distance between the mark and the metal pillar closest to the first mark among the plurality of metal pillars is equal to or an integral multiple of the distance between adjacent metal pillars of the plurality of metal pillars. The distance between the second mark and the metal strut closest to the second mark among the plurality of metal struts is equal to or an integral multiple of the distance between the adjacent metal struts. The first mark and the second mark are arranged. is there.

  With such a configuration, a plurality of metal pillars can be used as a die pad for mounting an IC element or as an external terminal of the IC element, and the shape and size of an IC fixing region that is arbitrarily set Accordingly, a plurality of metal columns can be used properly as die pads or external terminals. For this reason, it is not necessary to assemble a semiconductor device by preparing a unique die pad, a unique lead frame, and a unique substrate for each type of IC element. For various types of IC elements, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout of the pad terminals. Therefore, the manufacturing cost of the substrate and the manufacturing cost of the semiconductor device using the substrate can be reduced. In the process of manufacturing a semiconductor device using this substrate, for example, a resin cutting line can be recognized based on a plurality of marks, and the resin can be cut along the recognized cutting line.

In the substrate according to one aspect of the present invention, the plurality of metal struts are connected to each other at a part from the first surface of the plurality of metal struts to the second surface of the plurality of metal struts. And a connecting portion.
The board | substrate which concerns on 1 aspect of this invention is further equipped with the support substrate which supports the said 2nd surface of the said several metal support | pillar, The said support substrate and the said several metal support | pillar are joined via an adhesive agent It is characterized by being.
The substrate according to an aspect of the present invention is characterized in that each of the plurality of metal struts is formed in the same shape and the same size.
The substrate according to an aspect of the present invention is characterized in that the plurality of marks are made of the same material as the plurality of metal columns.

(3) Substrate manufacturing method A substrate manufacturing method according to an aspect of the present invention includes a first surface and a second surface facing away from the first surface, and is longitudinal in a plan view. Forming a plurality of metal struts so that a plurality of columns and a plurality of rows can be formed in the horizontal direction, and forming a first mark and a second mark in an outer peripheral region surrounding the plurality of metal struts. In the step of forming the plurality of marks, the distance between the first mark and the metal column closest to the first mark among the plurality of metal columns is the plurality of marks. The distance between the second metal column and the metal column closest to the second mark among the plurality of metal columns is equal to or an integral multiple of the distance between adjacent metal columns among the metal columns. Is equal to or an integral multiple of the distance between the adjacent metal columns The first mark and the second mark are arranged in the above.

  With such a method, a plurality of metal pillars can be used as a die pad for mounting an IC element or as an external terminal of the IC element, and the shape and size of an IC fixing region that is arbitrarily set Accordingly, a plurality of metal columns can be used properly as die pads or external terminals. For this reason, it is not necessary to assemble a semiconductor device by preparing a unique die pad, a unique lead frame, and a unique substrate for each type of IC element. For various types of IC elements, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout of the pad terminals. Therefore, the manufacturing cost of the substrate and the manufacturing cost of the semiconductor device using the substrate can be reduced. In the process of manufacturing a semiconductor device using this substrate, for example, a resin cutting line can be recognized based on a plurality of marks, and the resin can be cut along the recognized cutting line.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) 1st Embodiment FIGS. 1-6 is a figure which shows the manufacturing method of the board | substrate 50 which concerns on 1st Embodiment of this invention. Specifically, FIGS. 1 (a), 2 (a), 4 (a) and 5 are bottom views, and FIGS. 1 (b), 2 (b) and 4 (b) are diagrams. It is an end elevation when 1 (a), FIG. 2 (a), and FIG. 4 (a) are cut along lines X1-X′1, X2-X′2, and X4-X′4, respectively. 3 and 5 (a) to 6 (c) are end views.

  First, a copper plate (that is, Cu strip) 1 as shown in FIGS. 1A and 1B is prepared. The vertical and horizontal dimensions of the copper plate 1 in plan view may be larger than the package outline of the semiconductor device created from the copper plate 1. Moreover, the thickness h of the copper plate 1 is, for example, about 0.10 to 0.30 mm. Next, as shown in FIGS. 2A and 2B, the upper surface of the copper plate 1 is entirely covered with the photoresist 3, and a resist pattern 5 that partially exposes the surface is formed on the lower surface of the copper plate 1. Form. Here, first, for example, a positive type photoresist is applied to the entire lower surface of the copper plate 1, and then, for example, the photoresist is exposed using a photomask M1 shown in FIG. 17A, for example, and then developed into the photoresist. By performing the treatment, a resist pattern 5 is formed on the lower surface of the copper plate 1.

  As shown in FIG. 17A, the photomask M1 has, for example, a regular circular light shielding pattern P1 in plan view, and the light shielding pattern P1 intersects in the vertical direction and the horizontal direction (perpendicular to the vertical direction). In the direction). In the photomask M1, the area other than the light shielding pattern P1 is a transmission area that transmits light. By exposing the positive photoresist using such a photomask M1, the light shielding pattern P1 is transferred to the lower surface of the copper plate 1, and as shown in FIGS. As a result, a resist pattern 5 having a regular circular shape is formed. 2A and 2B, the distance between the centers of the resist pattern 5 (that is, the pitch) is, for example, about 0.5 to 1.0 mm, and the diameter φ is 0.2 to 0.3 mm. Degree.

Next, as shown in FIG. 3, the lower surface of the copper plate 1 is half-etched (that is, etched halfway in the thickness direction of the copper plate 1) using the resist pattern 5 having a circular shape as a mask, and the concave portion 7 is formed. For etching the copper plate 1, for example, a ferric chloride solution is used. Next, the photoresist 3 and the resist pattern 5 are removed from the copper plate 1. 4A and 4B, a metal thin film 9 such as silver (Ag) or palladium (Pd) is plated on the upper surface and the lower surface of the copper plate 1, respectively. The metal thin film 9 may be plated before the copper plate 1 is etched. After the concave portion 7 is formed on the lower surface of the copper plate 1 and the metal thin film 9 is plated, a plurality of regular circles emerges there.
Also, before or after such plating treatment or the like, a support substrate 21 as shown in FIG. 5A is prepared, and an adhesive 23 is applied to the upper surface of the support substrate 21 as shown in FIG. 5B. Apply. The support substrate 21 is, for example, a glass substrate. The adhesive 23 is, for example, a solder resist, an ultraviolet curable adhesive (that is, a UV adhesive), a thermosetting adhesive, or the like. Then, as shown in FIG. 5C, the lower surface of the plated copper plate 1 is pressed against the upper surface of the support substrate 21 to which the adhesive 23 has been applied to adhere.

Next, as shown in FIG. 6A, an opening is made directly above the region where the recess 7 is formed, and the other region (that is, the region where a plurality of regular circles are raised) is opened. A covering resist pattern 31 is formed on the upper surface of the copper plate 1. Here, first, for example, a positive resist is applied to the entire upper surface of the copper plate 1, and then the resist is exposed using, for example, a photomask M1 as shown in FIG. By performing the treatment, a resist pattern 31 is formed on the upper surface of the copper plate 1. By exposing the positive resist using the photomask M1, the light-shielding pattern P1 is transferred to the upper surface of the copper plate 1, and a regular circular resist pattern 31 is formed in plan view.
Next, as shown in FIG. 6B, etching is performed using the regular circular resist pattern 31 as a mask until the copper plate 1 is penetrated from the upper surface side to the lower surface side, so that a plurality of cylindrical electrodes (ie, posts) are formed. ) 40 is formed. After the plurality of posts 40 are formed from the copper plate 1, the resist pattern 31 is removed from the upper surface of the posts 40 as shown in FIG. Thereby, the substrate 50 is completed.

  As shown in FIG. 7, the completed substrate 50 includes a plurality of posts 40 arranged in the vertical direction and the horizontal direction in a plan view, and these posts 40 are attached to the support substrate 21 via an adhesive (not shown). It is joined. After the substrate 50 is completed in this way, the recognition mark 8 is formed by coloring the upper surface (front surface) of the post 40 at a desired position by, for example, an inkjet method or a laser mark. Alternatively, the recognition mark 8 may be formed by applying ink on the upper surface of the post 40 using a dispenser, or by using a printing method. When the recognition mark 8 is formed by the ink jet method, for example, heat-resistant different color ink or different color plating can be adopted as the coloring material. As shown in FIG. 7, a large number of posts 40 made of the copper plate 1 are formed on the support substrate 21, which have the same shape and the same size, and are arranged at equal intervals in the vertical and horizontal directions. By forming the recognition mark 8 on an arbitrary post 40, the IC fixing area on the substrate 50 can be recognized in the process of attaching the IC element to the substrate 50 (ie, the die attaching process), and the IC element is fixed to the IC. It is possible to accurately align the area.

Next, a method for manufacturing the semiconductor device 100 by attaching a bare IC element to the substrate 50 will be described.
8 to 14 are views showing a method of manufacturing the semiconductor device 100 according to the first embodiment of the present invention. More specifically, FIGS. 8A to 11A are plan views, and FIGS. 8B to 11B are FIGS. 8A to 11A along the X-axis direction. It is an enlarged end view when cut. 12 (a) to 14 (a) are bottom views, and FIG. 14 (b) is an enlarged end view when FIG. 14 (a) is cut along the X-axis direction.
8A and 8B, first, an adhesive (not shown) is applied to the upper surface of the post 40 (or the lower surface side of the IC element 51) in the IC fixing region. The adhesive used here is, for example, a thermosetting paste or a sheet. Next, the IC fixing area is recognized using the recognition mark 8 as a mark, and the IC element 51 is aligned with the recognized IC fixing area. Then, in the aligned state, the lower surface of the IC element 51 (the surface opposite to the surface on which the pad terminal of the IC element 51 is formed) is brought into contact with and fixed on the plurality of posts 40 in the IC fixing region ( Die attach process).

  Next, as shown in FIGS. 9A and 9B, the upper surface of the post 40 in a region other than the IC fixing region (that is, a region removed from directly below the IC element 51), and a pad on the surface of the IC element 51. The terminal is connected by, for example, a gold wire 53 (wire bonding process). Here, the post 40 serving as an external terminal may be recognized using the recognition mark 8 as a mark, and one end of the gold wire 53 may be connected to the recognized post 40. According to such a method, the post 40 serving as the external terminal can be accurately recognized from among the plurality of posts 40, and the gold wire 53 can be attached to the recognized post 40 with high accuracy. In the case where the recognition mark 8 is conductive like the post 40, for example, the post 40 may be used as an external terminal by connecting the gold wire 53 to the post 40 on which the recognition mark 8 is formed.

  Next, as shown in FIGS. 10A and 10B, the mold resin 61 is supplied to the upper surface side of the support substrate 21, and above the support substrate 21 including the IC element 51, the gold wire 53, and the post 40. The whole is sealed with mold resin 61 (resin sealing step). In this resin sealing step, for example, a mold (not shown) in which a plurality of IC elements 51 and a plurality of posts 40 are accommodated is placed on the support substrate 21, and the mold resin 61 is placed inside the mold. At a high temperature (for example, 150 ° C. or higher). The mold resin 61 is, for example, a thermosetting epoxy resin. As described above, the support substrate 21 is, for example, a glass substrate, and is a material having a relatively small thermal expansion coefficient. Therefore, even when heat of about 200 ° C. is applied in the resin sealing process, the vertical and horizontal directions in a plan view. Hardly spread. Therefore, it is possible to keep the distance between the adjacent posts 40 substantially constant during the resin sealing process. Further, this resin sealing step may be performed in a vacuum state.

  Next, as shown in FIGS. 11A and 11B, the mold resin 61 including the IC element 51, the gold wire 53, and the post 40 is peeled off from the support substrate. In the case of using an ultraviolet curable adhesive as the adhesive 23, the support substrate may be peeled off after the adhesive strength is reduced by UV (ultraviolet) irradiation. Alternatively, the mold resin 61 containing the IC element 51 may be simply peeled off from the support substrate by applying mechanical force. After peeling off the mold resin 61 from the support substrate, as shown in FIG. 12 (a), it was covered with the metal thin film 9 of the post 40 from the lower surface of the mold resin 61 (that is, the surface peeled off from the support substrate). The surface is exposed. In FIGS. 11A and 11B, the adhesive after the mold resin 61 is peeled off from the support substrate may remain on the mold resin 61 side or may remain on the support substrate side. .

Next, in FIGS. 11A and 11B, a product mark (not shown) or the like is formed on the upper surface (that is, the surface where the terminals are not exposed) of the mold resin 61 using, for example, ink and laser. I write. Then, as shown in FIGS. 11A and 11B, for example, an ultraviolet curable tape (UV tape) 67 is continuously pasted on the entire upper surface of the mold resin 61. Note that the UV tape 67 may be continuously applied not to the upper surface of the mold resin 61 but to the entire lower surface.
Next, as shown in FIGS. 14A and 14B, a dicing blade 75 is applied to the surface (for example, the lower surface) of the mold resin 61 on which the UV tape 67 is not applied, so that the mold resin 61 is removed from the product. Cut according to the outer shape (dicing process). In this dicing process, the mold resin 61 is divided into individual resin packages, and blank portions of the resin that do not become products are cut and removed.

Thereby, as shown in FIGS. 15A and 15B, the semiconductor device 100 including the IC element 51, the post 40, the gold wire 53, and the resin package 62 for sealing them is completed. The lower surface side of the post 40 exposed from the resin package may remain covered with the metal thin film 9, or a solder ball or the like may be placed so as to cover the metal thin film 9.
Table 1 shows an example of the applicable chip size, the number of terminals under the chip (that is, the number of posts 40), the maximum number of external terminals, and the package outline of the semiconductor device 100 according to the first embodiment.

In Table 1, the pitch is a distance between adjacent posts in the same column or the same row, for example, a value indicated by a distance from one post center to the other post center. . Here, the pitch in the same column and the pitch in the same row have the same value, and as shown in Table 1, the value is about 0.5 mm, for example. The applied chip size is the chip size of an IC element sealed in a resin package. The maximum number of external terminals is the maximum number of posts 40 that are resin-sealed by the resin package, and the package outer shape is the vertical or horizontal length of the resin package in plan view. Table 1 exemplifies a case where the shape of the IC element in plan view and the shape of the resin package in plan view are each square.
By the way, in the above dicing process, for example, as shown in FIGS. 14A and 14B, the mold resin 61 is cut along a cutting line (hereinafter referred to as a dicing line) to form individual resin packages. To divide. At this time, if the mold resin 61 is cut at a position overlapping the column or row of the post 40 in plan view, the post 40 at the position overlapping the dicing line is removed, and as a result, the reliability of the semiconductor device 100 can be improved. it can.

  This point will be described in detail. For example, as shown in FIG. 24A, the post 15 (the post 15 is a metal support according to the second embodiment. Here, the post 15 and the post 40 are considered to be the same. The distance between the resin cut surface when the mold resin 61 is cut at a position overlapping with the post 15 and the side surface of the post 15 is La, and the cut surface and the post when the mold resin 61 is cut at a position between the posts 15 When the distance between the 15 side surfaces is Lb, the magnitude relationship between La and Lb is clearly La> Lb. Thus, when the mold resin 61 is cut at a position overlapping the post 15, the side surface of the post 15 functioning as an external terminal can be covered with the mold resin 61 relatively thickly, and the post 40 is exposed on the resin cut surface. You can avoid it. As a result, a structure in which moisture or the like hardly enters the contact interface between the post 40 and the mold resin 61 is obtained.

  Furthermore, as shown in FIG. 24 (b), when the mark 8 serving as a mark for the die attach process is formed on the surface of the post 15 by the ink jet method, the electric field quality contained in the mark 8 together with moisture is indicated by the arrow As shown in the figure, there is a possibility that it will diffuse into the package and cause migration (for example, the wiring material is ionized and moved). However, such a concern can be eliminated by removing the post 15 in which the mark 8 is formed in the dicing process. For this reason, in the dicing process, it is preferable to cut the mold resin 61 at a position overlapping the column or row of the post 40 in plan view.

However, as shown in FIG. 12A, the planar shape of the post 40 exposed on the lower surface of the mold resin 61 is the same shape (in this embodiment, a regular circle). For example, when the mold resin 61 is diced in accordance with the outer shape of the product, a unique shape as a mark is not found on the lower surface of the mold resin 61. In addition, the semiconductor device 100 that has reached the dicing process includes manufacturing errors that have occurred in each process such as the manufacturing process of the substrate 50, the die attach process, the wire bonding process, and the resin sealing process that have been performed before that. There may be. For this reason, for example, the actual pitch of the posts 40 may deviate from the design value, and in the dicing process, the mold resin 61 may not be cut at the position of the column or row.
Therefore, in order to reduce such a possibility, in this embodiment, a dicing line is calculated for each substrate (including resin) set in the dicing apparatus. In order to perform the calculation, as shown in FIG. 12B, for example, marks 63a to 63h are formed at the four corners of the rectangular substrate in plan view.

  Specifically, as shown in FIG. 12B, for example, an outer peripheral region surrounding a plurality of posts 40 arranged in a plan view so as to form a plurality of columns in the vertical direction and a plurality of rows in the horizontal direction (that is, The marks 63a to 63h are formed on the outer periphery of the mold resin 61. Of these marks, the mark 63a is formed on the extension of the leftmost row in plan view, and is formed at a position away from the post 40a located at the upper end of this row by a distance of one pitch. The mark 63d is formed on the extension of the leftmost column in plan view and at a position separated downward by a distance of one pitch from the post 40b positioned at the lower end of the column. Further, the mark 63h is formed on the extension of the rightmost row in plan view, and at a position away from the post 40d located at the upper end of this row by a distance of one pitch. In addition, the mark 63e is formed on the extension of the leftmost column in plan view and at a position separated downward by a distance of one pitch from the post 40c positioned at the lower end of this column.

  Further, the mark 63b is formed on the extension of the uppermost row in plan view, and is formed on the left side by a distance of one pitch from the post 40a located at the left end of this row. In addition, the mark 63g is formed on the extension of the uppermost row in plan view, and is formed at a position on the right side by a distance corresponding to one pitch from the post 40d located at the right end of this row. The mark 63c is formed on the extension of the lowermost row in plan view, and is formed at a position separated to the left by a distance of one pitch from the post 40b located at the left end of this row. Further, the mark 63f is formed on the extension of the lowermost row in plan view, and is formed at a position separated to the right by a distance of one pitch from the post 40c located at the right end of this row.

That is, the mark 63a is formed on the upper side of the post 40a located at the upper left in plan view, and the mark 63b is formed on the left side of the post 40a. The distance between the post 40a (the post closest to the mark 63a among the plurality of posts 40) and the mark 63a (the distance between the centers of the post 40a and the mark 63a) is, for example, one pitch between adjacent posts 40 (adjacent ones). The same value as the distance between the centers of the matching posts 40). The distance between the post 40a (the post closest to the mark 63b among the plurality of posts 40) and the mark 63b (the distance between the centers of the post 40a and the mark 63b) is, for example, one pitch between the adjacent posts 40. It is set to the same value as (distance between the centers of adjacent posts 40). Further, the mark 63c is formed on the left side of the post 40b located at the lower left in plan view, and the mark 63d is formed on the lower side of the post 40a. The distance between the post 40b (the post closest to the mark 63c among the plurality of posts 40) and the mark 63c (the distance between the centers of the post 40b and the mark 63c) is, for example, one pitch (adjacent to the adjacent posts 40). The same value as the distance between the centers of the matching posts 40). The distance between the post 40b (the post closest to the mark 63d among the plurality of posts 40) and the mark 63d (the distance between the centers of the post 40b and the mark 63d) is, for example, one pitch between the adjacent posts 40. It is set to the same value as (distance between the centers of adjacent posts 40). Furthermore, the mark 63e is formed on the lower side of the post 40c located at the lower right in plan view, and the mark 63f is formed on the right side of the post 40c. The distance between the post 40c (the post closest to the mark 63e among the plurality of posts 40) and the mark 63e (the distance between the centers of the post 40c and the mark 63e) is, for example, one pitch (adjacent to the adjacent posts 40). The same value as the distance between the centers of the matching posts 40). The distance between the post 40c (the post closest to the mark 63f among the plurality of posts 40) and the mark 63f (the distance between the centers of the post 40c and the mark 63e) is, for example, one pitch between the adjacent posts 40. It is set to the same value as (distance between the centers of adjacent posts 40). Further, the mark 63g is formed on the right side of the post 40d located at the upper right in plan view, and the mark 63h is formed on the upper side of the post 40d. The distance between the post 40d (the post closest to the mark 63g among the plurality of posts 40) and the mark 63g (the distance between the centers of the post 40d and the mark 63g) is, for example, one pitch (adjacent to the adjacent posts 40). The same value as the distance between the centers of the matching posts 40). The distance between the post 40d (the post closest to the mark 63h among the plurality of posts 40) and the mark 63h (the distance between the centers of the post 40d and the mark 63h) is, for example, one pitch between the adjacent posts 40. It is set to the same value as (distance between the centers of adjacent posts 40). As a result, the marks 63 a to 63 h are arranged on the same line as the outermost column or row of the post 40. Although the example in which the distance between each mark and the nearest post is the same value (same size) as one pitch between adjacent posts 40 has been described, it may be an integer multiple instead of the same value (same size). Good.
The marks 63a to 63h are through holes (that is, pilot holes) formed in the mold resin 61, for example. Such a pilot hole can be formed, for example, by excavating the mold resin 61 from the upper surface to the lower surface using a drill.

Next, a method for calculating a dicing line using these marks 63a to 63h will be described with reference to FIG.
First, the semiconductor device 100 before dicing is set in a dicing device (not shown). In addition, before and after the setting to the dicing apparatus, a design value of the interval between the marks 63a and 63h (that is, the interval [X] shown in FIG. 13A) is input to the dicing apparatus in advance. As shown in Table 2, the design value of the distance [X] is 18.5 mm, for example, and this value is stored in advance in the storage means provided in the dicing apparatus. Here, the storage means is a device having a data holding function such as a hard disk or a flash memory. Further, as shown in Table 2, the cutting intervals (that is, the lateral length of the package outer shape) [X1] [X2] [X3]... Are equal intervals, and the design values thereof vary depending on the type of product. As an example, it is 2.5 mm. This design value is also stored in advance in the storage means. Note that the interval [X8] is the length of the surplus part that is insufficient in length and cannot be used in the product. The interval [X8] is a value determined depending on the values of the intervals [X1] [X2] [X3]... And [X], and is 1.0 mm as an example. This value is also stored in advance in the storage means.

Next, the marks 63a and 63h are picked up by an image pickup device (for example, a CCD or a CMOS image sensor) provided in the dicing device, and the distance between the marks 63a and 63h in the lateral direction, that is, the interval [X] is set. Actually measure. And this measured value is memorize | stored in said memory | storage means. As shown in Table 2, here, it is assumed that the measured value of [X] is, for example, 18.6 mm.
Next, with respect to the interval [X], an arithmetic process for comparing the design value with the measurement value is performed to calculate an error of the measurement value with respect to the design value. Here, as shown in Table 2, the error is, for example, + 0.54%. Then, the above errors are reflected in the design values of the intervals [X1] [X2] [X3]... And [X8], and the intervals [X1] [X2] [X3]. Is calculated. The calculated values shown in Table 2 reflect the above errors, and the values are 2.51 mm for the interval [X1] [X2] [X3]... And 1.01 mm for the interval [X8]. . This calculated value is a numerical value for determining the dicing line. In the present embodiment, this calculated value is stored in the storage means of the dicing apparatus.

  By the same procedure, for example, actual values are calculated for the intervals [Y1] [Y2] [Y3] shown in FIG. 13B, and these calculated values are stored in the storage means of the dicing apparatus. That is, the design value of [Y], which is the distance between the marks 63b and 63c in the vertical direction, and the design values of the cutting intervals [Y1] [Y2] [Y3] are stored in advance in the storage means of the dicing apparatus. . Next, the interval [Y] is actually measured, and the measured value is stored in the storage means. Subsequently, for the interval [Y], an arithmetic process for comparing the design value with the measurement value is performed to calculate an error of the measurement value with respect to the design value. Then, the actual value for [Y1] [Y2] [Y3] is calculated by reflecting the above error on each design value of the interval [Y1] [Y2] [Y3]. Thereafter, the calculated value is stored in the storage unit of the dicing apparatus.

  As described above, after the calculated values of [X1] [X2] [X3]..., [X8], and [Y1] [Y2] [Y3] are stored in the storage means of the dicing apparatus, the above measurement is performed. Dicing processing is performed on the semiconductor device 100 that has been subjected to. For example, in FIG. 13A, when the mold resin 61 is diced in the vertical direction, the dicing device recognizes, for example, the marks 63a and 63d by the imaging device, and the vertical straight line connected by the two marks (that is, A dicing blade is applied to the lower surface of the mold resin 61 so as to overlap the leftmost column of the post 40 in plan view, and this column is cut. That is, all the posts 40 arranged in the leftmost row are cut with a dicing blade (first cut in the vertical direction). Next, a dicing blade is applied to a position moved 2.51 mm to the right with reference to this cut line, and this row is cut (second cut in the vertical direction). Thereafter, the third, fourth,..., And seventh rows are similarly cut.

In the final cutting in the vertical direction, the dicing device recognizes, for example, the marks 63h and 63e, and the left side of the vertical straight line (that is, the rightmost column of the post 40) connected by the two marks. The row is cut by applying a dicing blade to the position moved 1.01 mm to the 8th cut in the vertical direction. Thereby, the cutting in the vertical direction is completed, and the remaining portion is removed from the product.
Similarly, when dicing the mold resin 61 in the horizontal direction, the dicing device recognizes the marks 63b and 63g by the imaging device, and the horizontal straight line connected by the two marks (that is, the uppermost row of the posts 40). ) And a dicing blade to cut this line (first cut in the horizontal direction). Next, the row is cut by applying a dicing blade to the position moved by the calculated value [Y1] downward on the basis of the cut line (second cut in the horizontal direction). Thereafter, similarly, the third and fourth times may be cut.

  In the above embodiment, the dicing line is determined using the distance between the marks 63a and 63h in the horizontal direction as the interval [X] and the distance between the marks 63b and 63c in the vertical direction as the interval [Y]. Showed how to do. If the distance between each mark and the nearest post is equal to or an integral multiple of one pitch between adjacent posts 40, for example, the distance between the marks 63a and 63f in the lateral direction is set as the interval [X]. The dicing line can be determined by using the distance between the vertical direction of the mark 63a and the mark 63f as the interval [Y]. In this case, only two marks 63a and 63f need be provided.

  As described above, according to the first embodiment of the present invention, the post 40 can be used as a die pad for mounting the IC element 51 or as an external terminal of the IC element 51, and is arbitrarily set. Depending on the shape and size of the IC fixing area, the post 40 can be used as a die pad or an external terminal. That is, the post 40 can be a die pad or an external terminal. Therefore, unlike the prior art, there is no need to prepare a unique die pad, a unique lead frame, a unique substrate (such as an interposer) and assemble a semiconductor device for each type of IC element 51. For various types of IC elements 51, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout of the pad terminals. Thereby, the manufacturing cost of a board | substrate and the manufacturing cost of a semiconductor device using this board | substrate can be reduced.

  Further, according to the first embodiment of the present invention, the actual pitch of the post 40 can be grasped based on the design value of the distance between the marks 63a to 63h and the measured value, and the mold resin 61 is cut. The dicing line can be corrected before starting. Thereby, the mold resin 61 can be cut with good reproducibility at a position overlapping the row or column of the post 40 in plan view. Furthermore, as described above, when the mold resin 61 is cut at a position overlapping the row or column of the posts 40 in plan view, a large distance La between the package side surface and the side surface of the post 40 can be secured, It is possible to prevent the post 40 from being exposed on the resin cut surface. The side surface of the post 40 can be covered with the mold resin 61, and a structure in which moisture or the like hardly enters the contact interface between the post 40 and the mold resin 61 can be formed. Thereby, since the possibility of corrosion of the post 40 can be reduced, it is possible to contribute to improving the reliability of the semiconductor device.

  In the first embodiment, the case where the marks 63a to 63h for calculating the dicing line are formed of pilot holes has been described. However, the marks 63a to 63h are not limited to pilot holes. For example, as shown in FIG. 16, the marks 63 a and 63 b may be posts formed on the support substrate 21. Although not shown, the same applies to the marks 63c to 63h. Even in such a configuration, since the lower surfaces of the marks 63a to 63h and the lower surface of the post 40 are aligned at the same height, after the resin sealing step, the marks 63a to 63h are made of the mold resin 61 together with the post 40. It will be exposed from the lower surface. Therefore, for example, the distance between the marks 63a and 63b can be measured, and the actual pitch of the post 40 can be grasped based on the measured value and the design value. Thereby, the effect similar to said 1st Embodiment can be acquired.

  When manufacturing the substrate 50 shown in FIG. 16, it is preferable to use a photomask M2 as shown in FIG. 17B, for example, instead of the photomask M1 as shown in FIG. In addition to the light shielding pattern P1, the photomask M2 has a light shielding pattern P2 similar to the marks 63a to 63h at positions corresponding to the marks 63a to 63h. Using such a photomask M2, the photoresist is exposed to form resist patterns 5 and 31 (see FIGS. 2 and 6), whereby the marks 63a to 63h can be formed from the copper plate 1. According to this method, since the post 40 and the marks 63a to 63h can be formed at the same time, it is possible to reduce processes such as drilling as compared with the first embodiment described above, and contribute to the reduction in the number of processes. Can do.

  In the first embodiment, the case where the photoresist formed on the upper surface and the lower surface of the copper plate 1 is a positive type has been described. However, these are not limited to the positive type, and are negative types. Also good. In the case of using a negative type photoresist, for example, in the photomask M1 shown in FIG. 17A or the photomask M2 shown in FIG. What is necessary is just to reverse the transmissive area | region to make. That is, an inversion mask of the photomask M1 or an inversion mask of the photomask M2 may be used. Thereby, the resist patterns 5 and 31 (see FIGS. 2 and 6) described in the first embodiment can be formed.

(2) Second Embodiment In the first embodiment described above, the case where the substrate 50 including the post 40 is manufactured by bonding the lower surface of the copper plate 1 to the upper surface of the support substrate 21 has been described. And the case where the marks 63a-63h for calculating a dicing line were formed in the mold resin 61 which sealed this board | substrate 50 was demonstrated. However, the semiconductor device manufacturing method, the substrate, and the manufacturing method thereof according to the present invention are not limited to the first embodiment, and may be, for example, the following second embodiment.
In the second embodiment, a substrate manufacturing method will be described first, and then a semiconductor device manufacturing method using the substrate will be described. In the second embodiment, as an example of a substrate manufacturing method, two manufacturing methods shown in FIGS. 18 and 19 will be described. FIG. 18 shows a manufacturing method applying the semi-additive method, and FIG. 19 shows a manufacturing method applying the subtractive method. After describing these two methods of manufacturing a substrate, a method of manufacturing a semiconductor device will be described with reference to FIGS.

FIGS. 18A to 18F are cross-sectional views showing a method (semi-additive method) for manufacturing the substrate 150 according to the second embodiment of the present invention. First, a copper plate 1 is prepared as shown in FIG. Next, as shown in FIG. 18B, photoresists 12a and 12b are applied to the upper and lower surfaces of the copper plate 1, respectively. The photoresists 12a and 12b may be, for example, a positive type or a negative type.
Next, as shown in FIG. 18C, the photoresist is exposed and developed to expose a region where a plurality of cylindrical electrodes (ie, posts) are formed, and to cover the other regions. Patterns 12a 'and 12b' are formed. Here, a resist pattern 12 a ′ is formed on the upper surface of the copper plate 1, and a resist pattern 12 b ′ is formed on the lower surface of the copper plate 1. When the photoresists 12a and 12b are, for example, a negative type, for example, the photomask M1 shown in FIG. On the other hand, when the photoresists 12a and 12b are of a positive type, for example, an inversion mask of the photomask M1 may be used for the exposure of the photoresists 12a and 12b.

Next, as shown in FIG. 18D, a plating layer 13a and a copper layer 1 are formed on the copper plate 1 in a region exposed from the resist patterns 12a ′ and 12b ′ (ie, a region where posts are formed) by, for example, electrolytic plating. 13b is formed. Here, the plating layer 13 a is formed on the upper surface of the copper plate 1 and the plating layer 13 b is formed on the lower surface of the copper plate 1.
In FIG. 18 (d), the plating layers 13a and 13b are each shown in a two-layer structure, but the plating layers 13a and 13b may have a laminated structure of two or more layers or a single-layer structure. For example, the plating layers 13a and 13b may have a three-layer structure made of Ni (lower layer) / Pd (middle layer) / Au (upper layer), a two-layer structure made of Ni (lower layer) / Au (upper layer), or a single layer made of Ag. A layer structure can be adopted.

Next, as shown in FIG. 18E, the resist pattern is removed from the upper surface and the lower surface of the copper plate 1, respectively. Then, as shown in FIG. 18 (f), the concave portion 14a is formed by etching the copper plate 1 from the upper surface side using the plating layer 13a as a mask, and the concave portion is formed by etching the copper plate 1 from the lower surface side using the plating layer 13b as a mask. 14b is formed. Here, the copper plate 1 is half-etched from the upper surface and the lower surface, respectively, to form a plurality of posts 15 and to form a connecting portion 16 that connects these posts 15 in the cross-sectional view in the lateral direction. That is, the etching is stopped before the copper plate 1 is completely etched between the plurality of posts 15 (that is, before penetration). Then, by such half etching, the substrate 150 in a state where the posts are connected to each other in a part from the upper surface to the lower surface of the copper plate 1 is completed.
The half etching of the copper plate 1 shown in FIG. 18 (f) is performed by, for example, dip type or spray type wet etching. For example, a ferric chloride solution or an alkaline etching solution (hereinafter referred to as an alkaline solution) is used as the etching solution.

The concave portions 14a and 14b formed on the upper surface and the lower surface of the copper plate 1 may be formed at the same depth or at different depths, respectively. For example, when the recesses 14a and 14b are formed by spray wet etching, the etching time on the upper surface side is set to twice the etching time on the lower surface side. Thereby, for example, a recess 14a having a depth of 0.1 mm can be formed on the upper surface side, and a recess 14b having a depth of 0.05 mm can be formed on the lower surface side.
In FIG. 18E, before the copper plate 1 is etched, a plating protection photoresist (not shown) may be newly formed on the upper and lower surfaces of the copper plate 1, respectively. In the etching process of the copper plate 1, since the copper plate 1 is etched using the plating layers 13a and 13b covered with the photoresist as a mask, the plating layers 13a and 13b can be protected from the etching solution.

  The plating protecting photoresist may be left as it is even after the recesses 14a and 14b are formed. Thereby, it is possible to continue to protect the plating layers 13a and 13b in the subsequent assembly process. This plating protecting photoresist may be left on both of the plating layers 13a and 13b, or may be left only on the plating layer 13b. When the photoresist is left only on the plating layer 13b, the plating layer 13b can be continuously protected in the subsequent assembly process. Further, such a photoresist for plating protection may be formed not after the etching of the copper plate 1 but after the etching of the copper plate 1. Even with such a configuration, it is possible to continue to protect the plated layers 13a and 13b in the subsequent assembly process.

Next, the other substrate manufacturing method will be described with reference to FIG.
19A to 19G are cross-sectional views illustrating a method (subtractive method) for manufacturing the substrate 150 according to the second embodiment of the present invention. 19, parts having the same configuration as in FIG. 18 are given the same reference numerals, and detailed descriptions thereof are omitted.
First, a copper plate 1 is prepared as shown in FIG. Next, as shown in FIG. 19B, plating layers 13a and 13b are respectively formed on the upper and lower surfaces of the copper plate 1 by, for example, electrolytic plating. Similarly to FIG. 18, in FIG. 19B, the plated layers 13a 'and 13b' are shown in a two-layer structure, but the plated layers 13a 'and 13b' may have a laminated structure of two or more layers or a single layer structure. The plating layers 13a 'and 13b' are, for example, a laminated structure made of Ni (lower layer) / Pd (middle layer) / Au (upper layer), a laminated structure made of Ni (lower layer) / Au (upper layer), or a single layer made of Ag. The structure can be taken.

Next, as shown in FIG. 19C, photoresists 17a and 17b are applied to the upper and lower surfaces of the copper plate 1, respectively. The photoresists 17a and 17b may be positive type or negative type, for example. Then, as shown in FIG. 19D, the photoresists 17a and 17b are exposed and developed to form resist patterns 17a 'and 17b' that cover the areas where the posts are formed and expose the other areas. To do.
Here, a resist pattern 17 a ′ is formed on the upper surface of the copper plate 1, and a resist pattern 17 b ′ is formed on the lower surface of the copper plate 1. When the photoresists 17a and 17b are, for example, positive types, for example, a photomask M1 shown in FIG. In addition, when the photoresists 17a and 17b are, for example, a negative type, an inversion mask of the photomask M1 may be used for the exposure processing of the photoresists 17a and 17b.

Next, the plating layers 13a ′ and 13b ′ are removed by etching using the resist patterns 17a ′ and 17b ′ as masks. As a result, as shown in FIG. 19 (e), patterned plating layers 13 a and 13 b are formed on the upper and lower surfaces of the copper plate 1, respectively.
Here, when the plating layers 13a and 13b are made of Ni / Pd / Au or Ni / Au, for example, aqua regia is used as the etching solution for the plating layer. Further, when the plating layers 13a and 13b are made of Ag, for example, a nitric acid solution is used as an etching solution. After the plating layer is etched in this way, as shown in FIG. 19F, the copper plate 1 is placed on the upper surface side using the resist patterns 17a ′ and 17b ′ and the plating layers 13a and 13b covered therewith as a mask. Etching from the lower surface side. Thereby, while forming the recessed part 14a in the upper surface side of the copper plate 1, the recessed part 14b is formed in the lower surface side.

In the manufacturing method shown in FIG. 19, as in the manufacturing method shown in FIG. 18, the copper plate 1 is half-etched from the upper surface and the lower surface to form a plurality of posts 15, and these posts 15 are viewed in cross section. A connecting portion 16 connected in the horizontal direction is formed. That is, the etching is stopped before the copper plate 1 is completely etched between the plurality of posts 15 (that is, before penetration). Then, by such half etching, the substrate 150 in a state where the posts 15 are connected to each other in a part from the upper surface to the lower surface of the copper plate 1 is completed.
Note that the half etching of the copper plate 1 shown in FIG. 19F is performed by, for example, dipping or spraying wet etching. For example, a ferric chloride solution or an alkaline solution is used as the etching solution. Further, the recesses 14a and 14b formed on the upper surface and the lower surface of the copper plate 1 may be formed at the same depth or at different depths, respectively. For example, when the recesses 14a and 14b are formed by a spray method, a recess having a depth of, for example, 0.1 mm is formed on the upper surface side by adjusting the time required for wet etching in the same manner as the manufacturing method shown in FIG. At the same time, a recess having a depth of 0.05 mm can be formed on the lower surface side.

Next, as shown in FIG. 19G, the resist pattern is removed from the substrate 150. However, this resist pattern removal step is not an essential step in the present embodiment. In this embodiment, resist patterns may be left on both sides of the substrate 150. In FIG. 19G, only the resist pattern on the upper surface side of the substrate 150 may be removed, and the resist pattern on the lower surface side may be left as it is. Thereby, the resist pattern can be used as a protective film for the plating layers 13a and 13b or the plating layer 13b in the subsequent assembly process.
In the manufacturing method shown in FIG. 19, the steps of FIGS. 19C to 19E may be performed by physical processing instead of chemical processing such as wet etching. For example, the plating layers 13a and 13b can be partially removed by a sandblasting process or a process using a cutting tool. The sand blasting process is, for example, a process of partially spraying glass particles to scrape the plating layers 13a and 13b. By adjusting the amount of glass particles sprayed and the spraying pressure at this time, it is shown in FIG. 19 (e). It is possible to process the plated layers 13a and 13b.

FIG. 20A is a diagram illustrating an example of the substrate 150. The configuration of the substrate 150 formed by the method shown in FIGS. 18A to 18F is the same as the configuration of the substrate 150 formed by the method shown in FIGS. 19A to 19G. For example, FIG. 20 shows a three-dimensional view. That is, the substrate 150 includes a plurality of posts 15 arranged in the vertical direction and the horizontal direction, and these posts 15 are connected to each other at a portion (for example, an intermediate portion in the thickness direction) from the upper surface to the lower surface. It has a structure.
After the substrate 150 is completed in this manner, the recognition mark 8 is formed by coloring the upper surface (front surface) of the post 15 at a desired position by, for example, an inkjet method or a laser mark. When the recognition mark 8 is formed by the ink jet method, for example, heat-resistant different color ink or different color plating can be adopted as the coloring material. Alternatively, the recognition mark 8 may be formed by applying ink on the upper surface of the post 40 using a dispenser, or by using a printing method.

Next, a method for manufacturing a semiconductor device by attaching a bare IC element to the substrate 150 will be described.
FIG. 21A to FIG. 22B are cross-sectional views illustrating a method for manufacturing a semiconductor device 200 according to the second embodiment of the present invention. In FIG. 21A, first, the IC fixing area is recognized using the recognition mark 8 as a mark. Next, the IC element 51 is aligned with the recognized IC fixing area, and the IC element 51 is mounted on the plurality of posts 15 in the IC fixing area as shown in FIG. Die attach process). According to such a method, the IC element 51 can be accurately aligned with the IC fixing region, and the IC element 51 can be attached to the substrate 150 with little displacement. In this die attach step, the IC element 51 and the post 15 are attached with the adhesive 23. The adhesive 23 used is, for example, a thermosetting paste or a sheet.

Next, as shown in FIG. 21C, the post 15 is provided on the upper surface of the post 15 in the region other than the IC fixing region (that is, the region outside the IC element) and the active surface of the IC element 51. The pad terminal is connected by, for example, a gold wire 53 (wire bonding process). Here, the post 15 serving as an external terminal may be recognized using the recognition mark 8 as a mark, and one end of the gold wire 53 may be connected to the recognized post 15.
Next, as shown in FIG. 21D, the entire upper portion of the substrate 150 including the IC element 51, the gold wire 53, and the post 15 is sealed with a mold resin 61 (resin sealing step). The mold resin 61 is, for example, a thermosetting epoxy resin. In this resin sealing step, for example, a cavity is placed on the upper surface side of the substrate 150 including the IC element 51 and the like, and the inside thereof is decompressed, and the mold resin 61 is supplied into the decompressed cavity. By supplying the resin under such a reduced pressure, the mold resin 61 can be supplied into the cavity with good fillability, and as shown in FIG. .

  Thereafter, the connecting portion 16 connecting the posts 15 is etched away from the lower surface side. Etching of the connecting portion 16 is performed using, for example, a ferric chloride solution or an alkaline solution, as in the case where the recesses 14a and 14b are formed. As a result, as shown in FIG. 21 (e), the adjacent posts 15 can be electrically separated from each other, and the posts 15 connected to the gold wire 53 can be used as electrically independent external terminals. Become. Since each post 15 has its upper surface portion fixed by the mold resin 61, its position is maintained even after the connecting portion is removed.

  When a photoresist (not shown) is left on the lower surface side as a protective film for the plating layer 13b, the photoresist is removed after etching the connecting portion. Further, when the plating layer 13b is Ag plating, the Ag plating may be removed and another plating process may be performed. That is, the Ag plating may be removed, and then another type of plating may be reapplied as the plating layer 13b. Examples of other types of plating include Ni / Pd / Au, Ni / Au, and solder. Such re-attachment of the plating layer 13b may be performed after removing the photoresist when the photoresist is formed on the lower surface side, and it is connected when the photoresist is not formed on the lower surface side. This may be done after removing the part.

Next, as shown in FIG. 12B, for example, marks 63a to 63h for calculating dicing lines are formed. In the second embodiment, as in the first embodiment, the marks 63a to 63h may be pilot holes, for example. The pilot hole is formed by excavating the mold resin 61 from the upper surface to the lower surface using, for example, a drill. Then, before performing the dicing process, the dicing line is corrected using the marks 63a to 63h. The specific method is as described with reference to FIGS. 13A and 13B and Table 2 in the first embodiment.
After correcting the dicing line, for example, as shown in FIG. 22, a dicing blade 75 is applied to the mold resin 61 to cut the mold resin 61 in accordance with the outer shape of the product (dicing process). Here, for example, the mold resin 61 is cut along a dicing line corrected based on the calculated values in Table 2. As a result, the mold resin 61 is divided into individual resin packages, and the blank portion of the resin that does not become a product is cut and removed. Thereby, the semiconductor device 200 is completed.

  In this dicing step, for example, as shown in FIG. 22, it is preferable to cut the post 15 by using a dicing blade 75 that is larger than the terminal size (that is, wider than the post 15). Thereby, the post 15 at a position overlapping the dicing line can be more reliably excluded from the resin package. FIG. 22 shows the case where dicing is performed without attaching UV tape or the like to the entire upper surface of the mold resin 61, but this is merely an example. Also in the second embodiment, similarly to the first embodiment, UV tape may be applied to the entire upper surface of the mold resin 61, and dicing may be performed in this state. In that case, as in the first embodiment, the dicing blade 75 may be applied to the surface of the mold resin 61 on which the UV tape is not applied, and the mold resin 61 may be cut according to the outer shape of the product.

  As described above, according to the second embodiment of the present invention, a plurality of posts 15 can be used as a die pad for mounting the IC element 51 or as an external terminal of the IC element 51. Depending on the shape and size of the IC fixing region set to, a plurality of posts 15 can be used properly as die pads or external terminals. Therefore, it is not necessary to prepare a specific die pad, a specific lead frame, and a specific substrate for each type of IC element 51 to assemble a semiconductor device. For various types of IC elements 51, it is possible to share the specifications of the board used as the element mounting and external terminals without imposing restrictions on the layout of the pad terminals. Thereby, the manufacturing cost of a board | substrate and the manufacturing cost of a semiconductor device using this board | substrate can be reduced.

  Further, according to the second embodiment of the present invention, the actual pitch of the post 15 can be grasped based on the design value of the distance between the marks 63a to 63h and the measured value, and the mold resin 61 is cut. The cutting line can be corrected before doing. Thereby, the mold resin 61 can be cut with good reproducibility at a position overlapping the row or column of the post 15 in plan view. Further, as described above, when the mold resin 61 is cut at a position overlapping the row or column of the post 15 in plan view, a large distance La between the package side surface and the side surface of the post 15 can be secured. It is possible to prevent the post 15 from being exposed to the resin cut surface. The side surface of the post 15 can be covered with the mold resin 61, and a structure in which moisture or the like hardly enters the contact interface between the post 15 and the mold resin 61 can be formed. Thereby, since the possibility of corrosion of the post 40 can be reduced, it is possible to contribute to improving the reliability of the semiconductor device.

  In the second embodiment, the case where the marks 63a to 63h for calculating the dicing line are formed of pilot holes has been described. However, the marks 63a to 63h are not limited to pilot holes. For example, as shown in FIG. 23, the marks 63 a and 63 b may be posts formed on the lower surface side of the substrate 150. Although not shown, the same applies to the marks 63c to 63h. Even with such a configuration, the lower surfaces of the marks 63a to 63h and the lower surface of the post 15 can be made to be the same height. For example, as shown in FIGS. 63 a to 63 h can be exposed on the lower surface of the mold resin 61.

Therefore, even after the resin sealing step, the distance between the mark 63a and the mark 63b and the distance between the mark 63b and the mark 63c can be measured, and the post is based on the measured value and the design value. Fifteen actual pitches can be grasped. Thereby, the effect similar to said 1st Embodiment can be acquired.
When manufacturing the substrate 150 shown in FIG. 23, for example, a photomask M2 as shown in FIG. 17B may be used instead of the photomask M1 shown in FIG. Using the photomask M2 (or an inverted mask of the photomask M2), the resist patterns 12a ′ and 12b ′ shown in FIG. 18 and the resist patterns 17a ′ and 17b ′ shown in FIG. 19 (see, for example, FIG. 19). ), The marks 63a to 63h can be formed from the copper plate 1. According to this method, since the post 15 and the marks 63a to 63h can be formed at the same time, it is possible to reduce processes such as drilling as compared with the second embodiment described above, and contribute to the reduction in the number of processes. Can do.

  In the first and second embodiments described above, for example, as shown in FIGS. 13A and 13B, the lower surface of the mold resin 61 is arranged on the same line as the outermost column or row. Thus, the case where the marks 63a to 63h are formed has been described. However, in the present invention, the arrangement rule of the marks 63a to 63h is not limited to this. For example, as shown in FIG. 25, marks 63a, 63b, etc. may be formed at positions away from the row or column extension of the post 15. Even with such a configuration, the distance between the mark 63a and the post 15 and the distance between the mark 63b and the post 63b can each be an integral multiple of the pitch of the post 15. If the dicing device recognizes this integer multiple value, the mold resin 61 can be cut based on the marks 63a, 63b and the like. Therefore, for example, the mold resin 61 can be cut on the basis of the marks 63a, 63b, etc. by storing the above integral multiple values in the storage means of the dicing apparatus.

(3) Third Embodiment In the second embodiment described above, for example, as shown in FIGS. 18 and 19, the copper plate 1 is etched simultaneously from both the upper surface and the lower surface using the plating layers 13a and 13b as a mask. explained. However, in the present invention, the copper plate 1 is not etched from both the upper surface and the lower surface at the same time, but, for example, the copper plate 1 is etched from the lower surface using a resist pattern as a mask, thereby completing the substrate while leaving the connection portion. Also good. In the third embodiment, such a form will be described.

26A to 26F are cross-sectional views illustrating a method for manufacturing the substrate 160 according to the third embodiment of the present invention. First, a copper plate 1 is prepared as shown in FIG. Next, the 1st photoresist 27 is apply | coated to the upper surface and lower surface of the copper plate 1, respectively. This photoresist 27 may be, for example, a positive type or a negative type.
Next, the photoresist 27 applied on the upper surface of the copper plate 1 is exposed and developed to form a resist pattern 27a that covers the region where the post is to be formed and exposes other regions. As shown in FIG. 26A, here, a resist pattern 27 a is formed only on the upper surface of the copper plate 1. The unexposed photoresist 27 is left as it is on the lower surface of the copper plate 1. Here, when the photoresist 27 is, for example, a positive type, the photomask M1 shown in FIG. 17A may be used for the exposure process. Further, when the photoresist 27 is, for example, a negative type, an inversion mask of the photomask M1 may be used for the exposure process.

  Next, the upper surface of the copper plate 1 is etched using the resist pattern 27a as a mask. Thereby, the concave portion 29 is formed on the upper surface side of the copper plate 1. By forming the recesses 29, a plurality of posts 15 are formed on the upper surface of the copper plate 1. Further, in this etching process, since the concave portion 29 is formed only on the upper surface of the copper plate 1, the connecting portion 16 for connecting the plurality of posts 15 in the cross-sectional view in the lateral direction is left on the lower surface side of the copper plate 1. That is, the etching is stopped before the copper plate 1 is completely etched between the plurality of posts 15 (that is, before penetration). By such half etching, the posts 15 are connected to each other in a part from the bottom surface of the recess 29 to the lower surface of the copper plate 1.

Note that half etching of the copper plate 1 shown in FIG. 26B is performed by, for example, dipping or spraying wet etching. For example, a ferric chloride solution or an alkaline solution is used as the etching solution. The depth of the recess 29 formed on the upper surface of the copper plate 1 is, for example, d = 0.4 × h to 0.6 × h, where h is the thickness of the copper plate 1 and d is the depth of the recess 29. Degree. For example, a recess having a depth of 0.1 mm is formed on the upper surface side of the copper plate 1 by adjusting the time required for wet etching.
Next, the resist pattern 27a is removed from the upper surface of the copper plate 1, and the photoresist 27 is removed from the lower surface. Thereby, as shown in FIG.26 (c), the upper surface and lower surface of the copper plate 1 are exposed. Next, a second photoresist is applied to the upper and lower surfaces of the copper plate 1 in which the recesses 29 are formed. This second photoresist may be positive or negative, for example.

Next, as shown in FIG. 26 (d), the second photoresist applied to the upper and lower surfaces of the copper plate 1 is exposed and developed to expose the region where the post is to be formed. Resist patterns 37a and 37b exposing the regions are formed on the upper and lower surfaces of the copper plate 1, respectively. That is, the resist pattern 37 a is formed so as to cover the bottom surface and the side surface of the recess 29, and the resist pattern 37 b is formed on the lower surface of the copper plate 1 and facing the recess 29. Here, when the second photoresist is, for example, a positive type, the photomask M1 shown in FIG. 17A may be used for the exposure process. Further, when the photoresist 27 is, for example, a negative type, an inversion mask of the photomask M1 may be used for the exposure process.
Further, in the step of forming the resist pattern 37a, the resist pattern 37a is added to the inside of the concave portion 29 so as to cover a region along the opening end of the concave portion 29 (that is, a region that becomes an outer peripheral portion of the post in plan view). It is preferable to form. Thereby, a plating layer can be formed so as not to protrude from the upper surface of the post 15 in a later step. As a result, the generation of burrs at the end of the plating layer can be suppressed, and the rigidity of the plating layer can be improved. For example, if the generation of burrs is suppressed, there is an advantage that the mold resin can easily enter the recess 29 in a later step.

Next, as shown in FIG. 26E, plating layers 43a and 43b are formed on the copper plate 1 in the regions exposed from the resist patterns 37a and 37b (that is, regions where posts are formed) by, for example, electrolytic plating. Form. Here, the plating layer 43 a is formed on the upper surface of the copper plate 1 and the plating layer 43 b is formed on the lower surface of the copper plate 1. In FIG. 26 (e), the plated layers 43a and 43b are each shown as a single layer structure, but the plated layers 43a and 43b may be a single layer structure or a laminated structure of two or more layers. For example, the plating layers 43a and 43b are formed of a three-layer structure composed of Ni (lower layer) / Pd (middle layer) / Au (upper layer), a two-layer structure composed of Ni (lower layer) / Au (upper layer), or a single layer composed of Ag. A layer structure can be adopted.
Next, as shown in FIG. 26E, the resist pattern is removed from the upper surface and the lower surface of the copper plate 1, respectively. Thereby, the substrate 160 in a state where the plurality of posts 15 are connected to each other on the lower surface side of the copper plate 1 is completed.

Next, the case where the semiconductor device 300 is manufactured by attaching bare IC elements and passive elements to the substrate 160 will be described.
27A to 27E are cross-sectional views illustrating a method for manufacturing a semiconductor device 300 according to the third embodiment of the present invention. In FIG. 27A, first, the recognition mark 8 is formed by coloring the upper surface (front surface) of the post 15 at a desired position by the same method as in the first and second embodiments.
Next, in FIG. 27B, the IC fixing area is recognized using the recognition mark 8 as a mark, and the IC element 51 is aligned with the recognized area. Then, in the aligned state, the IC element 51 is attached on the post 15 in the IC fixing region (die attach process). According to such a method, the IC element 51 can be accurately aligned with the IC fixing region, and the IC element 51 can be attached to the substrate 160 with little misalignment. In this die attach step, the IC element 51 and the post 15 are attached with the adhesive 23.

Next, as shown in FIG. 27C, the post 15 is provided on the upper surface of the post 15 in the region other than the IC fixing region (that is, the region deviated from directly below the IC element) and the active surface of the IC element 51. The pad terminal is connected by, for example, a gold wire 53 (wire bonding process). Here, the post 15 serving as an external terminal may be recognized using the recognition mark 8 as a mark, and one end of the gold wire 53 may be connected to the recognized post 15.
Next, as shown in FIG. 27D, the entire upper portion of the substrate 160 including the IC element 51, the gold wire 53, and the post 15 is sealed with a mold resin 61 (resin sealing step). In this resin sealing step, for example, a cavity is placed on the upper surface side of the substrate 160 including the IC element 51 and the like, the inside thereof is decompressed, and the mold resin 61 is supplied into the decompressed cavity. By supplying the resin under such reduced pressure, the mold resin 61 can be supplied into the cavity with good fillability, and the recess 29 can be filled with the mold resin 61 without gaps as shown in FIG. .

Thereafter, the connecting portion 16 connecting the posts 15 is removed by etching from the lower surface side of the substrate 160. Etching of the connecting portion 16 is performed using, for example, a ferric chloride solution or an alkaline solution, as in the case where the concave portion 29 is formed. As a result, as shown in FIG. 27E, adjacent posts 15 can be electrically separated from each other, and the posts 15 in regions other than the IC fixing region are used as electrically independent external terminals, respectively. It becomes possible. Since each post 15 has its upper surface portion fixed by the mold resin 61, its position is maintained even after the connecting portion is removed.
The subsequent steps are the same as those in the first and second embodiments. For example, by a dicing process as shown in FIG. 22, the mold resin 61 is divided into individual resin packages, and the blank portion of the resin that does not become a product is cut and removed. Thereby, the semiconductor device 300 is completed. According to the third embodiment of the present invention, the same effects as those of the first and second embodiments can be obtained.

  In the first to third embodiments, the lower surface of the IC element 51 (the surface opposite to the surface on which the pad terminal is formed) is fixed so as to face the post 40 and the gold wire 53 is used. Although the case where the pad terminal of the IC element 51 and the post 40 are connected is shown, the present invention is not limited to this. For example, the IC element 51 may be configured such that the surface on which the pad terminal is formed faces the post 40 and the pad terminal and the post 40 are connected using bumps provided on the pad terminal. The same applies to the connection between the pad terminal and the post 15. In this case, the bump may be a stud bump, a solder bump, an Au bump formed by electrolytic plating, or the like.

The figure which shows the manufacturing method of the board | substrate 50 which concerns on 1st Embodiment (the 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the substrate 50 according to the first embodiment. FIG. 6 is a diagram (part 3) illustrating the method for manufacturing the substrate 50 according to the first embodiment. FIG. 4 is a diagram (part 4) illustrating a method for manufacturing the substrate 50 according to the first embodiment. FIG. 5 is a diagram illustrating a method for manufacturing a substrate 50 according to the first embodiment (No. 5). FIG. 6 is a view (No. 6) illustrating the method for manufacturing the substrate 50 according to the first embodiment. The figure which shows an example of the board | substrate 50 which concerns on 1st Embodiment. FIG. 2 is a diagram (part 1) illustrating a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment (No. 4). FIG. 5 is a diagram illustrating a method for manufacturing the semiconductor device 100 according to the first embodiment (No. 5). FIG. 6 is a view (No. 6) illustrating the method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 7 is a view showing the method for manufacturing the semiconductor device 100 according to the first embodiment (No. 7). FIG. 6 shows a configuration example of a semiconductor device 100. The figure which shows the other structural example of the board | substrate 50. FIG. The figure which shows an example of the photomasks M1 and M2. The figure which shows the manufacturing method of the board | substrate 150 which concerns on 2nd Embodiment (the 1). The figure which shows the manufacturing method of the board | substrate 150 which concerns on 2nd Embodiment (the 2). The figure which shows an example of the board | substrate 150 which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device 200 which concerns on 2nd Embodiment (the 1). FIG. 6 is a diagram (No. 2) illustrating a method for manufacturing the semiconductor device 200 according to the second embodiment. The figure which shows the other structural example of the board | substrate 150. FIG. The figure which shows an example of a dicing position. The figure which shows an example of arrangement | positioning of the marks 63a and 63b. The figure which shows the manufacturing method of the board | substrate 250 which concerns on 3rd Embodiment. The figure which shows the manufacturing method of the semiconductor device 300 which concerns on 3rd Embodiment. The figure which shows a prior art example. The figure which shows a prior art example. The figure which shows a prior art example. The figure which shows a prior art example.

Explanation of symbols

  1 Copper plate, 3, 12a, 12b, 17a, 17b, 27 Photoresist, 5, 12a ′, 12b ′, 17a ′, 7b ′, 27a, 37a, 37b Resist pattern, 7, 14a, 14b Recess, 8 Recognition mark, 9, 13a, 13a ′, 13b, 13b ′, 43a, 43b Plating layer, 15, 40 Post (an example of a metal support), 16 connection portion, 21 support substrate, 23, 67 adhesive, 29 recess, 50, 150, 160 substrate, 51 IC element, 53 gold wire (an example of a conductive member), 61 mold resin, 63a-63h mark, 75 blade, 100, 200, 300 semiconductor device, M1, M2 photomask, P1, P2 light shielding pattern

Claims (13)

A plurality of metals having a first surface and a second surface facing away from the first surface, and arranged in a plurality of rows in a vertical direction and a plurality of rows in a horizontal direction in a plan view A step of preparing a substrate with a support;
Fixing an IC element to the first surface of the first metal column among the plurality of metal columns;
Electrically connecting the first surface of the second metal column of the plurality of metal columns and the IC element using a conductive member;
Sealing the IC element and the conductive member with a resin;
Forming a first mark and a second mark in an outer peripheral region surrounding the plurality of metal columns,
In the step of forming the plurality of marks, the distance between the first mark and the metal column closest to the first mark among the plurality of metal columns is the distance between the plurality of metal columns. The distance between the adjacent metal struts is equal to or an integral multiple of the distance between the adjacent metal struts, and the distance between the second mark and the metal strut closest to the second mark among the plurality of metal struts is the adjacent metal strut A method of manufacturing a semiconductor device, wherein the first mark and the second mark are arranged so as to be equal to or an integral multiple of a distance between columns. In the step of forming the plurality of marks,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first mark is formed on an extension of a first column of the plurality of columns. In the step of forming the plurality of marks,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the second mark is formed on an extension of a first row of the plurality of rows. Measuring a lateral distance between the first mark and the second mark to obtain a first measurement value;
Calculating a first difference between a design value of a lateral distance between the first mark and the second mark and the first measurement value;
Recognizing a first cutting line of the resin based on the first difference;
Cutting the resin along the first cutting line;
The method of manufacturing a semiconductor device according to claim 1, further comprising: Measuring a longitudinal distance between the first mark and the second mark to obtain a second measurement value;
Calculating a second difference between a design value of a longitudinal distance between the first mark and the second mark and the second measurement value;
Recognizing a second cutting line of the resin based on the second difference;
Cutting the resin along the second cutting line;
The method for manufacturing a semiconductor device according to claim 1, further comprising:   In the step of forming the first mark and the second mark, a through hole is formed in the resin in the outer peripheral region as at least one of the first mark or the second mark. The method for manufacturing a semiconductor device according to claim 1, wherein: A plurality of metal columns having a first surface and a second surface facing away from the first surface and arranged in a plan view so as to form a plurality of columns in the vertical direction and a plurality of rows in the horizontal direction And a first mark and a second mark formed in an outer peripheral region having a first surface and a second surface facing away from the first surface and surrounding the plurality of metal columns. The distance between the first mark and the metal column closest to the first mark among the plurality of metal columns is the distance between adjacent metal columns among the plurality of metal columns. The distance between the second mark and the metal strut closest to the second mark among the plurality of metal struts is equal to the distance between the adjacent metal struts. Alternatively, a substrate on which the first mark and the second mark are arranged so as to be an integral multiple is prepared. And a step,
Fixing an IC element to the first surface of the first metal column among the plurality of metal columns;
Electrically connecting the first surface of the second metal column of the plurality of metal columns and the IC element using a conductive member;
Sealing the IC element and the conductive member with a resin,
In the step of sealing with the resin, the resin is molded so that the second surfaces of the plurality of marks are exposed from the resin. A substrate for fixing an IC element,
A plurality of metals having a first surface and a second surface facing away from the first surface, and arranged in a plurality of rows in a vertical direction and a plurality of rows in a horizontal direction in a plan view A strut,
A first mark and a second mark formed in an outer peripheral region surrounding the plurality of metal columns,
The distance between the first mark and the metal column closest to the first mark among the plurality of metal columns is equal to the distance between adjacent metal columns of the plurality of metal columns or The distance between the second mark and the metal strut closest to the second mark among the plurality of metal struts is an integral multiple or an integral multiple of the distance between the adjacent metal struts. The substrate is characterized in that the first mark and the second mark are arranged so as to be.   And a connecting portion that connects the plurality of metal struts to each other in a part from the first surface of the plurality of metal struts to the second surface of the plurality of metal struts. The substrate according to claim 8. A support substrate for supporting the second surface of the plurality of metal columns,
The substrate according to claim 8, wherein the support substrate and the plurality of metal columns are bonded via an adhesive.   11. The substrate according to claim 8, wherein each of the plurality of metal struts has the same shape and the same size.   The substrate according to any one of claims 8 to 11, wherein the plurality of marks are made of the same material as the plurality of metal columns. A method of manufacturing a substrate for fixing an IC element,
A first surface and a second surface facing away from the first surface, and a plurality of metal columns so as to form a plurality of columns in the vertical direction and a plurality of rows in the horizontal direction in plan view. Forming, and
Forming a first mark and a second mark in an outer peripheral region surrounding the plurality of metal columns,
In the step of forming the plurality of marks, the distance between the first mark and the metal column closest to the first mark among the plurality of metal columns is the distance between the plurality of metal columns. The distance between the adjacent metal struts is equal to or an integral multiple of the distance between the adjacent metal struts, and the distance between the second mark and the metal strut closest to the second mark among the plurality of metal struts is the adjacent metal strut A method for manufacturing a substrate, wherein the first mark and the second mark are arranged so as to be equal to or an integral multiple of a distance between columns.

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