JP2011103371A - Method of manufacturing semiconductor device, substrate, and array of the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a reduction in the number of semiconductor devices collected from a semiconductor device array when recognition marks for die-attachment in a die-attachment process are formed in a first region containing posts (electrodes) electrically connected to IC elements and the recognition marks require different surface states from other posts, wherein the posts thus changed in its surface states are unsuitable for die-attachment and wire bonding. <P>SOLUTION: Marks 7 for die-attachment are disposed in a second region 20b not containing IC elements 51 or posts 40 acting as electrodes. Thus a packing density can be increased in a first region 20a, so that a larger number of semiconductor devices 100 can be collected from a single semiconductor device array 300. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method, a substrate, and an array of semiconductor devices.

  Semiconductor devices equipped with an IC element as a semiconductor element are roughly classified into a peripheral type in which external terminals are arranged around the package and an area type in which external terminals are arranged on the lower surface of the package. The peripheral type is a package represented by DIP, SOP, and QFP as shown in FIGS. As shown in FIG. 24D, in the peripheral type, an IC element 210 is mounted on a chip mounting portion called a die pad 201, and a pad electrode provided in the IC element 210 and a lead 203 of a lead frame are connected by a gold wire or the like. Thereafter, a part of the outer peripheral portion of the lead 203 is left and all the others are sealed with resin. The portion of the lead 203 inside the resin package is called an internal terminal, and the portion outside the resin package is also called an external terminal.

  The area type is a package typified by BGA as shown in FIGS. 25A and 25B and FIGS. 26A and 26B. It is manufactured by mounting the element 210, electrically connecting the substrate 211 and the IC element 210 with a gold wire, solder, or gold bump, and further sealing the IC element 210 or the like with resin. As shown in FIGS. 25A and 25B, a substrate 211 and an IC element 210 connected by a gold wire 213 is also called a gold wire type BGA. Here, FIG.25 (b) is sectional drawing of Fig.25 (a).

  In addition, as shown in FIGS. 26A and 26B, the substrate 211 and the IC element 210 connected by the bump 223 is also called a bump type BGA. In particular, some bump type BGAs do not perform resin sealing as shown in FIGS. 26 (a) and 26 (b). Here, FIG.26 (b) is sectional drawing of Fig.26 (a). As shown in FIGS. 26A and 26B, the area-type external terminals are not leads but electrodes (or solder balls) 225 mounted on the back surface of the substrate 211. The above-described structure is typically formed by forming and then dividing an array of semiconductor devices in which a plurality of IC elements are mounted on a substrate.

  Here, in the following description, a region serving as a mark for mounting a semiconductor element or an electronic component is defined as a recognition mark. As a method of mounting a plurality of IC elements on a substrate, as shown in FIG. 27 (FIG. 1 in Patent Document 1) included in Patent Document 1, the outer periphery of the mother substrate includes the same composition as the mother substrate, In addition, it includes an ablation region 103 having a ceramic insulating layer 104 having the same main component as the main substrate 101 and a different color tone, and the ablation region 103 penetrates the ablation region 103 and passes through the mother substrate 101. The opening pattern 104a is exposed on the surface. By using this technique, it is possible to perform alignment when performing dicing using the opening pattern 4a. In addition, in the region where the electronic component is mounted, a mounting portion 5 having a concave shape is typically provided. The electronic component is disposed inside, around, or the like of the recess provided in the mounting unit 5.

  Also, as shown in Patent Document 2, after forming a noble metal on a copper substrate as a mask, etching is performed to form a post connected by a part of the copper substrate, and forming a recognition mark, a dicing mark, etc. It is disclosed. Hereinafter, description will be made with reference to the drawings. 28A to 28E are cross-sectional views showing the manufacturing process after the post is formed, and FIG. 29 is a plan view in a state where the recognition mark and the dicing mark are formed.

  As shown in FIG. 28A, first, the recognition mark 8 is formed on the surface of the substrate 10. The recognition mark 8 is formed using, for example, an ink jet method. The recognition mark 8 is disposed outside the IC fixing area, for example.

  Next, as shown in FIG. 28 (b), the IC fixing area is recognized using the recognition mark 8 as a mark, and the IC element 11 is aligned with the recognized IC fixing area. IC elements 11 are mounted on a plurality of posts 5. In this die attach (IC element 11 mounting) step, the IC element 11 and the post 5 are attached with an adhesive 12. The adhesive 12 used is, for example, a thermosetting paste or a sheet. FIG. 29 is a plan view corresponding to this state.

  Next, as shown in FIG. 28 (c), the upper surface of the post 5 in a region off from just below the IC element 11 and the pad terminal provided on the active surface of the IC element 11 are connected with, for example, a gold wire 13. Connecting. Here, the post 5 serving as the external terminal is recognized using the recognition mark 8 as a mark, and one end of the gold wire 13 is connected to the recognized post 5.

  Next, as shown in FIG. 28 (d), the entire surface of the substrate 10 including the IC element 11, the gold wire 13 and the post 5 to which the IC element 11 is fixed is sealed with a mold resin 14. The mold resin 14 is, for example, a thermosetting epoxy resin. Thereafter, the connecting portion 6 connecting the posts 5 is removed by etching from the side opposite to the surface on which the IC element 11 is mounted. Thus, as shown in FIG. 28 (e), adjacent posts 5 can be electrically separated from each other, and the posts 5 connected to the gold wire 13 can be used as electrically independent external terminals. Become. Then, dicing is performed based on position information obtained by referring to the dicing marks 9 before sealing with the mold resin, and the individual semiconductor devices are separated.

  By using such a manufacturing method, it is possible to share the post 5 with respect to the fixed region of the IC element 11 and the pad electrode provided in the IC element 11. That is, a dedicated pattern for fixing the IC element 11 is not necessary, and the IC elements 11 having different dimensions can be mounted using the substrate 10 having the same configuration. Therefore, it is possible to reduce the types of photomasks and the like that form the substrate 10, and the manufacturing cost can be reduced. In addition, when the new IC element 11 is handled, the substrate 10 can be used as it is, so that TAT can be shortened.

JP 2006-185978 A JP 2009-55014 A

  When the technique described in Patent Document 1 is used, for example, in order to mount IC elements having different chip sizes and different numbers of terminals, substrates having different patterns (for example, the positions of the opening patterns 4a are different) are required. That is, a dedicated photomask is required in accordance with the dimensions of each IC element. Therefore, when dealing with a small amount of various types of IC elements, it is necessary to provide a large number of expensive photomasks for substrate formation, which is disadvantageous in terms of cost. In addition, when a new IC element is handled, it is necessary to create a new photomask, and there is a problem that TAT becomes long.

  Next, a problem when the technique described in Patent Document 2 is used will be described with reference to FIG. The recognition mark 8 needs to be formed at the apex of the post 5. The formation of the recognition mark 8 uses a technique such as photolithographic method or direct drawing by an ink jet method. However, such a method requires an independent process for forming the recognition mark and increases the number of manufacturing steps. There are challenges. Further, the post 5 on which the recognition mark 8 is formed is unsuitable as a pad electrode or an electrode for fixing the IC element 11 because its surface state is altered. Therefore, the post 5 whose surface condition has changed as the recognition mark 8 is not suitable for mounting the IC element 11 or as a pad electrode. The number of recognition marks 8 corresponding to each IC element 11 is arranged in the substrate 10. However, in the state where the recognition marks 8 are left, impurities due to the recognition marks 8 reach the regions of the IC elements 11 and the gold wires 13. This may diffuse and reduce the reliability of the semiconductor device 100. Therefore, in order to ensure high reliability, it is necessary not to leave the recognition mark 8 inside the semiconductor device 100. Therefore, there is a problem that restrictions on layout occur.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A method of manufacturing a semiconductor device according to this application example includes a first surface having a first region and a second region that planarly surrounds at least a part of the first region, and the first surface. A substrate having a second surface located opposite to the first surface, a plurality of rows in the first direction of the first surface in the first region, and a second direction intersecting the first direction Forming a plurality of first mask materials having the same shape in the first region so that the intervals between the plurality of adjacent first mask materials are equal to each other so that a plurality of rows are arranged in a row, Etching the substrate to form a plurality of convex portions using the plurality of first mask materials as a mask, parallel to at least a part of the plurality of first mask materials along the second direction, A step of forming a plurality of marks located in the second region, and a semiconductor element Wherein the plurality of alignment of the convex portion was performed using a plurality of marks, characterized in that it comprises a and a step of mounting the first convex portion of the semiconductor element and the plurality of protrusions and.

  According to this, the mark can be formed without using a manufacturing method such as ink printing or laser processing. This eliminates the need for a manufacturing apparatus specialized for the formation of marks, thereby reducing capital investment. The “interval” is defined as the distance from the center of the convex portion to the center of the adjacent convex portion.

  Application Example 2 In the method of manufacturing a semiconductor device according to the application example, the step of forming the plurality of marks includes a step of forming a second mask material in the second region, and the second mask material. And etching the substrate using the mask as a mask.

  According to the application example described above, since etching is performed using the second mask material as a mask, misalignment does not occur in principle at the position of the convex portion generated by the etching and the second mask material, so extremely high accuracy is achieved. Thus, it becomes possible to mount a semiconductor element.

  Application Example 3 A method of manufacturing a semiconductor device according to the application example, wherein the plurality of first mask materials and the second mask material have the same configuration and are formed at the same time.

  According to the application example described above, the first mask material and the second mask material can be simultaneously formed by using, for example, a plating method. Therefore, it is possible to shorten the manufacturing process. Further, it is possible to apply a method of exposing the first mask material and the second mask material using the same photomask, and in this case, since the misalignment does not occur in principle in the position of the convex portion and the mark, it is extremely high. A semiconductor element can be mounted with high accuracy.

  Application Example 4 In the semiconductor device manufacturing method according to the application example, the step of etching the substrate is performed simultaneously with the step of forming the plurality of convex portions.

  According to the application example described above, the convex portion and the mark can be formed by one etching. Therefore, it is possible to shorten the manufacturing process.

  Application Example 5 In the semiconductor device manufacturing method according to the application example, in the step of forming the mark, a recess is provided in a region surrounding the mark of the substrate, and the first surface of the mark And the first surface of the convex portion is provided on the same plane.

  According to the application example described above, when the mark and the convex portion (the region surrounded by the concave portion) are imaged, the image can be captured without changing the focal position of the imaging device. Therefore, even when miniaturization progresses and a high magnification ratio (shallow depth of focus) is required, it becomes possible to focus easily, and the semiconductor element and the mark can be aligned with high accuracy. Become.

  [Application Example 6] A method of manufacturing a semiconductor device according to the application example, wherein the first mask material and the second mask material are a photoresist, a plated layer of a material different from the substrate, or a material in which these are laminated. It is characterized by being.

  According to the application example described above, when searching for the next mark, it is possible to search without changing the focal position of the imaging apparatus. Therefore, even when miniaturization progresses and a high magnification factor (shallow depth of focus) is required, it becomes possible to easily search for the next mark, and the semiconductor element and the mark can be aligned at a high speed. Is possible.

  Application Example 7 A substrate according to this application example is provided in a first region on the first surface side, and includes a plurality of rows in the first direction and the first direction in a plan view on the first surface side. A plurality of rows are formed in the intersecting second direction, and a plurality of convex portions adjacent to each other at the same interval along the first direction and the second direction, and the first surface in the first surface side in the plan view. A plurality of marks located in a second region adjacent to at least a part of the region and arranged in parallel with at least a part of the plurality of convex portions along the second direction. To do.

  According to this, since the marks are regularly arranged, it is easy to find the marks, and it is possible to search for the marks in a short time. In addition, since there is no mark in the first area, the utilization factor of the first area can be improved as compared with the case where the mark is provided in the first area.

  Application Example 8 An array of semiconductor devices according to this application example is provided in a first region on the first surface side, and includes a plurality of columns in the first direction in a plan view on the first surface side, A plurality of rows in a second direction intersecting with one direction, adjacent to each other at the same interval along the first direction and the second direction, and electrically separated and mechanically fixed respectively. A substrate having a plurality of marks arranged in parallel with the plurality of semiconductor elements, and a plurality of marks arranged in a second region planarly adjacent to at least a part of the first region, and the plurality of marks And a semiconductor element mounted on at least one of the convex portions.

  According to this, since the marks are regularly arranged, it is easy to find the marks, and it is possible to mount the semiconductor element in a short time without causing a positional shift. Further, with the above configuration, the mark can be disposed outside the effective region that is electrically connected to the IC element, and the effective density of the semiconductor element can be improved.

(A) is a plan view of an array of semiconductor devices for explaining the first embodiment, (b) is a cross-sectional view taken along the line AA ′ of (a), and (c) is a back surface (first) of the mark. FIG. 3 is an enlarged plan view showing a shape on the (second surface) side. An example of the layout of an IC element when an alignment mark is formed separately from the mark. (A) is a top view which shows the structural example of the semiconductor device concerning a 1st modification, (b) is the sectional view on the A-A 'line of (a). (A) is a top view of the board | substrate concerning 2nd Embodiment, (b) is the sectional view on the A-A 'line of (a). (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 3rd Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 3rd Embodiment. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 3rd Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 3rd Embodiment. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 3rd Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 3rd Embodiment. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 3rd Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 3rd Embodiment. The top view which shows the dicing process of the array of a semiconductor device. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 2nd modification, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning a 2nd modification. (A) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 2nd modification, (b) is shown to Fig.1 (a) concerning a 2nd modification. FIG. 6 is a plan view showing a process corresponding to a region B. (A), (c) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 3rd modification, (b), (d) is a 3rd modification. The top view which shows the process corresponding to the area | region B shown in this Fig.1 (a). (A), (c) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 3rd modification, (b), (d) is a 3rd modification. The top view which shows the process corresponding to the area | region B shown in this Fig.1 (a). (A) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 4th modification, (b) is FIG.1 (a) concerning a 4th modification. The top view which shows the process corresponding to the area | region B shown to Fig.1 (a). (A), (c) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning a 4th modification, (b), (d), (e) is 4th. The top view which shows the process corresponding to the area | region B shown to Fig.1 (a) concerning the modification of FIG. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 4th Embodiment, (b), (d), (f). These are the top views of the board | substrate concerning 4th Embodiment. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 4th Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) of the surface (1st surface) of a board | substrate concerning 4th Embodiment. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 5th Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 5th Embodiment. (A), (c) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 5th Embodiment, (b), (d) is 5th Embodiment. The top view which shows the process corresponding to the area | region B shown in this Fig.1 (a). (A) is sectional drawing corresponding to a die attach process, (b) is a top view. (A), (c), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 6th Embodiment, (b), (d), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 6th Embodiment. (A), (c), (d), (e) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 6th Embodiment, (b), (f). These are top views which show the process corresponding to the area | region B shown to Fig.1 (a) concerning 6th Embodiment. (A), (c) is process sectional drawing corresponding to the AA 'line of Fig.1 (a) concerning 6th Embodiment, (b), (d) is 6th Embodiment. The top view which shows the process corresponding to the area | region B shown in this Fig.1 (a). (A)-(c) is a perspective view for demonstrating background art, (d) is sectional drawing for demonstrating background art. (A) is a perspective view for demonstrating background art, (b) is sectional drawing of (a). (A) is a perspective view for demonstrating background art, (b) is sectional drawing of (a). The top view for demonstrating background art. (A)-(e) is process sectional drawing for demonstrating background art. The top view in the state where the recognition mark and the dicing mark were formed.

Hereinafter, embodiments embodying the present invention will be described with reference to the drawings.
First Embodiment: Semiconductor Device Array and Semiconductor Device

  Hereinafter, an array of semiconductor devices as a first embodiment will be described with reference to the drawings. FIG. 1A is a plan view of a surface (first surface) on which an IC element as a semiconductor element is mounted in the array of the semiconductor device according to the present embodiment. 1B is a cross-sectional view taken along the line A-A ′ of FIG. 1A, and FIG. 1C is an enlarged plan view showing the shape of the back surface (second surface) side of the mark. Here, in FIG. 1A, the mold resin 61 is removed in order to improve visibility. Moreover, in FIG.1 (b), although the post | mailbox 40 is described so that it may take a cylindrical shape, it may be provided with a shape different from a cylindrical shape by the characteristic of the manufacturing method mentioned later.

  The semiconductor device array 300 includes a mold resin 61, a gold wire 53, an IC element 51, a post 40, a plating layer 3 a, a plating layer 3 b, a first region 20 a, a second region 20 b, and a mark 7. Here, the direction parallel to the direction in which the plurality of marks 7 are arranged (in this embodiment, arranged in parallel) is the first direction, and the direction intersects (is orthogonal to in this embodiment) the first direction. Is treated as the second direction.

  The first region 20a is a region in which the IC element 51 and the post 40 to which the IC element 51 is electrically connected are housed, and the semiconductor device 100 is obtained by cutting off the region indicated by the dotted line by dicing. The second region 20b is a region surrounding at least a part of the first region 20a. The second region 20 b includes a mark 7. By referring to the position of the mark 7, the mounting position information of the IC element 51 can be obtained. The mark 7 has a function as a mark indicating a dicing position. The mold resin 61 supports the post 40. The post 40 fixes the IC element 51 and has a function (wire bonding function) for electrically connecting the post 40 and the IC element 51 at a position surrounding the IC element 51 through, for example, a gold wire 53. ing. The posts 40 are arranged at equal intervals in the first direction and the second direction, and include a post base material 41, a plating layer 3a, and a plating layer 3b. The “interval” indicates the distance between the center of the posts 40 and the center of the adjacent posts 40. Hereinafter, it is also called a pitch.

  The plated layer 3 a is located on the surface (first surface) of the post base 41 and the post located in a region surrounding the IC element 51 to fix the post base 41 and avoid the influence of oxidation or the like. 40 and the IC element 51 have a function of securing the strength of wire bonding. The plating layer 3 b is located on the back surface (second surface) of the post base material 41. Then, it is formed so as to ensure the solder adhesion with a circuit board (not shown) on which the semiconductor device 100 is mounted while avoiding the influence of oxidation or the like of the post base material 41. The plated layer 3a and the plated layer 3b may be used as a self-aligned mask in a semiconductor device manufacturing process described later.

  FIG. 1C is an enlarged plan view showing a planar shape when the periphery of the mark 7 is viewed from the back surface. Thus, even after the IC element 51 and the like are mounted and sealed with the mold resin 61, the mark 7 can be seen from the back surface. Therefore, the dicing process can be performed using the mark 7 as a mark, and the dicing can be performed by correcting the dimensional deviation or the like of the array 300 of the semiconductor device generated during the manufacturing process, and the dicing with higher positional accuracy is performed. (The manufacturing method will be described later). Note that the mark 7 may be formed only on the front side without forming the mark 7 through the back side.

  Next, an example in which the alignment mark is used separately from the mark 7 will be described. FIG. 2 shows an example of the layout of the IC element when the alignment mark is formed separately from the mark. As shown in FIG. 2, the IC element 51 constitutes one semiconductor device 100 using, for example, 6 × 6 posts 40. Here, if the alignment mark 7 a is introduced, 7 × 7 posts 40 are required to form one semiconductor device 100. Therefore, the number of semiconductor devices 100 that can be taken decreases. For example, when FIG. 1A is compared with FIG. 2, the alignment mark 7 a is inserted, and in this case, the number of semiconductor devices 100 that can be taken is reduced from nine to six. In particular, when the semiconductor device 100 is small, the reduction in the number of picks increases, but by using the mark 7 as an alignment mark, the density of the semiconductor devices 100 in the array 300 of semiconductor devices can be increased. .

  In the present embodiment, the embodiment in which the mark 7 is formed in a direction parallel to the first direction has been described. However, a configuration in which the mark is arranged in the second direction intersecting the first direction may be used. This is particularly suitable when the dicing apparatus has a configuration in which dicing accuracy can be improved by forming marks in the first direction and the second direction.

(First Modification: Configuration of Semiconductor Device)
In the above-described embodiment, for example, as illustrated in FIG. 1, the embodiment using only one IC element 51 as the semiconductor device 100 has been described. However, the present invention is not limited to this, and a plurality of, for example, a plurality of IC elements 51 are used. The present invention is also applicable when using an IC element (multi-chip module: MCM).

  FIG. 3A is a plan view showing a configuration example of a semiconductor device according to a modification of the present invention. FIG. 3B is a cross-sectional view of FIG. 3A taken along line A-A ′. In FIG. 3A, the entry of the mold resin 61 is omitted in order to avoid complication of the drawing. In FIGS. 3A and 3B, parts having the same configurations as those described in the above embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

  As shown in FIGS. 3A and 3B, in the present invention, two IC elements 51 and IC elements 51 ′ are arranged in one semiconductor device 100. The IC element 51 and the IC element 51 'may be of the same type, or may be different types having different external shapes and numbers of pad terminals. As described above, it is also preferable to configure the semiconductor device array 300 including the semiconductor device 100 in which a plurality of IC elements 51 and IC elements 51 ′ are sealed with the mold resin 61, and a circuit on which the semiconductor device 100 is mounted. It becomes possible to improve the mounting density of a substrate (not shown) equivalently.

  For such an array 300 of semiconductor devices, the IC element 51 and the IC element 51 ′ are aligned by the mark 7 in the same manner as in the above embodiment, and die attachment, wire bonding, dicing, and the like are performed. Obtainable.

  That is, as shown in FIG. 3A, first, the first IC fixing area and the second IC fixing area are searched using the mark 7 as a mark. Next, the first IC element 51 is attached to the post 40 in the first IC fixing area, and the second IC element 51 'is attached to the post 40 in the second IC fixing area (so-called die attach process). Then, the post 40 disposed in a region other than the IC fixing region and the pad terminals of the IC element 51 and the IC element 51 'are connected by a gold wire 53 or the like. Here, using the mark 7 as a mark, the post 40 serving as an external terminal may be searched, and one end of the gold wire 53 may be connected to the searched post 40.

  In this case, it is not essential to form the mark 7 so as to penetrate the back surface side, and it may be arranged only on the front surface. With this configuration, the mounting accuracy of the IC element 51 can be improved. In addition, when different photomasks are used for the front surface processing and the back surface processing, the back surface processing mask is more versatile because the pattern formation of the mark 7 can be omitted, and the back surface processing mask is reduced by shortening the TAT. It becomes possible to provide.

  Next, as shown in FIG. 3B, the IC element 51, the IC element 51 ', the gold wire 53, and the post 40 are sealed with a mold resin 61 using, for example, a thermosetting epoxy resin. Thereafter, the array 300 of semiconductor devices is diced so that the IC element 51 and the IC element 51 ′ are included in the same semiconductor device 100, thereby dividing the semiconductor device 100 into individual semiconductor devices 100. That is, the two IC elements 51 are recognized by recognizing the rectangular shape including the IC element 51 and the IC element 51 ′ and the post 40 electrically connected to the IC element 51 and the IC element 51 ′ by the gold wire 53. Therefore, the IC element 51 ′ can be handled as an equivalent of one IC element, and can correspond to the MCM. Here, the example in which the two IC elements 51 and 51 'correspond to the MCM has been described, but this can be similarly developed even when three or more IC elements are used.

  Thus, according to this modification, the post 40 can be a die pad or an external terminal, as in the above-described embodiment. Accordingly, when assembling the MCM, it is not necessary to prepare a specific die pad, a specific lead frame, or a specific substrate (such as an interposer) for each type of the IC element 51 and the IC element 51 ′, thereby reducing the manufacturing cost. Is possible. Also in this case, as described above, the post 40 in the area other than the IC fixing area may be used as the relay terminal of the gold wire 53. That is, the post 40 connected to the pad terminal of the IC element 51 via the gold wire 53 may be connected to another post 40 via the gold wire 53. According to such a method, the pad terminal of the IC element 51 and IC element 51 ′ can be pulled out to an arbitrary position without changing the arrangement position of the post 40, so that the position of the external terminal of the semiconductor device 100 is substantially reduced. Can be changed. Further, as described above, dicing can be performed so that the post 40 does not remain on the side surface of the semiconductor device 100, and a wiring pattern of a circuit board (not shown) on which the semiconductor device 100 is mounted and around the semiconductor device 100 remain. It is possible to suppress the occurrence of a defect due to a short circuit with the post 40 and the limitation that occurs when the wiring pattern is laid out.

Further, as shown in FIG. 3A, the pad terminals included in the IC element 51 and the IC element 51 ′ may be electrically connected via the gold wire 53 and the post 40. Thereby, since wiring between the IC element 51 and the IC element 51 ′ can be performed in the semiconductor device 100, the wiring pattern of a circuit board (not shown) on which the semiconductor device 100 is mounted can be reduced, and the wiring pattern can be freely set. It becomes possible to increase the degree.
(Second Embodiment: Substrate on which a semiconductor element is mounted)

  Hereinafter, a second embodiment will be described with reference to the drawings. FIG. 4A is a plan view of the surface (first surface) of the substrate according to the present embodiment. FIG. 4B is a cross-sectional view taken along the line A-A ′ of FIG.

  The substrate 6 has a structure capable of mounting the IC element 51 (shown by a dotted line) and wire bonding of the gold wire 53. Here, in FIG. 4A, the post 40 is described as having a cylindrical shape, but may have a shape different from the cylindrical shape depending on the characteristics of the manufacturing method described later.

  The substrate 6 includes a post 40, a post base 41, a plating layer 3 a, a plating layer 3 b, a first region 20 a, a second region 20 b, and a mark 7. The post 40 includes a post base 41, a plating layer 3a, and a plating layer 3b. Here, a direction parallel to the direction in which the plurality of marks 7 are arranged (parallel in the present embodiment) is defined as the first direction, and a direction intersecting with the first direction (perpendicular in the present embodiment) is defined as the second direction. Treat as

  The first region 20a is a region (first surface) on which the IC element 51 is mounted on the substrate 6 and the post 40 described above, to which the IC element 51 is electrically connected, and is indicated by a dotted line by dicing. This is a region where the semiconductor device 100 is obtained by separating with a. The second region 20b is a region surrounding at least a part of the first region 20a. The second region 20 b includes a mark 7. By referring to the position of the mark 7, the mounting position information of the IC element 51 can be obtained. The mark 7 has a function as a mark indicating a dicing position. The plurality of post base materials 41 are arranged at equal intervals in the first direction and the second direction, and it becomes possible to easily search for the post 40 obtained by processing the post base material 41 as described above. ing.

  In this case, it is not essential to form the mark 7 so as to penetrate the back surface side, and it may be arranged only on the front surface. With this configuration, the mounting accuracy of the IC element 51 can be improved. In addition, when different photomasks are used for the front surface processing and the back surface processing, the back surface processing mask is more versatile because the pattern formation of the mark 7 can be omitted, and the back surface processing mask is reduced by shortening the TAT. It becomes possible to provide.

  The plated layer 3 a is located on the surface (first surface) of the post base 41 and has a function to withstand heat and stress applied in the process of fixing the IC element 51 and wire bonding with the IC element 51. The plating layer 3 b is located on the back surface (second surface) of the post base material 41. Further, it avoids the influence of oxidation or the like on the back surface side (second surface side) of the post base material 41 and ensures adhesion with solder or the like used when mounting the semiconductor device 100 on a circuit board (not shown). It is formed properly. The plated layer 3a and the plated layer 3b may be used as a self-aligned mask in a semiconductor device manufacturing process described later. By using such a substrate, the mounting position of the IC element 51 can be detected at high speed and with high accuracy. Further, the mounting density of the semiconductor device 100 can be improved as compared with the case where the alignment mark 7a is used. Further, when the mounting position accuracy of the IC element 51 can be improved by arranging the marks 7 with respect to the second direction intersecting with the arrangement of the marks 7, it is preferable to arrange the marks 7 also with respect to the second direction. It becomes.

Third Embodiment: Semiconductor Device Manufacturing Method-1
Hereinafter, as a third embodiment, a method for manufacturing the above-described semiconductor device will be described with reference to the drawings. In the present embodiment, a first manufacturing method for manufacturing the semiconductor device 100 by dicing the array 300 of semiconductor devices described above will be described. Here, the same reference numerals are assigned to those having a configuration similar to that described above. 5 (a), (c), (e), FIG. 6 (a), (c), (e), FIG. 7 (a), (c), (e), FIG. 8 (a), (c) ) And (e) are process cross-sectional views corresponding to the line AA ′ in FIG. 5 (b), (d), (f), FIG. 6 (b), (d), (f), FIG. 7 (b), (d), (f), FIG. (d), (f) is a top view which shows the process corresponding to the area | region B shown to Fig.1 (a) of the surface (1st surface) of the board | substrate concerning this embodiment. If there is a feature on the back surface (second surface) side, this is clearly stated and a plan view of the back surface is shown. FIG. 9 is a plan view showing a dicing process of the array 300 of semiconductor devices.

  First, as step 1, a substrate 1 as a substrate shown in FIGS. 5A and 5B is prepared. The substrate 1 may be a copper plate made of copper, for example. As long as the size of the substrate 1 in plan view is larger than the two package outlines for the first region 20a of the semiconductor device 100 created from the substrate 1 and the two regions for the second region 20b. good. Moreover, the thickness of the board | substrate 1 is about 0.10-0.30 mm, for example.

  Next, as step 2, as shown in FIGS. 5C and 5D, the first surface (hereinafter also referred to as “front surface”) and the second surface (hereinafter referred to as “back surface”) of the substrate 1 are also described. ), A photoresist layer 2a ′ and a photoresist layer 2b ′ are formed respectively. The photoresist layer 2a 'and the photoresist layer 2b' may be, for example, a positive type or a negative type. In addition, in order to avoid complication of drawing, the hatching in the small circular area | regions in a top view, such as the convex part 40p, is abbreviate | omitted, for example.

  Next, as step 3, as shown in FIGS. 5E and 5F, the photoresist layer 2a 'and the photoresist layer 2b' located on the surface of the substrate 1 are exposed and developed. Specifically, a pattern corresponding to a plurality of posts 40 (see FIG. 1A) is provided in the first region 20a, and a pattern 7 (see FIG. 1A) is provided in the second region 20b. A resist pattern 2a provided with a mark precursor 7 ′ is formed. The resist pattern 2b is in a state where the photoresist layer 2b 'is left as it is. It should be noted that some pattern may be assigned to the photoresist layer 2b 'in a region away from the first region 20a and the second region 20b.

  Here, the resist pattern 2b may be formed on the back surface by forming a photoresist after forming the resist pattern 2a and curing it. Alternatively, the resist pattern 2a may be formed after the resist pattern 2b is formed on the back surface by changing the order.

  Next, as step 4, as shown in FIGS. 6 (a) and 6 (b), for example, using a ferric chloride solution or an alkaline etching solution (hereinafter also referred to as an alkaline solution), a dip method or a spray is used. The substrate 1 is etched using the resist patterns 2a and 2b as masks by the wet etching method of the formula, and the convex portions 40p and the marks 7 are formed. Here, the mark 7 is etched by controlling the etching time, the temperature and the concentration of the etching solution so that the convex portion 40p is connected to a part of the substrate 1 in this etching, that is, half etching is performed. In the present embodiment, the mark 7 is a region where the recess 63x is formed.

  Next, as step 5, as shown in FIGS. 6C and 6D, the resist patterns 2a and 2b are temporarily removed and a photoresist layer is formed on the front side and the back side, respectively, and then the front side photoresist layer is formed. Is exposed and developed to form a resist pattern 16a exposing a region where the convex portion 40p is formed and a region surrounding the concave portion 63x formed in the mark 7, and a resist pattern covering the back surface of the substrate 1 16b is formed. The resist pattern 16b may be formed on the back surface by forming a photoresist layer after forming the resist pattern 16a on the front surface and then curing the photoresist layer. Alternatively, the resist pattern 16b may be formed on the front surface after the resist pattern 16b is formed on the rear surface by changing the order.

  Next, as step 6, as shown in FIGS. 6E and 6F, using the resist patterns 16a and 16b as a mask, a region where the protrusions 40p are exposed using a method such as electroplating, and a mark precursor For example, Ni (nickel) / Pd (palladium) / Au (gold) multilayer plating is performed on the region surrounding the recess 63x of the body 7 from the side closer to the surface to form the plating layer 3a. As the plating layer 3a, a Ni / Au two-layer structure or an Ag (silver) single layer may be used instead of Ni / Pd / Au. Further, a metal containing Rh (rhodium), Ru (ruthenium), or the like may be used. When using the board | substrate 1, it is suitable to plate the metal which can take selectivity with copper. The plating layer 3a has a total thickness of about 3 μm, for example.

  Next, as step 7, as shown in FIGS. 7A and 7B, the resist patterns 16a and 16b are temporarily removed and a photoresist layer is formed on the front side and the back side, respectively, and then the back side photoresist is formed. The layer is exposed and developed, and in the first area 20a in plan view, the photoresist layer is aligned with the area where the substrate 1 is etched when viewed from the front side, and surrounds the recess 63x in the second area 20b. A resist pattern 17b is formed, and a resist pattern 17a is formed on the entire surface of the substrate 1. Here, the mark 7 indicates a region surrounded by the recess 63x in a plan view. In this case, it is preferable to leave the photoresist in the region where the mark 7 is located, and form the resist pattern 17b so that the mark 7 can be easily recognized in the process shown in FIG. Here, after forming the resist pattern 17b, a photoresist layer may be formed and cured to form the resist pattern 17a on the entire surface. Further, the resist pattern 17b may be formed after the resist pattern 17a is formed on the entire surface by changing the order. Here, FIG. 7B is a plan view seen from the back side.

  Next, as step 8, as shown in FIGS. 7C and 7D, for example, Ni (nickel: near the surface) / Pd (palladium: middle layer) / Au (gold: gold) using the resist patterns 17a and 17b as a mask. Multilayer plating at a position away from the surface is performed to form a plating layer 3b. As the plating layer 3b, a two-layer structure of Ni (near the surface) / Au (position away from the surface) or an Ag (silver) single layer may be used instead of Ni / Pd / Au. Further, a metal containing Rh (rhodium), Ru (ruthenium), or the like may be used. When using the board | substrate 1 which used copper as a material, it is suitable to plate the metal which can take selectivity with copper as a material. The plating layer 3b has a thickness of all layers, for example, about 3 μm. Here, FIG. 7D is a plan view seen from the back surface.

  Next, as step 9, as shown in FIGS. 7E and 7F, the resist patterns 17a and 17b are removed. Here, FIG. 7F is a plan view seen from the back side. Here, what is shown in FIGS. 7E and 7F has a structure as the substrate 6.

  Next, as step 10, as shown in FIGS. 8A and 8B, the adhesive 23 is applied to the IC element 51 and attached to the convex portion 40 p with the mark 7 as a mark (die attach). Instead of applying the adhesive 23 to the IC element 51, the IC element 51 may be mounted on the adhesive 23 using the mark 7 as a mark after being placed on the convex portion 40 p. At this time, when the adhesive 23 is placed, the adhesive 23 may be placed on the convex portion 40p using the mark 7 as a mark. And the convex part 40p in the area | region surrounding the convex part 40p with which the IC element 51 was mounted | worn, and the pad terminal (electrode) with which the IC element 51 is provided are electrically connected using the gold wire 53 (wire bonding). .

  Next, as step 11, as shown in FIGS. 8C and 8D, the surface side is sealed (covered) with a mold resin 61 containing a resin such as a thermosetting epoxy resin, for example. In this step, a mold resin 61 is provided so as to cover the convex portion 40p, the IC element 51, and the gold wire 53. . This step may be performed in a reduced pressure atmosphere. In this case, it becomes possible to encapsulate the surface side without generating voids in the encapsulation process with the epoxy resin. Here, FIG.8 (d) has shown the top view from the back surface side.

  Next, as step 12, as shown in FIGS. 8E and 8F, the substrate 1 is etched from the back side using, for example, a ferric chloride solution or an alkaline solution using the plating layer 3b as a mask. The protrusions 40p are separated from each other to form the posts 40. Each post 40 is supported by the mold resin 61 and can hold its position even if the fixing by the substrate 1 is released. At the same time, the metal plate 301 corresponding to the substrate 1 left in the second region is etched to expose the mold resin 61 from the back surface side of the mark 7 through the recess 63x. Here, before the substrate 1 is etched, it is also preferable to insert a step of cleaning with a sulfuric acid-based cleaning solution in order to remove the metal oxide film incidentally formed in the manufacturing steps so far. Further, after the substrate 1 is etched, the plating layer 3b serving as a mask remains as burrs. Therefore, it is preferable to perform a honing (deburring) process. Specifically, a liquid such as water is mechanically removed by spraying a liquid such as water against the burrs of the plating layer 3b. Since the mold resin 61 has a large optical characteristic with the surrounding metal layer, the mold resin 61 can be recognized well from the back surface, and can be suitably used as a mark for dicing.

  Next, as step 13, as shown in FIG. 9, for example, an ultraviolet curable film (not shown) is embrittled on the side of the mold resin 61 of the array 300 of the semiconductor device (it becomes brittle by irradiation with ultraviolet rays and can be easily peeled off). It is possible to obtain high dicing position accuracy by performing dicing while referring to the position of the mark 7 in real time using the blade 302 from the back surface. In addition, the thick line in FIG. 9 is a line which shows that a dicing line cut | disconnects this area | region, and is not an actual line. Here, this cutting direction is performed along the first direction. Then, after the same operation is performed in the second direction, the semiconductor device 100 can be formed by irradiating with ultraviolet rays to make the ultraviolet curable film brittle and separate. In some cases, a finished product may be fixed to the ultraviolet curable film.

  Thereafter, as shown in the first embodiment, the semiconductor device 100 is formed by performing dicing. As described above, since dicing can be performed while directly viewing the mark 7, the dicing line can be corrected when the mold resin 61 or the like is cut. Further, the mark 7 has a configuration in which the mold resin 61 is exposed in the substrate 1 in a plan view on the back surface side. Since the optical characteristics (for example, light reflectance) are greatly different between the substrate 1 and the mold resin 61, high contrast can be obtained. Therefore, it is possible to correct the dicing line more accurately with ease and high accuracy.

(Second Modification: Semiconductor Device Manufacturing Method)
Hereinafter, a modification of the third embodiment will be described. When the third embodiment is used, the plating layer 3a (see FIG. 6E) is formed using the same plating material in the first region 20a and the second region 20b. The required plating layer is preferably made of a material having strong oxidation resistance and excellent reliability, whereas in the second region 20b, the mark 7 formed in the second region 20b (FIG. 6 (e) In the case of ()), it is preferable to form another plating layer because the optical characteristics are preferably different from those of the surroundings. Hereinafter, a modified example in this case will be described. In terms of process, since there are many parts similar to the third embodiment, they are appropriately cited to avoid duplication of explanation. Here, FIGS. 10A, 10C, 10E, and 11A are process cross-sectional views corresponding to the line AA ′ in FIG. 1A, and FIGS. (F), FIG.11 (b) is a top view which shows the process corresponding to the area | region B shown to Fig.1 (a) of the surface (1st surface) of the board | substrate concerning this embodiment. If there is a feature on the back surface (second surface) side, this is clearly stated and a plan view of the back surface is shown.

  First, steps 1 to 4 are performed as the third embodiment. Next, as step 5A, as shown in FIGS. 10A and 10B, a resist pattern 16c having a pattern covering the second region 20b and having the top of the convex portion 40p of the first region 20a opened, A resist pattern 16d (covering both the first region 20a and the second region 20b) is formed. Here, the mark 7 indicates a region surrounded by the recess 63x in a plan view.

  Next, as shown in FIGS. 10C and 10D, Ni / Pd / Au plating is performed as step 6A to form a plating layer 3a.

  Next, as step 7A, as shown in FIGS. 10E and 10F, after removing the resist pattern 16c and the resist pattern 16d, the first region 20a and the second region 20b newly located on the back surface side are removed. And a resist pattern 16e which is located on the surface and covers the mark 7 and the first region of the second region 20b.

  Next, as step 8A, as shown in FIGS. 11A and 11B, the plating layer 3c is formed in the second region 20b and in the region excluding the mark 7. For the plating layer 3c, it is preferable to use, for example, Ag (silver) which is optically excellent in light reflectance. Then, after removing the resist pattern 16e and the resist pattern 16f, the semiconductor device 100 is formed by performing the steps 10 to 13 shown in the third embodiment. In this case, a highly reliable gold-based material is used for the first region 20a, and a silver-based material with excellent reflectance is used for the second region 20b. It is possible to provide a manufacturing method having both. Note that the process order may be changed as long as the set of the steps 5A and 6A and the set of the steps 7A and 8A are combined. Further, the present invention can also be applied to semiconductor device manufacturing methods-2 and 3 described later, and can be dealt with by inserting a step of forming a resist pattern separately covering the first region 20a and the second region 20b.

(Third Modification: Semiconductor Device Manufacturing Method)
Hereinafter, another modification of the third embodiment will be described. In the third embodiment, as shown in step 4, the convex portion 40p and the mark 7 are formed in the same step. In this case, the etching depth of the convex portion 40p and the mark 7 is changed. For example, the etching amount of the mark 7 may be increased to penetrate the mark 7 and the dicing mark on the back surface side may not be handled, and the degree of freedom related to the process conditions may be reduced. It may be preferable to perform etching that can correspond to 40p and the depth of the mark 7 independently. Hereinafter, a modified example in this case will be described. In terms of process, since there are many parts similar to the third embodiment, they are appropriately cited to avoid duplication of explanation. Here, FIGS. 12A, 12C, 13A, and 13C are process cross-sectional views corresponding to the line AA ′ in FIG. 1A, and FIGS. FIGS. 13B and 13D are plan views showing the process corresponding to the region B shown in FIG. 1A of the surface (first surface) of the substrate according to the present embodiment. If there is a feature on the back surface (second surface) side, this is clearly stated and a plan view of the back surface is shown.

  First, step 1 and step 2 are performed. Next, as step 3B, as shown in FIGS. 12A and 12B, the photoresist layer 2a 'and the photoresist layer 2b' located on the surface of the substrate 1 are exposed and developed. Specifically, a resist pattern 2a that includes a pattern corresponding to a plurality of posts 40 (see FIG. 1A) in the first region 20a and covers the second region 20b is formed. The resist pattern 2b is in a state where the photoresist layer 2b 'is left as it is. It should be noted that some pattern may be assigned to the photoresist layer 2b 'in a region away from the first region 20a and the second region 20b. The resist pattern 2b may be formed on the back surface by forming a photoresist after forming the resist pattern 2a and curing it. Alternatively, the resist pattern 2a may be formed after the resist pattern 2b is formed on the back surface by changing the order.

  Next, as step 4B, as shown in FIGS. 12C and 12D, for example, using a ferric chloride solution or an alkaline etching solution (hereinafter also referred to as an alkaline solution), a dip method or a spray is used. The substrate 1 is etched using the resist patterns 2a and 2b as a mask by the wet etching method of the formula, and the convex portion 40p is formed. In this etching, the etching is performed by controlling the etching time, the temperature of the etching solution, and the concentration so that the convex portion 40p is connected to a part of the substrate 1, that is, half etching. Here, the mark 7 indicates a region surrounded by the recess 63x in a plan view.

  Next, as step 5B, as shown in FIGS. 13A and 13B, the resist patterns 2a and 2b are temporarily removed and a photoresist layer is formed on the front side and the back side, respectively, and then the front side photoresist layer is formed. Is exposed and developed to cover the region (first region 20a) where the convex portion 40p is formed, and the resist pattern 2c is applied to the second region 20b corresponding to the mark 7 (see FIGS. 13C and 13D). And a resist pattern 2d covering the back surface of the substrate 1 is formed. Note that the resist pattern 2d may be formed on the back surface by forming a photoresist layer after forming the resist pattern 2c on the front surface and curing it. Further, the resist pattern 2c may be formed on the front surface after the resist pattern 2d is formed on the rear surface by changing the order.

  Next, as step 6B, as shown in FIGS. 13C and 13D, the mark 7 is formed by etching. In this modification, the mark 7 having a through-hole shape is formed. In this case, since the position of the mark 7 from the back surface side can be detected, the accuracy in the dicing process can be further increased. In addition, when the mark 7 is a through-hole, it is preferable to prevent the protrusion by sticking a tape or the like on the back surface side in a sealing process with a mold resin 61 described later. Then, in step 5 in the third embodiment, “temporarily remove the resist patterns 2a and 2b” is read as “temporarily remove the resist patterns 2c and 2d”, and the process is continued according to the third embodiment. Thus, the semiconductor device 100 is formed. In this case, since the depth of the mark 7 and the depth of the convex portion 40p can be changed independently, the degree of freedom of the structure is improved, such as passing the mark 7 to the back surface or reducing the etching amount of the mark 7. It becomes possible.

(Fourth Modification: Semiconductor Device Manufacturing Method)
Hereinafter, still another modification of the third embodiment will be described. In the third embodiment, the mark 7 has a concave shape, but a convex shape may be used. Hereinafter, a modified example in this case will be described. In terms of process, since there are many parts similar to the third embodiment, they are appropriately cited to avoid duplication of explanation. The difference in this modification is mainly the mask that covers the second region 20b, and therefore, the part showing the main differences in the process will be described. Here, FIGS. 14A, 15A, and 15C are process cross-sectional views corresponding to the line AA ′ in FIG. 1A, and FIGS. 14B, 15B, (D), (e) is a top view which shows the process corresponding to the area | region B shown to Fig.1 (a) of the surface (1st surface) of the board | substrate concerning this embodiment. If there is a feature on the back surface (second surface) side, this is clearly stated and a plan view of the back surface is shown.

  First, steps 1 and 2 are performed. Next, as step 3C, as shown in FIGS. 14A and 14B, the photoresist layer 2a 'and the photoresist layer 2b' located on the surface of the substrate 1 are exposed and developed. Specifically, a pattern corresponding to a plurality of posts 40 (see FIG. 1A) is provided in the first region 20a, and the post 40 (located in the first region in FIG. 1) is also provided in the second region 20b. In order to form the mark 7 having the same shape as the post 40), a resist pattern 2e similar to that in the first region 20a is formed. The back surface is covered with a first region 20a and a second region 20b with a resist pattern 2f.

  Next, step 4 is performed as shown in FIGS. Although the names assigned to the resist patterns are different here, for example, the same process can be used by using the same resist. In the following processes, even if the resist pattern names are different, they are treated as the same process and are not specified.

  Next, as step 5C, as shown in FIGS. 15C and 15D, the resist patterns 2a and 2b are temporarily removed and a photoresist layer is formed on the front side and the back side, respectively, and then the front side photoresist layer is formed. Are exposed and developed to form a resist pattern 2g that exposes the top of the convex portion 40p and the top of the mark 7, and the first region 20a and the second region 20b located on the back surface of the substrate 1 are formed. A covering resist pattern 2h is formed. Next, the semiconductor device 100 shown in FIG. 1A can be obtained by performing Step 6 and the subsequent steps. In this case, the adhesive 23 shown in FIGS. 8A and 8B in the third embodiment is applied to the IC element 51 and the mark 7 is used as a mark to attach to the convex portion 40p (die attach). With features. Here, since the convex portion 40p and the mark 7 have the same height (in other words, the surface of the convex portion 40p and the surface of the mark 7 are on the same plane), the optical observation system can be easily used in the die attach process. Can be focused. Therefore, it is possible to perform die attach and wire bonding with high speed and accurate position accuracy. In this case, the post 40 and the mark 7 are arranged in the same shape and with the same interval. When it is difficult to recognize the position of the mark 7 using this configuration, as shown in FIG. 15E, the mark 7 is surrounded by the plating layer 3a so that the arrangement of the mark 7 can be clearly shown ( A mark 7 is shown and is partially enclosed, and may be clearly indicated. Further, the mark 7 may be explicitly shown by other methods. For example, it is preferable to arrange a mark 7 having a size different from that of the mark 7 or to arrange a line or the like for clarifying the mark 7. Further, the present invention can also be applied to semiconductor device manufacturing methods-2 and 3 described later, and can be dealt with by inserting a step of forming a resist pattern separately covering the first region 20a and the second region 20b.

Fourth Embodiment: Semiconductor Device Manufacturing Method-2
Although the method for manufacturing a semiconductor device has been described above, examples of the method for manufacturing a semiconductor device include those other than the methods described above. A semiconductor device manufacturing method as a fourth embodiment of the present invention will be described below with reference to the drawings. Here, FIGS. 16A, 16C, 17E, 17A, 17C, 17E are process cross-sectional views for explaining a method for manufacturing a semiconductor device according to the present embodiment, 16 (b), (d), (f), FIGS. 17 (b), (d), and (f) are plan views for explaining the method for manufacturing the semiconductor device according to the present embodiment. Since the final shape is similar to that shown in FIGS. 1A and 1B, the cross-sectional view taken along the line AA 'in FIG. 1A is used, and the plan view is shown in FIG. A region B shown in (a) is used.

  First, a substrate 1 as a substrate shown in FIGS. 16A and 16B is prepared. As long as the size of the substrate 1 in plan view is larger than the two package outlines for the first region 20a of the semiconductor device 100 created from the substrate 1 and the two regions for the second region 20b. good. Moreover, the thickness of the board | substrate 1 is about 0.10-0.30 mm, for example.

  Next, as shown in FIGS. 16C and 16D, each of the first surface (hereinafter also referred to as “front surface”) and the second surface (hereinafter also referred to as “back surface”) of the substrate 1 is exposed to photo. A resist layer 18a ′ and a photoresist layer 18b ′ are formed. The photoresist layer 18a 'and the photoresist layer 18b' may be, for example, a positive type or a negative type.

  Next, as shown in FIGS. 16E and 16F, the photoresist layer 18a ′ and the photoresist layer 18b ′ located on the front surface and the back surface of the substrate 1 are exposed and developed to form a plurality of convex portions. (Hereinafter also referred to as a post) formed in a pattern shape corresponding to a first region 20a formed and a mark 7 (see FIG. 1A) located in a second region 20b surrounding the first region 20a. Resist patterns 18a and 18b are formed.

  Next, as shown in FIGS. 17A and 17B, using the resist patterns 18a and 18b as a mask, a convex portion 40p (see FIG. e) A plating layer 3a is formed to cover (see). In the second region 20b, a plating layer 3a surrounding the mark 7 (see FIG. 17E) having a concave shape is formed.

  Then, in the first region 20a on the back surface side, a plating layer 3b is formed to cover a region overlapping with the convex portion 40p (see FIG. 17E) in a plan view as in the front surface side. A plated layer 3b is formed in the second region 20b so that the mark 7 can be observed from the back surface in a plan view. In the plating step, for example, multilayer plating of Ni (nickel) / Pd (palladium) / Au (gold) is performed from the side closer to the surface of the substrate 1 to form the plating layers 3a and 3b. As the plating layers 3a and 3b, a Ni / Au two-layer structure or an Ag (silver) single layer may be used instead of Ni / Pd / Au. Further, a metal containing Rh (rhodium), Ru (ruthenium), or the like may be used. When copper is used as the material of the substrate 1, it is preferable to plate a metal that can be selected from copper. The plating layers 3a and 3b have a total thickness of about 3 μm, for example.

  Next, as shown in FIGS. 17C and 17D, the resist patterns 18a and 18b are removed. 17E and 17F, on the surface side, the substrate 1 is etched from the surface side using the plating layer 3a as a mask, and a plurality of convex portions 40p are formed in the first region 20a in plan view. In addition to forming the mark 7, on the back surface side, using the plating layer 3 b as a mask, a convex portion 40 q is formed at a position corresponding to a region overlapping with the plurality of convex portions 40 p in plan view. Here, the mark 7 is a region surrounded by the recess 63x in a plan view. When each region is formed, etching is performed by controlling the etching time, the temperature of the etching solution, and the concentration so as to achieve half etching in which a part of the substrate 1 is connected. Half etching of the substrate 1 is performed by, for example, dipping or spraying wet etching. For example, a ferric chloride solution or an alkaline solution is used as the etching solution. In this state, the substrate 6 has a configuration in which a semiconductor element (not shown) or the like can be mounted.

  In addition, the etching amount of the surface of the board | substrate 1 and a back surface may be formed in the same depth, and may be formed in a different depth. For example, when performing spray-type wet etching, the etching time on the front surface side is set to twice the etching time on the back surface side. Thereby, for example, the etching amount on the front surface side can be set to 0.1 mm, and the etching amount on the back surface side can be set to 0.05 mm. In this embodiment, the process is performed so as to have different depths.

  In this case, the second region 20b shown in FIGS. 17C and 17D may be covered with the plating layer 3b. In this case, when the steps of FIGS. 17E and 17F are performed, the mark 7 is formed on the surface. The presence of the mark 7 makes it possible to recognize the position of an IC element (not shown) by the mark 7 and perform a precise die attach process. In addition, when different photomasks are used for the front surface processing and the back surface processing, the back surface processing mask is more versatile because the pattern formation of the mark 7 can be omitted, and the back surface processing mask is reduced by shortening the TAT. It becomes possible to provide.

  Here, after the wet etching process is finished, the exposed surface of the substrate 1 may be oxidized and darkened due to the influence of the etching solution. Therefore, a step of performing acid cleaning to remove the oxide layer after the wet etching may be used. In this case, it is possible to prevent a decrease in reliability caused by impurities contained in the oxide layer. Then, the semiconductor device 100 is formed by continuously performing the steps 10 to 13 shown in the third embodiment.

  By using this manufacturing method, the etching process can be reduced once compared with the manufacturing method-1 of the semiconductor device. Moreover, the plating process can be reduced once. Moreover, since both surfaces are etched simultaneously, the photoresist coating process can be reduced twice compared with the case of etching one side at a time. Further, the number of resist pattern removals can be reduced by three times. Therefore, it is possible to reduce the time required for manufacturing and reduce the amount of photoresist used.

  In FIGS. 17A and 17B, before the substrate 1 is etched, a plating protecting photoresist (not shown) may be newly formed on the front surface and the back surface of the substrate 1, respectively. In the etching process of the substrate 1, since the substrate 1 is etched using the plating layers 3a and 3b covered with the photoresist as a mask, the plating layers 3a and 3b can be protected from the etching solution. This photoresist may be formed on only one side of the front surface or the back surface. For example, by forming on the surface side, wire bonding can be performed with good adhesion.

  Here, before the substrate 1 is etched, it is also preferable to insert a step of cleaning with a sulfuric acid-based cleaning solution in order to remove the metal oxide film incidentally formed in the manufacturing steps so far. Further, after etching the substrate 1, the plating layers 3a and 3b used as a mask remain as burrs. Therefore, it is also preferable to perform a honing (deburring) process. Specifically, a liquid such as water is mechanically removed by hitting the burrs of the plating layers 3a and 3b in the form of a jet. In this case, it is preferable to perform the honing process on both sides.

Fifth Embodiment: Semiconductor Device Manufacturing Method-3
Although the method for manufacturing a semiconductor device has been described above, examples of the method for manufacturing a semiconductor device include those other than the methods described above. Hereinafter, a semiconductor device manufacturing method according to a fifth embodiment of the present invention will be described with reference to the drawings. Here, FIGS. 18A, 18C, 19E, 19A, and 19C are process cross-sectional views for explaining the manufacturing method of the semiconductor device according to the present embodiment, and FIG. ), (D), (f), FIG. 19B, and FIG. 19D are plan views for explaining the method for manufacturing the semiconductor device according to the present embodiment. Since the final shape is similar to that shown in FIGS. 1A and 1B, the cross-sectional view taken along the line AA 'in FIG. 1A is used, and the plan view is shown in FIG. A region B shown in (a) is used.

  First, the substrate 1 shown in FIGS. 18A and 18B is prepared. The size of the substrate 1 in plan view is larger than the region including two package outlines on the first region 20a of the semiconductor device 100 created from the substrate 1 and the mark 7 on the second region 20b. I need it. Moreover, the thickness of the board | substrate 1 is about 0.10-0.30 mm, for example.

  Next, as shown in FIGS. 18C and 18D, the first surface (hereinafter also referred to as “surface”) and the second surface (the surface opposite to the first surface) of the substrate 1. , Also referred to as “back surface”), plating is performed using a method such as electroplating. In the plating step, for example, multilayer plating of Ni (nickel) / Pd (palladium) / Au (gold) is performed from the side closer to the surface to form the plating layers 3a and 3b. As the plating layers 3a and 3b, a Ni / Au two-layer structure or an Ag (silver) single layer may be used instead of Ni / Pd / Au. Further, a metal containing Rh (rhodium), Ru (ruthenium), or the like may be used. When using the board | substrate 1, it is suitable to plate the metal which can take selectivity with copper. The plating layer 3a formed on the front surface side and the plating layer 3b formed on the back surface side have a thickness of about 3 μm, for example. In the present embodiment, the description of the case where Ni / Pd / Au is used will be continued.

  Next, as shown in FIGS. 18E and 18F, a photoresist layer 18a 'and a photoresist layer 18b' are formed on the front surface side and the back surface side, respectively. The photoresist layer 18a 'and the photoresist layer 18b' may be, for example, a positive type or a negative type.

  Next, as shown in FIGS. 19A and 19B, the photoresist layer 18a ′ and the photoresist layer 18b ′ are exposed and developed, and a resist pattern 18a and a resist pattern 18b are formed on the front and back surfaces of the substrate 1, respectively. Form.

  In this case, the region 20b shown in FIGS. 19A and 19B may be covered with the plating layer 3b. In this case, when the steps of FIGS. 17E and 17F are performed, the mark 7 is formed on the surface. The presence of the mark 7 makes it possible to recognize the position of an IC element (not shown) by the mark 7 and perform a precise die attach process. In addition, when different photomasks are used for the front surface processing and the back surface processing, the back surface processing mask is more versatile because the pattern formation of the mark 7 can be omitted, and the back surface processing mask is reduced by shortening the TAT. It becomes possible to provide.

  Next, as shown in FIGS. 19C and 19D, the resist pattern 18a and the resist pattern 18b are used as a mask to leave the substrate 1 and perform etching so that part of the substrate 1 is connected (so-called half-etching). Thus, a region to be the convex portion 40p is formed in the first region 20a on the front surface side. Then, the mark 7 is formed in the second region 20b. And the area | region used as the convex part 40q which overlaps with the convex part 40p planarly similarly to the surface side is formed in the 1st area | region 20a of the back surface side. In the second region 20b, a plated region is left around the mark 7 in plan view. In the plating step, for example, multilayer plating of Ni (nickel) / Pd (palladium) / Au (gold) is performed from the side closer to the surface to form the plating layers 3a and 3b. As the plating layers 3a and 3b, a Ni / Au two-layer structure or an Ag (silver) single layer may be used instead of Ni / Pd / Au. Further, a metal containing Rh (rhodium), Ru (ruthenium), or the like may be used. When copper is used as the material of the substrate 1, it is preferable to plate a metal that can be selected from copper. The plating layers 3a and 3b have a total thickness of about 3 μm, for example.

  Here, when each region is formed, the etching is performed while controlling the etching time, the temperature and the concentration of the etching solution so that half etching is partially connected to the substrate 1. Half etching of the substrate 1 is performed by, for example, dipping or spraying wet etching. In addition, aqua regia that can dissolve Au is used as an etching solution for the plating layers 3a and 3b, and after etching the plating layers 3a and 3b, the etching solution is switched to, for example, a ferric chloride solution or an alkaline solution. It can respond.

  In addition, the etching amount of the surface of the board | substrate 1 and a back surface may be formed in the same depth, and may be formed in a different depth. For example, when performing spray-type wet etching, the etching time on the front surface side is set to twice the etching time on the back surface side. Thereby, for example, the etching amount on the front surface side can be set to 0.1 mm, and the etching amount on the back surface side can be set to 0.05 mm. In this embodiment, the process is performed so as to have different depths.

  In the etching process of the substrate 1, the plating layers 3 a and 3 b and the substrate 1 are etched using the resist patterns 18 a and 18 b covering the plating layers 3 a and 3 b as a mask. Therefore, the plating layers 3 a and 3 b covered with the resist patterns 18 a and 18 b 3b can be protected from the etchant. Here, a step of performing acid cleaning after wet etching may be used. Further, physical etching may be performed instead of etching by chemical processing means such as wet etching. For example, it is also possible to perform mechanical processing by performing a sand blasting process by spraying glass particles or the like.

  Next, as shown in FIGS. 19E and 19F, the resist patterns 18a and 18b are removed, and the steps 10 to 13 shown in the third embodiment are continuously performed, whereby the semiconductor device 100 is formed. The

  By using this manufacturing method, the etching process can be reduced once compared with the semiconductor device manufacturing method described in the third embodiment. Moreover, the plating process can be reduced once. Moreover, since both surfaces are etched simultaneously, the photoresist coating process can be reduced twice compared with the case of etching one side at a time. Further, the number of resist pattern removals can be reduced by three times. Therefore, it is possible to reduce the time required for manufacturing and reduce the amount of photoresist used.

  Further, as compared with the fourth embodiment, etching can be performed without exposing the plating layers 3a and 3b to an etching solution without forming a resist mask for plating protection. That is, it is possible to hold the high-quality plated layers 3a and 3b without increasing the number of steps.

  Here, before the substrate 1 is etched, it is also preferable to insert a step of cleaning with a sulfuric acid-based cleaning solution in order to remove the metal oxide film incidentally formed in the manufacturing steps so far. Further, after etching the substrate 1, the plating layers 3a and 3b used as a mask remain as burrs. Therefore, it is also preferable to perform a honing (deburring) process. Specifically, a liquid such as water is mechanically removed by hitting the burrs of the plating layers 3a and 3b in the form of a jet. In this case, it is preferable to perform the honing process on both sides.

(Fifth Modification: Semiconductor Device Manufacturing Method)
Hereinafter, another modified example will be described with respect to the above-described embodiment and modified example. In the above-described embodiment and modification, the semiconductor element and the post are bonded using the wire bonding process, but this uses a process (so-called face-down process) for simultaneously fixing and electrically connecting the semiconductor element. May be. Specifically, the die attach process shown in FIG. 10 of the third embodiment and shown in FIGS. 8A and 8B has another configuration. 20A and 20B are a sectional view and a plan view, respectively, corresponding to the die attach process. Here, the main difference from the above-described embodiment is that, instead of wire bonding, the electrode of the IC element 51 and the plating layer 3a (plating layer 3 covering the convex portion 40p) are electrically coupled together for direct fixation. It is that you are. After this step, it is possible to cope with the semiconductor device manufacturing method using the face-down step by performing the steps 10 to 13 of the third embodiment.

Sixth Embodiment: Semiconductor Device Manufacturing Method-4
Although the method for manufacturing a semiconductor device has been described above, examples of the method for manufacturing a semiconductor device include those other than the methods described above. Hereinafter, a semiconductor device manufacturing method according to a sixth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a case will be described in which the mark 7 has a convex shape as shown in the fourth modification. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.

  21-23 is a figure which shows the manufacturing method of the board | substrate 6 concerning 6th Embodiment of this invention. More specifically, FIGS. 21 (a), (c), (e), FIGS. 22 (a), (c), (d), (e), FIGS. 23 (a), (c) are shown in FIG. FIG. 21 (b), (d), (f), FIG. 22 (b), (f), FIG. 23 (b), and FIG. It is sectional drawing in the AA 'line in (a), FIG.21 (b), FIG.22 (b), FIG.23 (is a top view in the area | region B in Fig.1 (a). Since the configurations are similar, the region used in FIG. 1 is used.

  First, a substrate 1 as shown in FIGS. 21A and 21B is prepared. As long as the size of the substrate 1 in plan view is larger than the two package outlines for the first region 20a of the semiconductor device 100 created from the substrate 1 and the two regions for the second region 20b. good. Moreover, the thickness of the board | substrate 1 is about 0.10-0.30 mm, for example.

  Next, as shown in FIGS. 21C and 21D, the surface (first surface) of the substrate 1 is entirely covered with a resist pattern 19a, and the surface is partially exposed on the back surface of the substrate 1. A resist pattern 19b is formed. The distance (that is, the pitch) between adjacent isolated patterns of the resist pattern 19b is, for example, about 0.5 to 1.0 mm, and the shape of the isolated pattern is, for example, a regular circle having a diameter φ of about 0.2 to 0.3 mm. It is.

  Here, the region corresponding to the region 20b may be covered with the resist pattern 19b. In this case, in the subsequent process, the back surface of the substrate 1 is closed, and the mark 7 (see FIG. 23) is formed on the surface of the substrate 1. Here, when different photomasks are used for the front surface processing and the back surface processing, the back surface processing mask is more versatile because the pattern formation of the mark 7 can be omitted, and the TAT is shortened to reduce the back surface processing mask. Can be provided.

  Next, as shown in FIGS. 21E and 21F, the back surface of the substrate 1 is half-etched (that is, etched halfway in the thickness direction of the substrate 1) using the resist pattern 19b having a regular circular pattern as a mask. Then, the convex portion 40p is formed on the back surface side of the substrate 1. For etching the substrate 1, for example, a ferric chloride solution is used.

  Next, the resist pattern 19a and the resist pattern 19b are removed. 22 (a) and 22 (b), plating layers 3a and 3b using a metal such as silver (Ag) or palladium (Pd) on the front surface and the back surface of the substrate 1, respectively (for convenience of explanation, the surface 3a on the side and 3b on the back side). The plating layers 3a and 3b may be formed before the substrate 1 is etched. After the convex portion 40p is formed on the back surface of the substrate 1 and the plating layer 3 is formed, a plurality of regular circles emerges there.

  Also, a support substrate 21 coated with an adhesive 25 as shown in FIG. 22C is prepared before or after such plating treatment or the like.

  Next, as shown in FIG. 22 (d), the back surface of the substrate 1 that has been subjected to the plating treatment is pressed against the surface of the support substrate 21 to which the adhesive 25 has been applied to adhere.

  Next, as shown in FIGS. 22E and 22F, a resist pattern 19c is formed on the surface of the substrate 1 so as to overlap the projections 40p in a plane.

  Next, as shown in FIGS. 23A and 23B, using the regular circular resist pattern 19c as a mask, etching is performed until the substrate 1 penetrates from the front surface side to the back surface side, thereby forming the post 40. After the post 40 is formed, the resist pattern 19c is removed from the surface of the post 40 as shown in FIGS. 23 (c) and 23 (d). Thereby, the substrate 6 is completed. The post 40 formed in the second region 20b functions as the mark 7.

  Thereafter, the process up to the encapsulation of the mold resin 61 of the process A of the third embodiment is performed, and the support substrate 21 coated with the adhesive 25 is peeled off together with the adhesive 25. Then, the semiconductor device 100 is formed by fixing the front surface side using an ultraviolet curable film (a film that becomes brittle by being irradiated with ultraviolet rays and can be easily peeled off), and dicing using the blade 302 from the back surface. can do. The back side of the post 40 exposed from the resin package may remain covered with the plating layer 3b, or a solder ball or the like may be placed so as to cover the plating layer 3b.

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2a ... Resist pattern, 2a '... Photoresist layer, 2b' ... Photoresist layer, 2b ... Resist pattern, 2c ... Resist pattern, 2d ... Resist pattern, 2e ... Resist pattern, 2f ... Resist pattern, 2g ... Resist pattern, 2h ... resist pattern, 3a ... plating layer, 3b ... plating layer, 5 ... post, 6 ... substrate, 7 ... mark, 7 '... mark precursor, 7a ... alignment mark, 8 ... recognition mark, 9 ... Dicing mark, 10 ... substrate, 11 ... IC element, 12 ... adhesive, 13 ... gold wire, 14 ... mold resin, 16a ... resist pattern, 16b ... resist pattern, 16c ... resist pattern, 16d ... resist pattern, 16e ... resist Pattern, 16f ... resist pattern, 17a ... resist pattern, 17b ... registry 18a ... resist pattern, 18b '... resist pattern, 18b' ... photoresist layer, 19a ... resist pattern, 19b ... resist pattern, 19c ... resist pattern, 20a ... first region, 20b ... 2nd area | region, 21 ... support substrate, 23 ... adhesive agent, 25 ... adhesive agent, 40 ... post, 40p ... convex part, 40q ... convex part, 41 ... post base material, 51 ... IC element, 53 ... gold wire, 61 ... Mold resin, 63x ... Recess, 100 ... Semiconductor device, 101 ... Mother board, 102 ... Wiring board area, 103 ... Abandonment area, 104 ... Insulating layer, 104a ... Opening pattern, 105 ... Mounting part, 109 ... Multiple Wiring substrate, 201 ... die pad, 210 ... IC element, 203 ... lead, 211 ... substrate, 213 ... gold wire, 223 ... bump, 225 ... electric 300, an array of semiconductor devices, 301, a metal plate, 302, a blade.

Claims (8)

A substrate having a first surface having a first region and a second surface that surrounds at least a part of the first region in a plan view, and a second surface located on the opposite side of the first surface is prepared. Process,
A plurality of first mask members having the same shape so that a plurality of columns are arranged in a first direction of the first surface in the first region, and a plurality of rows are arranged in a second direction intersecting the first direction. Forming the first region in the first region such that the intervals between the plurality of first mask materials adjacent to each other are the same;
Etching the substrate to form a plurality of convex portions using the plurality of first mask materials as a mask;
Forming a plurality of marks which are located in the second region in parallel with at least a part of the plurality of first mask materials along the second direction;
Performing alignment between the semiconductor element and the plurality of protrusions using the plurality of marks, and mounting the semiconductor element on a first protrusion of the plurality of protrusions;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of marks includes:
Forming a second mask material in the second region;
Etching the substrate using the second mask material as a mask;
A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein the plurality of first mask materials and the second mask material have the same configuration and are formed at the same time. .
  4. The method of manufacturing a semiconductor device according to claim 2, wherein the step of etching the substrate is performed simultaneously with the step of forming the plurality of convex portions. Manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the mark,
A concave portion is provided in a region surrounding the mark of the substrate, and the mark is provided such that the first surface of the mark and the first surface of the convex portion are located on the same plane. A method of manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 2, wherein the first mask material and the second mask material are a photoresist, a plated layer of a substance different from the substrate, or a combination thereof. A method of manufacturing a semiconductor device, wherein the semiconductor device is a laminated material. Provided in a first region on the first surface side, in a plan view on the first surface side, a plurality of columns in a first direction, a plurality of rows in a second direction intersecting the first direction, A plurality of convex portions adjacent to each other at the same interval along the first direction and the second direction;
Located in a second region adjacent to at least a portion of the first region in plan view on the first surface side, and arranged in parallel with at least a portion of the plurality of convex portions along the second direction. A substrate comprising a plurality of marks. Provided in a first region on the first surface side, in a plan view on the first surface side, a plurality of columns in a first direction, a plurality of rows in a second direction intersecting the first direction, A plurality of convex portions that are adjacent to each other at the same interval along the first direction and the second direction, are electrically separated and mechanically fixed, and at least a part of the first region is planar. A substrate having a plurality of marks arranged in a second region adjacent to each other and arranged in parallel with the plurality of semiconductor elements;
A semiconductor element mounted on at least one of the plurality of protrusions;
An array of semiconductor devices, comprising:

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