JP2010015050A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance display quality of a liquid crystal display. <P>SOLUTION: In the display, a first circuit wherein first TFT elements, first electrodes connected to source or drain of the first TFT elements and second electrodes each forms a counterpart to each first electrode are respectively disposed in a matrix shape in a first direction and a second direction is provided in a first region and a second circuit having a plurality of second TFT elements is provided in a second region positioned on the outer side of the first region. The plurality of second electrodes disposed in the matrix shape are made common to each second electrode arranged along the first direction and each of the second electrodes which are made common is connected to any one of a plurality of power supplying wiring lines for a common electrode via third TFT elements provided in a third region positioned on the outer side of the first region and on the outer side of the second region of the surface of an insulating substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a technique effective when applied to a TFT liquid crystal display device in which a circuit having a TFT element is disposed outside a display region of a liquid crystal display panel.

  2. Description of the Related Art Conventionally, a liquid crystal display device is a display device having a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates. It is used for displays.

  A liquid crystal display panel used for a display unit of a portable electronic device is a display panel that displays an image or an image by a driving method called an active matrix type, and a display region thereof is a TFT element used as an active element or a TFT element. A first electrode connected to the source (hereinafter referred to as a pixel electrode), a second electrode paired with the pixel electrode (hereinafter referred to as a counter electrode), and a set of pixels having a liquid crystal layer.

  In addition, the active matrix liquid crystal display panel includes a plurality of scanning signal lines, a plurality of video signal lines, and a plurality of common electrode power supply wirings in addition to the TFT elements, pixel electrodes, and counter electrodes. It has been.

  At this time, in each of the plurality of scanning signal lines, a portion passing through the display area extends in the first direction, and a portion passing through the display area of each scanning signal line is aligned in the second direction. Yes. At this time, each of the plurality of video signal lines extends in the second direction through the display area, and the part through the display area of each video signal line is aligned in the first direction. It is out. That is, a lattice of a plurality of scanning signal lines and a plurality of video signal lines is formed in the display area. The TFT element of each pixel is disposed in the vicinity of the lattice point (position where the scanning signal line and the video signal line intersect) of the lattice, the gate is connected to one scanning signal line, and the drain Is connected to one video signal line. At this time, the TFT elements of the respective pixels have different combinations of the scanning signal line to which the gate is connected and the video signal line to which the drain is connected.

  Further, the second electrode of each pixel is connected to a common electrode power supply wiring provided outside the display region.

  When the liquid crystal display panel is driven, for example, a video signal (grayscale voltage) to be applied to the pixel electrode of each pixel is generated based on a signal input from the outside, and the generated grayscale voltage is applied in a predetermined order and predetermined At the same time, a signal for selecting a pixel (pixel electrode) to which the gradation voltage applied to the video signal line is written is applied to each scanning signal line. At this time, a common potential voltage is applied to the counter electrode of each pixel through the common electrode power supply wiring. Then, by controlling the direction of the liquid crystal molecules in the liquid crystal layer according to the strength of the electric field that changes in accordance with the potential difference between the gradation voltage applied to the pixel electrode and the voltage applied to the counter electrode, Control light transmission or reflectance.

  At this time, the driving method of the liquid crystal display panel is, for example, a driving method called a vertical electric field driving method and a driving method called a horizontal electric field driving method depending on the direction of the electric lines of force for driving the liquid crystal molecules of the liquid crystal layer. Broadly divided. In a vertical electric field drive type liquid crystal display panel, a TFT element and a pixel electrode are provided on one of a pair of substrates, and a counter electrode is provided on the other substrate. In a horizontal electric field drive type liquid crystal display panel, a TFT element, a pixel electrode, and a counter electrode are provided on one of a pair of substrates.

  In addition, the driving method of the liquid crystal display panel is classified by, for example, the relationship of the polarity of each pixel in one frame period, that is, the relationship between the potential of the gradation voltage applied to the pixel electrode of each pixel and the potential of the counter electrode There are things to do. When the driving method of the liquid crystal display panel is classified according to the relationship of the polarity of each pixel in one frame period, there are various driving methods, and one of them is a driving method called line inversion driving.

  In the line inversion drive, for example, when the relationship between the polarities of the pixels in one frame period is viewed, the polarities of the pixels arranged along the extending direction of the scanning signal lines are the same, and the extending direction of the video signal lines In this driving method, the two adjacent pixels have opposite polarities.

  In line inversion driving, as a method of making the polarities of two pixels adjacent in the extending direction of the video signal line opposite to each other, for example, the potentials of the counter electrodes of the two pixels are fixed to the same potential. In another method, the potential of the gradation voltage applied to the pixel electrode of one pixel is made higher than the potential of the counter electrode, and the potential of the gradation voltage applied to the pixel electrode of the other pixel is made lower than the potential of the counter electrode. is there.

  In line inversion driving, as a method of making the polarities of two pixels adjacent in the extending direction of the video signal line opposite to each other, for example, there is a method of combining a driving method called common inversion. In line inversion driving combined with common inversion, for example, two potentials of a first potential and a second potential are prepared as the potential of the counter electrode, and one of two pixels adjacent in the extending direction of the video signal line is prepared. The counter electrode of one pixel is set to the first potential, and the counter electrode of the other pixel is set to the second potential. Thus, a liquid crystal display panel that performs line inversion driving combined with common inversion can reduce driving power as compared with a liquid crystal display panel that uses line inversion driving in which the electrodes of the counter potentials of all pixels in one frame period are equal. it can.

  By the way, the conventional liquid crystal display panel is used as a driving circuit for generating a video signal to be applied to a video signal line or a driving circuit for generating a scanning signal to be applied to a scanning signal line. A semiconductor device (driver IC) was used. However, in recent liquid crystal display panels, for example, those drive circuits may be built in a substrate having TFT elements, pixel electrodes, and the like.

  In recent liquid crystal display panels, for example, a predetermined number of video signals (gradation signals) input to one video signal input terminal are applied to a substrate having a video signal line of a pair of substrates. A switch circuit for distributing the video signal lines may be incorporated.

  In the case where a driver circuit or a switch circuit is incorporated in a substrate having a TFT element, a pixel electrode, a scanning signal line, a video signal line, and the like out of a pair of substrates, these circuits are provided outside the display region. At this time, the drive circuit and the switch circuit are circuits having TFT elements. At this time, since the drive circuit and the switch circuit need to be operated at high speed, it is desirable that a part or all of the semiconductor layers of the TFT elements of these circuits is a polycrystalline semiconductor such as polycrystalline silicon.

  However, in the TFT element in the display area of the conventional liquid crystal display panel, for example, the semiconductor layer is often formed of an amorphous semiconductor such as amorphous silicon.

Therefore, in a liquid crystal display panel in which a drive circuit and a switch circuit are built outside the display area, for example, the TFT elements in the display area are all formed of amorphous silicon, and the TFT elements outside the display area are semiconductor layers. A method has been proposed in which a part or all of these are formed of polycrystalline silicon (see, for example, Patent Document 1).
JP-A-5-55570

  When a liquid crystal display panel is driven by line inversion driving combined with common inversion, the liquid crystal display panel is provided with, for example, a first common electrode power supply wiring and a second common electrode power supply wiring, A pixel having a counter electrode connected to the first common electrode power supply wiring and a pixel having a counter electrode connected to the second common electrode power supply wiring when the pixels arranged in the extending direction are viewed. And alternately. Then, during one frame period, by applying a first potential voltage to the first common electrode power supply wiring and applying a second potential voltage to the second common electrode power supply wiring, line inversion driving is performed. Is realized.

  At this time, the plurality of counter electrodes arranged in a matrix in the display area are shared by the counter electrodes of the pixels arranged along the extending direction of the scanning signal line. For example, the extension of the scanning signal line One strip-like electrode extending long in the direction is opposed to the pixel electrode of each pixel, thereby functioning as a counter electrode of each pixel.

  Incidentally, when the liquid crystal display panel is driven, it is usually driven by a method called frame inversion in which the polarity of the pixel is inverted every predetermined frame period (for example, every frame period). Therefore, in line inversion driving combined with common inversion, the potential of the counter electrode, which was the first potential in a certain frame period, is changed to, for example, the second potential in the next frame period.

  In recent liquid crystal display devices, there is an increasing demand for a narrow frame, and the number of first common electrode power supply lines and second common electrode power supply lines arranged outside the display region tends to be reduced. There is. Therefore, in recent liquid crystal display devices, for example, many common counter electrodes are connected to one common electrode power supply wiring.

  In a conventional liquid crystal display device that is driven by line inversion driving combined with such common inversion, the potentials of all the counter electrodes connected to one common electrode power supply wiring are set to different potentials during frame inversion. change. For this reason, in a liquid crystal display device having such a driving method, for example, the potential of the counter electrode of a pixel having a pixel electrode to which a gradation voltage is applied just before the end of a certain frame period is changed immediately after the start of the next frame period. Changes to the potential. Still further, for example, in a plurality of common counter electrodes connected to one common electrode power supply wiring, the time difference between the start time of the frame period and the time when the gradation voltage is applied to the pixel electrode becomes longer. The time until the potential of the counter electrode changes to another potential is shortened. For this reason, the liquid crystal display device having such a driving method has a problem in that the shading in the vertical direction occurs and the display quality deteriorates.

  Furthermore, in the conventional liquid crystal display device driven by line inversion driving combined with common inversion, a number of common counter electrodes are connected to one common electrode power supply wiring. There is a problem that the load capacity when the voltage applied to the common electrode power supply wiring is changed from the first potential to the second potential is increased, resulting in an increase in power consumption.

  An object of the present invention is to provide a technique capable of improving the display quality of a liquid crystal display device.

  Another object of the present invention is to provide a technique capable of reducing power consumption of a liquid crystal display device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of typical inventions among the inventions disclosed in the present application will be described as follows.

  (1) A plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFT elements, a plurality of first electrodes, a plurality of second electrodes, and a plurality of common lines on the surface of the insulating substrate An electrode power supply wiring is provided, and a first TFT element, a first TFT connected to a source or drain of the first TFT element, is disposed on the first region of the surface of the insulating substrate. A first circuit in which an electrode and a second electrode paired with the first electrode are arranged in a matrix in a first direction and a second direction, respectively, are provided; A display device in which a second circuit having a plurality of second TFT elements is provided on a second region located outside the first region, wherein the plurality of the plurality of second TFT elements are provided. The common electrode power supply wiring is arranged outside the first region, and the matrix The plurality of second electrodes arranged in a square shape are shared by the second electrodes arranged along the first direction of the first region, and the shared Each of the second electrodes is outside one of the plurality of common electrode power supply wirings and the first region of the surface of the insulating substrate, and the second electrode The display device is connected via a third TFT element provided in a third region located outside the region.

  (2) In the display device according to (1), each of the plurality of scanning signal lines includes a portion passing through the first region and a portion passing through the outside of the first region. The portions of the scanning signal lines passing through the first region each extend along the first direction, and the portions of the scanning signal lines passing through the first region are A third TFT element, which is arranged along the second direction and is interposed between the common second electrode and the common electrode power supply wiring, has a gate connected to a scanning signal line. Display device.

  (3) In the display device of (2), the gates of the first TFT elements connected to the first electrode paired with each of the common second electrodes are the same. The first TFT connected to the scanning signal line, and the gate of the third TFT element is connected to the first electrode paired with the second electrode connected to the third TFT element. A display device connected to the same scanning signal line as the gate of the TFT element.

  (4) In the display device of (1), the plurality of common electrode power supply wirings include a first common electrode power supply wiring and a second common electrode power supply wiring. The plurality of second electrodes arranged in the direction are connected to the first common electrode power supply wiring via the third TFT element, and the third electrode A display device in which the second electrodes connected to the second common electrode power supply wiring through the TFT elements are alternately arranged.

  (5) In the display device according to (4), the first common electrode power supply wiring and the second common electrode power supply wiring have different potentials applied during one frame period and are determined in advance. A display device in which a potential of a voltage applied to the first common electrode power supply wiring and a potential of a voltage applied to the second common electrode power supply wiring are switched every frame period.

  (6) In the display device of (1), the second circuit includes a video signal input terminal to which a video signal applied to each of the plurality of video signal lines is input, and the plurality of video signal lines. One video signal input terminal is connected to each of a predetermined number of video signal lines among the plurality of video signal lines via the second TFT element. Display device.

  (7) In the display device of (1), each of the plurality of first TFT elements arranged in a matrix has a gate connected to one scanning signal line, and the drain or the source The one not connected to the first electrode is one video signal line, and the scanning signal line and the drain are connected to the gate of each first TFT element. Alternatively, the display device includes a circuit that generates a video signal to be applied to each of the plurality of video signal lines, in which the combination with the video signal line connected to the source is different.

  (8) In the display device according to (1), the first TFT element includes a semiconductor layer entirely made of an amorphous semiconductor, and the second TFT element and the third TFT element are formed of a semiconductor layer. A display device partly or entirely made of a polycrystalline semiconductor.

  (9) In the display device according to (1), the first TFT element has a semiconductor layer entirely made of an amorphous semiconductor, and the second TFT element and the third TFT element are formed of a semiconductor layer. A display device comprising a collection of band-shaped semiconductor single crystals, a part or all of which extends long in substantially the same direction as the channel length direction.

  (10) In the display device according to (8) or (9), the first TFT element, the second TFT element, and the third TFT element are respectively formed on the surface of the insulating substrate. A display device in which a gate electrode, a gate insulating film, and the semiconductor layer are stacked in this order.

  (11) In the display device of (1), the plurality of scanning signal lines, the plurality of video signal lines, the plurality of TFT elements, the plurality of first electrodes, and the plurality of second electrodes. The insulating substrate provided with the plurality of common electrode power supply wirings is one of the pair of substrates in the liquid crystal display panel in which a liquid crystal material is sealed between the pair of substrates. Display device.

  According to the present invention, the display quality of a display device driven by line inversion driving combined with common inversion can be improved. Further, according to the present invention, it is possible to reduce power consumption of a display device that is driven by line inversion driving combined with common inversion.

Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.

FIG. 1A to FIG. 1D are schematic views showing an example of a schematic configuration of a conventional liquid crystal display device related to the present invention.
FIG. 1A is a schematic plan view showing an example of a schematic configuration of a liquid crystal display panel in a conventional liquid crystal display device. FIG. 1B is a schematic circuit diagram illustrating an example of a circuit configuration of one pixel in the liquid crystal display panel. FIG. 1C is a schematic circuit diagram showing the circuit configuration of one pixel in the liquid crystal display panel in another format. FIG. 1D is a schematic circuit diagram showing an example of the circuit configuration of the display area and the video signal line selection circuit in the liquid crystal display panel shown in FIG.

  The present invention is applied, for example, to a liquid crystal display panel of a liquid crystal display device driven by line inversion driving combined with common inversion. At this time, the liquid crystal display panel has a configuration as shown in FIG. In addition to the liquid crystal display panel, the liquid crystal display device has a plurality of components such as a backlight, for example. However, since the present invention relates to the configuration of the liquid crystal display panel, the explanation of the other components is as follows. Omitted.

  The liquid crystal display panel is a display panel in which a liquid crystal material (not shown) is sealed between a pair of substrates, a first substrate 1 and a second substrate 2, and includes a plurality of scanning signal lines GL and a plurality of video signals. Line DL, first common electrode power supply line CB1, second common electrode power supply line CB2, a plurality of common lines CL, a plurality of video signal input lines DTL, a video signal line selection circuit 3, and a drive signal It has an input line 4 and the like. At this time, a plurality of scanning signal lines GL, a plurality of video signal lines DL, a first common electrode power supply wiring CB1, a second common electrode power supply wiring CB2, a plurality of common wirings CL, a plurality of The video signal input line DTL, the video signal line selection circuit 3, and the drive signal input line 4 are provided on the first substrate 1, for example. At this time, the first substrate 1 has an area larger than that of the second substrate 2 and, for example, an IC chip 5 for driving the liquid crystal display panel is mounted in a region not overlapping the second substrate 2. ing.

Each of the plurality of scanning signal lines GL has one end connected to the IC chip 5 and a portion passing through the display area DA and a portion passing outside the display area DA. At this time, the portion of each scanning signal line GL passing through the display area DA extends in the first direction (hereinafter referred to as the x direction). At this time, the portions of the scanning signal lines GL passing through the display area DA are arranged in the second direction (hereinafter referred to as the y direction). Furthermore, although a part is omitted in FIG. 1A, the first substrate 1 is provided with a larger number of M scanning signal lines GL. In the following description, when it is necessary to distinguish the M scanning signal lines GL, the subscript m is added, and the scanning signal line GL _m (m is 1, 2, 3,... Any integer). Further, the scanning signal lines GL _m are arranged in the order of GL ₁ , GL ₂ ,..., GL _M from the upper end side of the display area DA, and dummy scanning signal lines are arranged below the scanning signal lines GL _M. It is assumed that GL _{M + 1} is arranged.

Each of the plurality of video signal lines DL has one end connected to the video signal line selection circuit 3, and a portion passing through the display area DA and a portion passing outside the display area DA. At this time, the portion of each video signal line DL passing through the display area DA extends in the y direction. At this time, the portions of the video signal lines DL passing through the display area DA are arranged in the x direction. Furthermore, although a part is omitted in FIG. 1A, the first substrate 1 is provided with a larger number of 3N video signal lines DL. In the following description, when it is necessary to distinguish the 3N video signal lines DL, the subscript n is added, and the video signal line DL _n (n is 1, 2, 3,..., 3N). Any integer). The video signal lines DL _n is from the left side of the display area _DA, DL _1, DL 2, · · ·, _DL are arranged in the order of _3N, in the right side of the video signal line _{DL 3N} dummy video signal line DL _{Assume that 3N + 1} is arranged.

Each of the plurality of common lines CL extends in the x direction and is connected to the first common electrode power supply line CB1 or the second common electrode power supply line CB2 provided outside the display area DA. is doing. At this time, the respective common lines CL are arranged in the y direction and are connected to the common line CL connected to the first common electrode power supply line CB1 and the second common electrode power supply line CB2. The connected common lines CL are alternately arranged. Furthermore, although a part is omitted in FIG. 1A, the first substrate 1 is provided with, for example, M common wirings CL, and two adjacent common wirings CL. A single scanning signal line GL passes between them. In the following description, when it is necessary to distinguish M common wirings CL, the subscript m is added, and the common wiring CL _m (m is 1, 2, 3,... Any integer). Also, common lines CL _m is from the top side of the display area _{DA, CL 1, CL 2,} ···, and are arranged in the order of CL _M.

  In the example shown in FIG. 1A, the first substrate 1 is provided with two first common electrode power supply wirings CB1 and two second common electrode power supply wirings CB2. Of course, it is not limited to this.

The display area DA of the liquid crystal display panel having such a configuration is set by a set of a large number of pixels arranged in a matrix in the x direction and the y direction. At this time, an area occupied by one pixel in the display area DA is, for example, two adjacent scanning signal lines GL _m , GL _{m + 1} (m is any one of 1, 2, 3,..., M). ) And two adjacent video signal lines DL _n and DL _{n + 1} (where n is an integer of 1, 2, 3,..., 3N). At this time, for example, as shown in FIG. 1B, one pixel includes a first TFT element Tr1 and a first electrode PX (hereinafter referred to as a pixel electrode) connected to the source of the first TFT element Tr1. And a second electrode CT (hereinafter referred to as a counter electrode) paired with the pixel electrode PX. That is, in the display area DA, the first TFT element Tr1, the pixel electrode PX, and the counter electrode CT are arranged in a matrix in the x direction and the y direction, respectively. At this time, the first TFT elements Tr1 arranged in a matrix are arranged in the vicinity of the position where the scanning signal line GL _m and the video signal line DL _n intersect, and the gate has one scanning signal. was connected to line GL _m, drain is connected to one video signal line DL _n. At this time, it goes without saying that each first TFT element Tr1 has a different combination of the scanning signal line GL to which the gate is connected and the video signal line DL to which the drain is connected.

The counter electrode CT are arranged in a matrix are respectively connected to the common lines CL _m of one. In this case, among the counter electrodes CT arranged in a matrix, the counter electrode CT aligned along the x direction are commonly by a single common lines CL _m.

Furthermore, one pixel includes, for example, a pixel electrode PX, a counter electrode CT, a pixel capacitor C _LC (also referred to as a liquid crystal capacitor) formed of a liquid crystal material, a pixel electrode PX, a counter electrode CT, and a first electrode A storage capacitor C _STG (also referred to as an auxiliary capacitor or a storage capacitor) formed by an insulating layer formed on one substrate 1. Some recent liquid crystal display panels are not provided with the holding capacitor _CSTG .

In the example shown in FIG. 1B, the gate of the first TFT element Tr1 is connected to the upper scanning signal line GL _m of the two adjacent scanning signal lines GL _m and GL _{m + 1.} However, the present invention is not limited to this, and needless to say, it may be connected to the lower scanning signal line GL _{m + 1} . However, in this case, since the common line CL _{m + 1} passes between the two adjacent scanning signal lines GL _m and GL _{m + 1} , the counter electrode CT of the pixel having the first TFT element Tr1 is made common. It is shared by the wiring CL _{m + 1} .

Further, in the example shown in FIG. 1 (b), the drain of the first TFT element Tr1 is, two video signal lines _DL n adjacent, connected to the left side of the video signal lines DL _n of _{DL n + 1} However, the present invention is not limited to this, and needless to say, it may be connected to the right video signal line DL _{n + 1} .

By the way, when the circuit configuration of one pixel in the liquid crystal display panel is illustrated, for example, as shown in FIG. 1C, only the first TFT element Tr1 and the pixel electrode PX included in one pixel may be shown. . As described above, when the circuit configuration of one pixel is indicated by only the first TFT element Tr1 and the pixel electrode PX, the circuit configuration of the display area DA is, for example, as shown in FIG. Yes. In FIG. 1D, R _{m, n} , G _{m, n} and B _{m, n} (m = 1, 2, 3, 4, n = 1, 2) shown on the pixel electrode PX of each pixel. , N) are video signals (gradation voltages) applied to the respective pixel electrodes PX.

When the liquid crystal display panel is compatible with, for example, RGB color display, one pixel shown in FIGS. 1B and 1C is a pixel called a sub-pixel and has a red filter. A pixel, a pixel having a green filter, and a pixel having a blue filter represent one dot color of an image or an image. At this time, the color of one dot is the video signal R _{m, n} , G _{m, n} , B _{m, n} (for example, the video signal R _1,1 , G _1,1 , B _{1, 1} ) is represented by three pixels having a pixel electrode PX to which each is added.

At this time, the plurality of video signal lines DL arranged in the x direction are, for example, three adjacent video signal lines DL _n , DL _{n + 1} , DL _{n + 2} (n is 1, 2, 3,..., 3N And a set of video signal lines (three video signal lines) via the video signal line selection circuit 3 is divided into N videos. One of the signal input lines DTL _j (j is an integer of any one of 1, 2, 3,..., N), that is, one of the N video signal input terminals DT _j. It is connected. For example, as shown in FIG. 1D, the video signal line selection circuit 3 includes a second TFT interposed between the video signal lines DL _n , DL _{n + 1} , DL _{n + 2} and the video signal input terminal DT _j. An element Tr2 and three selection signal lines DS ₁ , DS ₂ , DS ₃ connected to the gate of the second TFT element Tr2 are provided. At this time, the gates of the three second TFT elements Tr2 connected to each of the set of video signal lines DL _n , DL _{n + 1} , DL _{n + 2} are respectively different selection signal lines DS ₁ , DS ₂ , DS _3. It is connected to the.

  FIG. 2 is a timing chart showing an example of a method for driving the liquid crystal display panel having the configuration shown in FIG.

When driving the liquid crystal display panel having the configuration shown in FIG. 1D, signals applied to the video signal input terminal DT _j , the scanning signal line GL _m , and the selection signal lines DS ₁ , DS ₂ , DS ₃ , for example, The switching control is performed at the timing as shown in FIG.

The scanning signal applied to each scanning signal line GL _m is a signal for selecting the pixel electrode PX to which the video signal applied to each video signal line DL _n is added (written). At this time, the scanning signal applied to each scanning signal line GL _m is a signal having one frame period as one cycle. For example, the mth line selection is performed after one frame period (for example, frame period FLP _{i + 1} ) starts. The signal is such that the voltage is at the H level during the period GSP _m and the voltage is at the L level during the other periods. Note that one line selection period is a period obtained by dividing one frame period by the number M of scanning signal lines GL. The H level voltage is a voltage at which the first TFT element Tr1 is turned on, and the L level voltage is a voltage at which the first TFT element Tr1 is turned off.

The selection signal applied to the selection signal lines DS ₁ , DS ₂ , DS ₃ of the video signal line selection circuit 3 is a video signal line DL for transmitting a video signal (gradation voltage) applied to the video signal input terminal DT _j. Is a signal for selecting. At this time, the selection signal applied to each of the selection signal lines DS ₁ , DS ₂ , DS ₃ is, for example, a signal having one line selection period as one cycle, and one line selection period is the number of video signal lines in one set. The signal is such that the voltage is at the H level only during the selection period divided by and the voltage is at the L level during the other periods. At this time, the selection signal applied to each of the selection signal lines DS ₁ , DS ₂ , DS ₃ is, for example, the selection signal applied to _{one of} the selection signal lines DS ₁ , DS ₂ , DS ₃ . When the voltage is at the H level, the voltage of the selection signal applied to the other two selection signal lines is set to the L level. The H level voltage is a voltage at which the second TFT element Tr2 is turned on, and the L level voltage is a voltage at which the second TFT element Tr2 is turned off.

One video signal input terminal DT ₁ has three video signal lines DL ₁ , DL ₂ , DL ₃ connected to the video signal input terminal DT ₁ via the second TFT element Tr ₂ . Video signals Rm _{, 1} , _{Gm, 1} , _{Bm, 1} are added. At this time, for example, during one line selection period, the video signal input terminal DT ₁ and the video signal lines DL ₁ , DL ₂ , DL ₃ are connected in this order. Therefore, when the video signals R _{m, 1} , G _{m, 1} , B _{m, 1} are added to the video signal input terminal DT ₁ in the order as shown in FIG. 2, the video signal R _{m, 1} becomes the video signal line DL. ₁ , the video signal G _{m, 1} is transmitted (distributed) to the video signal line DL ₂ , and the video signal B _{m, 1} is transmitted to the video signal line DL ₃ . Similarly, when the video signals R _{m, 2} , G _{m, 2} , B _{m, 2} are added to the video signal input terminal DT ₂ in the order shown in FIG. 2, the video signals R _{m, 2} are converted into video signal lines. the DL _4, the video signal _{G m, 2} is the video signal line DL _5, video signal _{B m, 2} is the video signal line DL _6, are respectively transmitted (is distributed). By doing in this way, the video signal applied to the pixel electrode PX of each pixel becomes as shown in FIG. Although not shown in FIGS. 1D and 2, the same applies to each of the video signal input terminals DT _j (j is an integer of 3, 4, 5,..., N). Add the video signal as follows.

  Although detailed description is omitted, the control as shown in FIG. 2 is performed by, for example, the IC chip 5 mounted on the first substrate 1.

  In this manner, when the video signal line selection circuit 3 is provided, the number of video signal input terminals DT can be made smaller than the number of video signal lines DL, so that, for example, the number of video signal output terminals of the IC chip 5 Can be reduced.

  Note that the input timing and switching timing of each signal shown in FIG. 2 are examples, and it is needless to say that the input timing and switching timing of each signal can be changed as appropriate. That is, when the liquid crystal display panel is actually driven, a predetermined video signal (gradation voltage) may be applied to all the pixel electrodes PX in one frame period by a method similar to the example shown in FIG.

FIG. 3A and FIG. 3B are schematic diagrams for explaining an example of a driving method of the liquid crystal display panel having the configuration shown in FIG. 1D and its problems.
FIG. 3A is a schematic circuit diagram showing the polarities of the pixels when the liquid crystal display panel having the configuration shown in FIG. FIG. 3B is a timing chart showing an example of the input timing and switching timing of each signal when the liquid crystal display panel having the configuration shown in FIG.

  As a driving method of the liquid crystal display panel, for example, there is a driving method called line inversion driving. In the line inversion driving, when the polarity of each pixel in one frame period is seen, for example, as shown in FIG. 3A, all the pixels arranged in the extending direction (x direction) of the scanning signal line GL have the same polarity. The driving method is such that two pixels adjacent in the extending direction (y direction) of the video signal line DL have opposite polarities. In FIG. 3A, the polarity of each pixel is indicated by a symbol “+” or “−” attached to each pixel electrode PX, where “+” indicates positive polarity and “−” indicates negative polarity. The positive polarity is the polarity of the pixel when the gradation voltage is expressed by applying a gradation voltage having the same potential as or higher than the voltage of the counter electrode CT to the pixel electrode PX, and the negative polarity is the voltage of the counter electrode CT. This is the polarity of the pixel when the gradation voltage is expressed by applying the gradation voltage of the same potential or lower potential to the pixel electrode PX.

  When a conventional general liquid crystal display panel is driven by line inversion, for example, the potentials of the counter electrodes CT of all the pixels are often made equal. On the other hand, the liquid crystal display panel configured as shown in FIGS. 1A and 1D can be driven by line inversion by combining a driving method called common inversion.

  In the case of line inversion driving combined with common inversion, for example, two kinds of voltages, that is, the voltage of the first potential Vc1 and the voltage of the second potential Vc2 are used as the voltage applied to the counter electrode CT. During one frame period, for example, the first potential Vc1 is applied to the first common electrode power supply line CB1, and the second potential Vc2 is applied to the second common electrode power supply line CB2. . At this time, if the first potential Vc1 is lower than the second potential Vc2, the first potential is applied to the pixel electrode PX of the pixel having the counter electrode CT connected to the first common electrode power supply wiring CB1. The gradation is expressed by applying a gradation voltage having the same potential as Vc1 or higher. At this time, a gradation voltage having a potential equal to or lower than the second potential Vc2 is applied to the pixel electrode PX of the pixel having the counter electrode CT connected to the second common electrode power supply wiring CB2. Express gradation. The polarity of the pixel is determined by the relationship between the potential of the counter electrode CT of the pixel and the potential of the pixel electrode PX. Therefore, the pixel having the counter electrode CT connected to the first common electrode power supply wiring CB1 has a positive polarity, and the pixel having the counter electrode CT connected to the second common electrode power supply wiring CB2 has a negative polarity. Become. Therefore, the same line inversion drive as that in the example shown in FIG.

  At this time, for example, in the next frame period, the voltage of the second potential Vc2 is applied to the first common electrode power supply wiring CB1, and the voltage of the first potential Vc1 is applied to the second common electrode power supply wiring CB2. When the gradation voltage is applied to the pixel electrode PX of each pixel by the method as described above, the polarity of each pixel becomes opposite to the example shown in FIG.

However, in the liquid crystal display panel configured as shown in FIGS. 1A and 1D, when line inversion driving combined with common inversion is performed, the video signal input terminal DT _j , the scanning signal line GL _m , FIG. 3B shows signals or voltages applied to the selection signal lines DS ₁ , DS ₂ , DS ₃ , the first common electrode power supply wiring CB 1, and the second common electrode power supply wiring CB 2, for example. Switching control is performed at such timing.

That is, the voltage applied to the first common electrode power supply line CB1, a potential at frame period FLP _i is When a second potential Vc2, at the beginning of a frame period _{FLP i + 1,} from the second potential Vc2 first The potential is switched to Vc1. At this time, the voltage applied to the second common electrode power supply wiring CB2 is that the potential in the frame period FLP _i is the first potential Vc1, for example, one line selection period has elapsed since the start of the frame period FLP _{i + 1} . when (at the start of the line selection period GSP _2), it is switched from the first potential Vc1 to the second potential Vc2.

At this time, in the plurality of common lines CL _m , the common line CL _{m = odd} whose subscript m is an odd number is connected to the first common electrode power supply line CB1, so the common line CL _{m =} potential of _odd at the beginning of a frame period FLP _i, simultaneously switched from the second potential Vc2 to the first potential Vc1. Similarly, since the common wiring CL _{m = even} having an even subscript m is connected to the second common electrode power supply wiring CB2, the potential of the common wiring CL _{m = even} starts the frame period FLP _{i + 1.} 1 line selection period after the when elapsed (at the start of the line selection period GSP _2), is switched from the first potential Vc1 to the second potential Vc2.

Therefore, assuming that the number M of the scanning signal lines GL (common wiring CL) is an even number, the pixel to which the gradation voltage is applied in the last line selection period GSP _M in the previous frame period FLP _i is the counter electrode CT. The first potential Vc1 and the polarity of the pixel in the frame period FLP _i is positive.

However, as shown in FIG. 3B, the potential of the counter electrode CT of these pixels is determined when one line selection period elapses after the start of the next frame period FLP _{i + 1} (in the line selection period GSP ₂ ). At the start), the first potential Vc1 changes to the second potential Vc2, and the electric field applied to the liquid crystal layer changes.

Such a phenomenon is not limited to the pixel to which the gradation voltage is applied in the last line selection period GSP _M in the previous frame period FLP _i . For example, the gradation voltage is applied to the start time of one frame period and the pixel electrode PX. As the time difference from the time at which is applied is longer, the time until the potential of the counter electrode CT changes to another potential becomes shorter. For this reason, the liquid crystal display device having such a driving method has a problem in that the shading in the vertical direction occurs and the display quality deteriorates.

  Furthermore, in the conventional liquid crystal display device driven by line inversion driving combined with common inversion, a number of common counter electrodes are provided in one common electrode power supply wiring, for example, the first common electrode power supply wiring CB1. CT is connected. Therefore, in such a liquid crystal display device, when the voltage applied to the first common electrode power supply wiring CB1 is switched from the first potential Vc1 to the second potential Vc2, and from the second potential Vc2 to the first potential Vc1. The load capacity when switching to is increased. This also means that the voltage applied to the second common electrode power supply wiring CB2 is switched from the second potential Vc2 to the first potential Vc1, and from the first potential Vc1 to the second potential Vc2. Sometimes it can be said. Therefore, in the conventional liquid crystal display device driven by such a method, there is a problem that the load capacity when switching (reversing) the potential of the counter electrode CT becomes large and the power consumption increases.

FIG. 4A and FIG. 4B are schematic views showing an example of a schematic configuration of a liquid crystal display device according to an embodiment of the present invention.
FIG. 4A is a schematic plan view showing an example of a schematic configuration of the liquid crystal display panel in the liquid crystal display device of the present embodiment. FIG. 4B is a schematic circuit diagram showing an example of the circuit configuration of the counter electrode selection circuit in the liquid crystal display panel shown in FIG.

  The liquid crystal display device of the present embodiment has, for example, a liquid crystal display panel configured as shown in FIG. The configuration of the liquid crystal display panel shown in FIG. 4A is the same as that shown in FIGS. 1A to 1D except that the counter electrode selection circuit 6 is provided outside the display area DA. The configuration is basically the same as that of the display panel. For this reason, in this embodiment, description of portions having the same configuration as the liquid crystal display panel shown in FIGS. 1A to 1D is omitted.

  In the liquid crystal display panel of this embodiment, two counter electrode selection circuits 6 are provided outside the display area DA of the first substrate 1. The counter electrode selection circuit 6 selects the common wiring CL (counter electrode CT) connected to the first common electrode power supply wiring CB1 or the second common electrode power supply wiring CB1 in each line selection period of one frame period. It is a circuit to do. At this time, of the two counter electrode selection circuits 6 arranged outside the display area DA, the counter electrode selection circuit 6 arranged on the left side of the display area DA is a common wiring in the upper half of the display area DA. This circuit selects CL. The counter electrode selection circuit 6 arranged on the right side of the display area DA is a circuit that selects the common wiring CL in the lower half of the display area DA.

At this time, a part of the counter electrode selection circuit 6 arranged on the right side of the display area DA is configured as shown in FIG. 4B, for example. The four common lines CL _m−1 , CL _m , CL _{m + 1} , and CL _{m + 2} shown in FIG. 4B are respectively connected to the first common electrode power supply line CB1 via the third TFT element Tr3. It is connected to the second common electrode power supply wiring CB2. Although not shown, all the common lines CL in the lower half of the display area DA are respectively connected to the first common electrode power supply line CB1 or the second common electrode via the third TFT element Tr3. It is connected to the power supply wiring CB2. At this time, in the y direction of the display area DA, there is a common line CL connected to the first common electrode power supply line CB1 and a common line CL connected to the second common electrode power supply line CB1. They are lined up alternately.

Furthermore, one gate of common lines CL _m and the third TFT element Tr is interposed between the first common electrode power supply line CB1 is opposed electrode connected to the common lines CL _m The gate of the first TFT element Tr of the pixel having CT is connected to the same scanning signal line GL _m . For this reason, the common line CL _m is added to the scanning signal line GL _m in a period during which the third TFT element Tr3 connected to the common line CL _m is on, that is, one frame period. The scan signal is connected to the first common electrode power supply wiring CB1 only for one line selection period GSP _m in which the scanning signal is at the H level.

  The same applies to the other common wirings CL. The first common electrode power supply wiring CB1 or the first common electrode power supply wiring CB1 or only during one line selection period in which the third TFT element Tr3 connected to the common wiring CL is turned on. It is connected to the second common electrode power supply wiring CB2.

  FIG. 5 is a timing chart showing an example of a method for driving the liquid crystal display panel of this embodiment.

The liquid crystal display panel of this embodiment is driven by, for example, line inversion driving combined with common inversion, and the polarity of each pixel is inverted every frame period. At this time, the video signal input terminals DT ₁ , DT ₂ , the scanning signal lines GL ₁ , GL ₂ , GL ₃ , GL ₄ , GL _M , the first common electrode power supply wiring CB 1, and the second common electrode power supply wiring The signal applied to each of CB2 is switched and controlled at the timing as shown in FIG. 5, for example. The switching control of these signals is performed by the line inversion driving combined with the common inversion in the example shown in FIG. 2, that is, in the conventional liquid crystal display panel, and the polarity of each pixel is set every frame period. Since this is the same as the case of inversion, detailed description is omitted.

At this time, assuming that the potential in the frame period FLP _i is the second potential Vc2, the voltage applied to the first common electrode power supply wiring CB1 is the first potential from the second potential Vc2 at the start of the frame period FLP _{i +} 1. Is switched to the potential Vc1. At this time, the voltage applied to the second common electrode power supply line CB2 is the potential the first potential Vc1 in the frame period FLP _i, for example, 1-line selection period is elapsed from the start of the frame period FLP i + ₁ is when (at the start of the line selection period GSP _2), it is switched from the first potential Vc1 to the second potential Vc2.

However, in the liquid crystal display panel of this embodiment, common lines CL _m connected to the first common electrode power supply line CB1, respectively, are connected via the third TFT element Tr3. The third TFT element Tr3 each, only one line selection period GSP _m of the scanning signal of the scanning signal lines GL _m whose gate is connected becomes the H level, is turned on. Therefore, in the frame period FLP _{i + 1} , the potential of each common line CL _m connected to the first common electrode power supply line CB1 is equal to the scanning signal line GL _m to which the gate of the third TFT element Tr3 is connected. When the scanning signal changes from the L level to the H level, the second voltage Vc2 is switched to the first voltage Vc1. Further, the in the next frame period FLP i + _2, each of the potentials of the common lines CL _m connected to the first common electrode power supply line CB1, a scanning signal gate of the third TFT element Tr3 is connected When the scanning signal of the line GL _m changes from the L level to the H level, the first voltage Vc1 is switched to the second voltage Vc2.

From Similarly, each of the common lines CL _m connected to the second common electrode power supply line CB2, the scanning signal of the scanning signal lines GL _m the gate of the third TFT element Tr3 are connected L level When changing to the H level, the first potential Vc1 is switched to the second potential Vc2. Further, the in the next frame period FLP i + _2, each of the potentials of the common lines CL _m connected to the second common electrode power supply line CB2, a scanning signal gate of the third TFT element Tr3 is connected When the scanning signal of the line GL _m changes from the L level to the H level, the second voltage Vc2 is switched to the first voltage Vc1.

That is, each of the potentials of the common lines CL _m in the liquid crystal display panel of this embodiment is 1 in a time period of a frame period, the first second potential from the potential Vc1 Vc2 or from the second potential Vc2, the 1 is switched to the potential Vc1. At this time, the potential of each of the common lines CL _m is switched at a timing gradation voltage to the pixel electrode PX of the pixel having the common lines CL _m to the connected counter electrode CT is written. Therefore, the liquid crystal display panel of this embodiment can suppress the occurrence of shading in the vertical direction and can improve the display quality.

The liquid crystal display panel of this embodiment, a period in which each of the common lines CL _m is connected to the first common electrode power supply line CB1 or the second common electrode power supply line CB2 by one line selection period Only one common wiring CL is always ensured to be electrically connected to one common electrode power supply wiring in one frame period. Therefore, the number of counter electrodes CT for switching the potential at the same time is much smaller than that of the conventional liquid crystal display panel, and the load capacity generated when switching the potential of the counter electrode CT is reduced. Therefore, the liquid crystal display panel of this embodiment can reduce power consumption.

FIG. 6A to FIG. 6C, FIG. 7A and FIG. 7B, FIG. 8A and FIG. 8B show the first substrate in the liquid crystal display panel of this embodiment. It is a schematic diagram which shows an example of schematic structure.
FIG. 6A is a schematic plan view showing an example of the planar configuration of the pixels of the first substrate in the liquid crystal display panel of the present embodiment. FIG. 6B is a schematic cross-sectional view showing an example of a cross-sectional configuration taken along the line AA ′ in FIG. FIG. 6C is a schematic cross-sectional view showing an example of a cross-sectional configuration along the line BB ′ in FIG.
FIG. 7A is a schematic plan view showing an example of a planar configuration of the video signal line selection circuit in the liquid crystal display panel of the present embodiment. FIG.7 (b) is a schematic cross section which shows an example of the cross-sectional structure in CC 'line of Fig.7 (a).
FIG. 8A is a schematic plan view showing an example of a planar configuration of the counter electrode selection circuit in the liquid crystal display panel of the present embodiment. FIG. 8B is a schematic cross-sectional view showing an example of a cross-sectional configuration taken along the line DD ′ in FIG.

  In principle, the liquid crystal display panel of this embodiment is a vertical electric field driving method in which the pixel electrode PX and the counter electrode CT are arranged on different substrates. It may be a lateral electric field drive system arranged on one substrate 1). However, it is considered that the third TFT element Tr3 is interposed between the common wiring CL that shares the counter electrode CT and the first common electrode power supply wiring CB1 or the second common electrode power supply wiring CB2. Then, a liquid crystal display panel of a horizontal electric field drive method is desirable.

  In the horizontal electric field driving type liquid crystal display panel, a first TFT element Tr 1, a pixel electrode PX, and a counter electrode CT are provided on a first substrate 1. At this time, the first substrate 1 includes a scanning signal line GL, a video signal line DL, a first TFT element Tr1, and the like stacked on the surface of an insulating substrate such as a glass substrate. For example, the configuration is as shown in FIGS. 6 (a) to 6 (c).

  First, a scanning signal line GL and a first insulating layer 101 that covers the scanning signal line GL are formed on the surface of the insulating substrate 100. On the first insulating layer 101, the semiconductor layer 102 of the first TFT element Tr1, the video signal line DL (including the drain electrode of the first TFT element Tr1), and the first TFT element Tr1 A source electrode 103 and a second insulating layer 104 covering them are formed. At this time, the semiconductor layer 102 of the first TFT element Tr1 has, for example, an active layer in which a channel is formed, a drain region, and a source region, all of which are formed of an amorphous semiconductor such as amorphous silicon. Has been. Needless to say, the planar layout of the first TFT element Tr1, that is, the planar shape of the semiconductor layer 102 and the planar shape of the source electrode 103 and the drain electrode portion of the video signal line DL can be appropriately changed.

  Further, on the second insulating layer 104, a common counter electrode CT that extends long along the extending direction (x direction) of the scanning signal line GL and a third insulating layer 105 that covers the counter electrode CT are provided. Is formed. In FIGS. 6A and 6C, a strip-like counter electrode CT extending over a plurality of pixels arranged in the x direction is provided, and the pixel electrode CT of each pixel is used in common. Although the case where the common wiring CL is integrated is taken as an example, the present invention is not limited to this, and an independent counter electrode CT may be formed for each pixel and connected by the common wiring CL for common use. Of course.

  In addition, a comb-like pixel electrode PX having a plurality of slits is formed on the third insulating layer 105. At this time, the pixel electrode PX is connected to the source electrode 103 through a contact hole CH 1 formed in the second insulating layer 104 and the third insulating layer 105. Of course, the number and direction of the slits of the pixel electrode PX can be appropriately changed. Although illustration is omitted, on the third insulating layer 105, for example, a protective film or an alignment film covering the pixel electrode PX is formed.

  As described above, the first TFT element Tr arranged in the display area DA has the gate electrode (scanning signal line GL), the gate insulating film (first insulating layer 101), and the semiconductor on the surface of the insulating substrate 100. In the case of a bottom gate structure in which the layers 102 are stacked in this order, it is desirable that the second TFT element Tr2 of the video signal line selection circuit 3 also has a similar bottom gate structure. At this time, the video signal line selection circuit 3 is configured as shown in FIGS. 7A and 7B, for example.

Selection signal lines DS ₁ , DS ₂ , DS ₃ are formed on the surface of the insulating substrate 100, and the selection signal lines DS ₁ , DS ₂ , DS ₃ are covered with the first insulating layer 101. The selection signal lines DS ₁ , DS ₂ , DS ₃ are formed at the same time in the step of forming the scanning signal lines GL, for example.

  Further, the semiconductor layer 106 of the second TFT element Tr2, the video signal line DL, and the video signal input line DTL are formed on the first insulating layer 101. These are the second insulating layer 104. Covered. The second TFT element Tr2 needs to operate at a higher speed than the first TFT element Tr1. Therefore, it is desirable that the semiconductor layer 106 of the second TFT element Tr2 be formed of a polycrystalline semiconductor such as polycrystalline silicon or an aggregate of strip-shaped semiconductor crystals extending in the channel length direction. At this time, as for the semiconductor layer 106 of the second TFT element Tr2, for example, all of the active layer in which the channel is formed, the drain region, and the source region may be formed of a polycrystalline semiconductor, or the entire active layer may be formed. Or only one part may be formed with the polycrystalline semiconductor. Of course, the planar layout of the second TFT element Tr2, that is, the planar shape of the semiconductor layer 106 and the planar shapes of the video signal input line DTL and the video signal line DL can be changed as appropriate.

  When both the first TFT element Tr1 and the second TFT element Tr2 have a bottom gate structure, the semiconductor layer 102 of the first TFT element Tr1 is formed of amorphous silicon, and the semiconductor layer 106 of the second TFT element Tr2 is formed. Since a method for forming a part or all of them with polycrystalline silicon is described in, for example, Patent Document 1 and the like, detailed description thereof is omitted.

  When the counter electrode selection circuit 6 is provided on the first substrate 1 having the first TFT element Tr1 and the second TFT element Tr2 having such a bottom gate structure, the third TFT element of the counter electrode selection circuit 6 is provided. It is desirable that Tr3 has a similar bottom gate structure. At this time, the configuration of the counter electrode selection circuit 6 is, for example, as shown in FIGS. 8 (a) and 8 (b).

  On the surface of the insulating substrate 100, scanning signal lines GL crossing the formation region of the counter electrode selection circuit 6 are formed, and the first insulating layer 101 is interposed on each scanning signal line GL. The semiconductor layer 107 of the third TFT element Tr is laminated. Further, on the first insulating layer 101, the first common electrode power supply wiring CB1, the second common electrode power supply wiring CB2, and the drain electrode 108 of the third TFT element Tr are formed. At this time, the first common electrode power supply wiring CB1 and the second common electrode power supply wiring CB2 each have the source electrode portion of the third TFT element Tr3.

  Further, on the first insulating layer 101, a second insulation covering the first common electrode power supply wiring CB1, the second common electrode power supply wiring CB2, the drain electrode 108 of the third TFT element Tr3, and the like. A layer 104 is formed, and a strip-shaped counter electrode CT is formed on the second insulating layer 104. At this time, each counter electrode CT is connected to the drain electrode 108 through a contact hole CH 2 formed in the second insulating layer 104.

  A third insulating layer 105 is formed on the second insulating layer 104 to cover the strip-shaped counter electrode CT.

  At this time, the third TFT element Tr3 applies the voltage applied to the first common electrode power supply wiring CB1 or the second common electrode power supply wiring CB2 to the counter electrode during one line selection period in which the third TFT element Tr3 is turned on. It must be rapidly added to CT (common wiring CL). Therefore, like the semiconductor layer 106 of the second TFT element Tr2, the semiconductor layer 107 of the third TFT element Tr3 includes all of the active layer, drain region, and source region where the channel is formed, or all of the active layer. Alternatively, it is desirable that only a part is formed of a polycrystalline semiconductor.

  Thus, the first TFT element Tr1 having the semiconductor layer 102 formed of amorphous silicon is disposed in the display area DA, and the second TFT having the semiconductor layer 106 formed of polycrystalline silicon outside the display area DA. When a third TFT element Tr3 having a semiconductor layer 107 made of polycrystalline silicon is additionally arranged on the first substrate 1 on which the TFT element Tr2 is arranged, the manufacturing procedure thereof is the first TFT element Tr1. The manufacturing procedure of the conventional first substrate 1 having only the second TFT element Tr2 may be the same. Therefore, the liquid crystal display panel of this embodiment can suppress an increase in manufacturing cost.

  As described above, according to the liquid crystal display device (liquid crystal display panel) of the present embodiment, the display quality can be improved. In addition, according to the liquid crystal display device of this embodiment, power consumption can be reduced. In addition, according to the liquid crystal display device of this embodiment, an increase in manufacturing cost can be suppressed.

  Furthermore, according to the liquid crystal display device of the present embodiment, the potential of each common wiring CL (common counter electrode CT) is switched by the third TFT element Tr3, so that it is outside the display area DA. An increase in the number of common electrode power supply wirings to be arranged can be suppressed, and the circuit scale (occupied area) of the counter electrode selection circuit 6 can be reduced. Therefore, it is possible to narrow the frame of the liquid crystal display device.

  The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

  For example, the number of common electrode power supply wirings CB1 and CB2 provided on the first substrate 1, the number of counter electrode selection circuits 6, and the arrangement positions thereof are not limited to the example shown in FIG. Of course it is possible.

  In the above embodiment, the liquid crystal display panel is driven by line inversion driving combined with common inversion. However, the present invention is not limited to this. For example, the present invention is not limited to this. Of course, the present invention can also be applied to a liquid crystal display panel that is driven by combining common inversion with frame inversion driving having the same polarity.

  In the above-described embodiment, the semiconductor layer 102 of the first TFT element Tr1 is formed of amorphous silicon. However, the present invention is not limited thereto, and the entire semiconductor layer 102 of the first TFT element Tr1 is used. Of course, all or part of the active layer may be formed of polycrystalline silicon. In this case, the first TFT element Tr1, the second TFT element Tr2, and the third TFT element Tr3 are not limited to the bottom gate structure described in the above embodiment, and a semiconductor layer and a gate are formed on the surface of the insulating substrate. Of course, a top gate structure in which an insulating film (first insulating layer 101) and a gate electrode (scanning signal line GL) are stacked in this order may be used.

  In the embodiment, the video signal line selection circuit 3 having the second TFT element Tr2 in which all or a part of the semiconductor layer is made of polycrystalline silicon is provided outside the display area DA of the first substrate 1. An example is given. However, the circuit having the second TFT element Tr2 provided outside the display area DA is not limited to the video signal line selection circuit 3, and for example, a circuit that generates a video signal (gradation voltage) to be applied to the video signal line DL. Of course, a circuit for generating a scanning signal to be applied to the scanning signal line GL may be used.

It is a schematic plan view which shows an example of schematic structure of the liquid crystal display panel in the conventional liquid crystal display device. It is a schematic circuit diagram which shows an example of the circuit structure of one pixel in a liquid crystal display panel. It is a schematic circuit diagram which shows the circuit structure of one pixel in a liquid crystal display panel in another format. FIG. 2 is a schematic circuit diagram showing an example of a circuit configuration of a display area and a video signal line selection circuit in the liquid crystal display panel shown in FIG. FIG. 3 is a timing chart illustrating an example of a method for driving the liquid crystal display panel having the configuration illustrated in FIG. FIG. 2 is a schematic circuit diagram illustrating the polarity of a pixel when line inversion driving is performed on the liquid crystal display panel having the configuration illustrated in FIG. FIG. 2 is a timing chart showing an example of input timing and switching timing of each signal when the liquid crystal display panel having the configuration shown in FIG. It is a schematic plan view which shows an example of schematic structure of the liquid crystal display panel in the liquid crystal display device of a present Example. FIG. 5 is a schematic circuit diagram illustrating an example of a circuit configuration of a counter electrode selection circuit in the liquid crystal display panel illustrated in FIG. It is a timing chart figure which shows an example of the drive method of the liquid crystal display panel of a present Example. It is a schematic plan view which shows an example of the plane structure of the pixel of the 1st board | substrate in the liquid crystal display panel of a present Example. It is a schematic cross section which shows an example of the cross-sectional structure in the A-A 'line of Fig.6 (a). It is a schematic cross section which shows an example of the cross-sectional structure in the B-B 'line | wire of Fig.6 (a). It is a schematic plan view which shows an example of the planar structure of the video signal line | wire selection circuit in the liquid crystal display panel of a present Example. It is a schematic cross section which shows an example of the cross-sectional structure in the C-C 'line of Fig.7 (a). It is a schematic top view which shows an example of the plane structure of the counter electrode selection circuit in the liquid crystal display panel of a present Example. It is a schematic cross section which shows an example of the cross-sectional structure in the D-D 'line | wire of Fig.8 (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st board | substrate 100 ... Insulating substrate 101 ... 1st insulating layer 102,106,107 ... Semiconductor layer 103 ... Source electrode 104 ... 2nd insulating layer 105 ... 3rd insulating layer 108 ... Drain electrode 2 ... 1st 2 substrate 3... Video signal line selection circuit 4... Drive signal input line 5... IC chip 6 .. counter electrode selection circuit GL, GL ₁ , GL ₂ , GL ₃ , GL ₄ , GL _m−1 , GL _m , GL _{m + 1} , GL _{m + 2} ... Scanning signal line DL, DL ₁ , DL ₂ , DL ₃ , DL ₄ , DL ₅ , DL ₆ , DL ₇ , DL _3N−1 , DL _3N , DL _n , DL _{n + 1} ... video signal line DTL. Signal input lines DT ₁ , DT ₂ , DT _N ... Video signal input terminal PX ... Pixel electrode CT ... Counter electrode CL, CL _m ... Common wiring CB1 ... First common electrode power supply wiring CB2 ... Second common power Power supply wiring for electrodes DS ₁ , DS ₂ , DS ₃ ... Selection signal line Tr 1... First TFT element Tr 2... Second TFT element Tr 3.

Claims (11)

A plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFT elements, a plurality of first electrodes, a plurality of second electrodes, and a plurality of common electrodes on the surface of the insulating substrate Wiring is provided,
On the first region of the surface of the insulating substrate, a first TFT element, a first electrode connected to a source or drain of the first TFT element, and a pair with the first electrode Are provided with a first circuit in which a second electrode is formed in a matrix in the first direction and the second direction, respectively.
In the display device, a second circuit having a plurality of second TFT elements is provided on a second region located outside the first region on the surface of the insulating substrate. And
The plurality of common electrode power supply wirings are disposed outside the first region,
The plurality of second electrodes arranged in a matrix are shared by the second electrodes arranged along the first direction of the first region,
The shared second electrodes are respectively outside one of the plurality of common electrode power supply wirings and the first region of the surface of the insulating substrate, The display device is connected through a third TFT element provided in a third region located outside the second region. Each of the plurality of scanning signal lines has a portion passing through the first region and a portion passing outside the first region;
The portions of the plurality of scanning signal lines that pass through the first region extend along the first direction, and the portions of the scanning signal lines pass through the first region. Are aligned along the second direction,
2. The third TFT element interposed between the shared second electrode and the common electrode power supply wiring has a gate connected to a scanning signal line. Display device. A gate of the first TFT element connected to the first electrode paired with each of the one shared second electrode is connected to the same scanning signal line;
The gate of the third TFT element has the same scanning signal as the gate of the first TFT element connected to the first electrode paired with the second electrode connected to the third TFT element. The display device according to claim 2, wherein the display device is connected to a line. The plurality of common electrode power supply wirings include a first common electrode power supply wiring and a second common electrode power supply wiring,
A plurality of the second electrodes arranged along the second direction, the second electrode connected to the first common electrode power supply wiring through the third TFT element; The display device according to claim 1, wherein the second electrodes connected to the second common electrode power supply wiring through the third TFT elements are alternately arranged.   The first common electrode power supply wiring and the second common electrode power supply wiring are different in potential applied to a voltage during one frame period, and the first common electrode power supply wiring is determined every predetermined frame period. 5. The display device according to claim 4, wherein a potential of a voltage applied to the electrode power supply wiring and a potential of a voltage applied to the second common electrode power supply wiring are switched. The second circuit is interposed between a video signal input terminal to which a video signal applied to each of the plurality of video signal lines is input and the plurality of video signal lines,
One video signal input terminal is connected to each of a predetermined number of video signal lines among the plurality of video signal lines via the second TFT element. The display device according to claim 1. Each of the plurality of first TFT elements arranged in a matrix has a gate connected to one scanning signal line and connected to the first electrode of the drain or the source. The video signal line connected to the gate and the drain or the source connected to the gate of each of the first TFT elements is the one that is not one video signal line. The combination with is different,
The display device according to claim 1, wherein the second circuit includes a circuit that generates a video signal to be applied to each of the plurality of video signal lines.   In the first TFT element, the semiconductor layer is entirely made of an amorphous semiconductor, and in the second TFT element and the third TFT element, a part or all of the semiconductor layer is made of a polycrystalline semiconductor. The display device according to claim 1.   In the first TFT element, all of the semiconductor layer is made of an amorphous semiconductor, and in the second TFT element and the third TFT element, a part or all of the semiconductor layer is substantially in the same direction as the channel length direction. The display device according to claim 1, wherein the display device is an aggregate of elongated semiconductor semiconductor crystals.   In the first TFT element, the second TFT element, and the third TFT element, a gate electrode, a gate insulating film, and the semiconductor layer are stacked in this order on the surface of the insulating substrate, respectively. The display device according to claim 8, wherein the display device is provided.   The plurality of scanning signal lines, the plurality of video signal lines, the plurality of TFT elements, the plurality of first electrodes, the plurality of second electrodes, and the plurality of common electrodes. The display according to claim 1, wherein the insulating substrate provided with the wiring is one of the pair of substrates in a liquid crystal display panel in which a liquid crystal material is sealed between the pair of substrates. apparatus.

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