JP2009537056A5 - - Google Patents

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Publication number
JP2009537056A5
JP2009537056A5 JP2009508669A JP2009508669A JP2009537056A5 JP 2009537056 A5 JP2009537056 A5 JP 2009537056A5 JP 2009508669 A JP2009508669 A JP 2009508669A JP 2009508669 A JP2009508669 A JP 2009508669A JP 2009537056 A5 JP2009537056 A5 JP 2009537056A5
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JP
Japan
Prior art keywords
analog value
memory cell
value
memory
distortion
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JP2009508669A
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English (en)
Japanese (ja)
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JP2009537056A (ja
JP4999921B2 (ja
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Priority claimed from PCT/IL2007/000580 external-priority patent/WO2007132457A2/en
Publication of JP2009537056A publication Critical patent/JP2009537056A/ja
Publication of JP2009537056A5 publication Critical patent/JP2009537056A5/ja
Application granted granted Critical
Publication of JP4999921B2 publication Critical patent/JP4999921B2/ja
Expired - Fee Related legal-status Critical Current
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JP2009508669A 2006-05-12 2007-05-10 メモリ素子用の歪み推定と誤り訂正符号化の組み合せ Expired - Fee Related JP4999921B2 (ja)

Applications Claiming Priority (19)

Application Number Priority Date Filing Date Title
US74710606P 2006-05-12 2006-05-12
US60/747,106 2006-05-12
US86348006P 2006-10-30 2006-10-30
US60/863,480 2006-10-30
US86381006P 2006-11-01 2006-11-01
US60/863,810 2006-11-01
US86739906P 2006-11-28 2006-11-28
US60/867,399 2006-11-28
US88502407P 2007-01-16 2007-01-16
US60/885,024 2007-01-16
US88610207P 2007-01-23 2007-01-23
US60/886,102 2007-01-23
US89286907P 2007-03-04 2007-03-04
US60/892,869 2007-03-04
US89429007P 2007-03-12 2007-03-12
US60/894,290 2007-03-12
US89445607P 2007-03-13 2007-03-13
US60/894,456 2007-03-13
PCT/IL2007/000580 WO2007132457A2 (en) 2006-05-12 2007-05-10 Combined distortion estimation and error correction coding for memory devices

Publications (3)

Publication Number Publication Date
JP2009537056A JP2009537056A (ja) 2009-10-22
JP2009537056A5 true JP2009537056A5 (https=) 2010-06-03
JP4999921B2 JP4999921B2 (ja) 2012-08-15

Family

ID=41314441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009508669A Expired - Fee Related JP4999921B2 (ja) 2006-05-12 2007-05-10 メモリ素子用の歪み推定と誤り訂正符号化の組み合せ

Country Status (1)

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JP (1) JP4999921B2 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100838292B1 (ko) * 2007-06-20 2008-06-17 삼성전자주식회사 메모리 셀의 읽기 레벨 제어 장치 및 그 방법
CN101842850B (zh) * 2007-10-31 2013-08-21 艾格瑞系统有限公司 多级闪存的系统性纠错
KR101434405B1 (ko) * 2008-02-20 2014-08-29 삼성전자주식회사 메모리 장치 및 메모리 데이터 읽기 방법
KR101378365B1 (ko) * 2008-03-12 2014-03-28 삼성전자주식회사 하이브리드 메모리 데이터 검출 장치 및 방법
US8671327B2 (en) 2008-09-28 2014-03-11 Sandisk Technologies Inc. Method and system for adaptive coding in flash memories
KR101738173B1 (ko) * 2008-09-28 2017-05-19 라모트 앳 텔-아비브 유니버시티 리미티드 플래시 메모리에서의 적응형 코딩 방법 및 시스템
CN102203875B (zh) 2008-09-30 2016-08-03 Lsi公司 使用参考单元的用于存储器器件的软数据生成的方法和装置
US8291297B2 (en) * 2008-12-18 2012-10-16 Intel Corporation Data error recovery in non-volatile memory
US8213255B2 (en) * 2010-02-19 2012-07-03 Sandisk Technologies Inc. Non-volatile storage with temperature compensation based on neighbor state information
US8737138B2 (en) 2010-11-18 2014-05-27 Micron Technology, Inc. Memory instruction including parameter to affect operating condition of memory
US9898361B2 (en) 2011-01-04 2018-02-20 Seagate Technology Llc Multi-tier detection and decoding in flash memories
WO2013065334A1 (ja) * 2011-11-02 2013-05-10 国立大学法人東京大学 メモリコントローラおよびデータ記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4068863B2 (ja) * 2002-03-08 2008-03-26 富士通株式会社 不揮発性多値半導体メモリ
JP3913704B2 (ja) * 2003-04-22 2007-05-09 株式会社東芝 不揮発性半導体記憶装置及びこれを用いた電子装置
JP5183625B2 (ja) * 2006-05-12 2013-04-17 アップル インコーポレイテッド 適応能力を有するメモリ素子
JP5095131B2 (ja) * 2006-05-31 2012-12-12 株式会社東芝 半導体記憶装置
KR100907218B1 (ko) * 2007-03-28 2009-07-10 삼성전자주식회사 읽기 레벨 제어 장치 및 그 방법
KR101425958B1 (ko) * 2007-09-06 2014-08-04 삼성전자주식회사 멀티-비트 데이터를 저장하는 메모리 시스템 및 그것의읽기 방법

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