JP2009508215A5 - - Google Patents

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Publication number
JP2009508215A5
JP2009508215A5 JP2008530073A JP2008530073A JP2009508215A5 JP 2009508215 A5 JP2009508215 A5 JP 2009508215A5 JP 2008530073 A JP2008530073 A JP 2008530073A JP 2008530073 A JP2008530073 A JP 2008530073A JP 2009508215 A5 JP2009508215 A5 JP 2009508215A5
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JP
Japan
Prior art keywords
memory
memory access
access request
signal
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008530073A
Other languages
English (en)
Japanese (ja)
Other versions
JP5058167B2 (ja
JP2009508215A (ja
Filing date
Publication date
Priority claimed from US11/222,615 external-priority patent/US8065457B2/en
Application filed filed Critical
Publication of JP2009508215A publication Critical patent/JP2009508215A/ja
Publication of JP2009508215A5 publication Critical patent/JP2009508215A5/ja
Application granted granted Critical
Publication of JP5058167B2 publication Critical patent/JP5058167B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008530073A 2005-09-09 2006-08-23 メモリアクセス要求の遅延アービトレーション Active JP5058167B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/222,615 2005-09-09
US11/222,615 US8065457B2 (en) 2005-09-09 2005-09-09 Delayed memory access request arbitration
PCT/US2006/032742 WO2007032866A1 (en) 2005-09-09 2006-08-23 Delayed memory access request arbitration

Publications (3)

Publication Number Publication Date
JP2009508215A JP2009508215A (ja) 2009-02-26
JP2009508215A5 true JP2009508215A5 (https=) 2012-08-02
JP5058167B2 JP5058167B2 (ja) 2012-10-24

Family

ID=37562281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008530073A Active JP5058167B2 (ja) 2005-09-09 2006-08-23 メモリアクセス要求の遅延アービトレーション

Country Status (8)

Country Link
US (1) US8065457B2 (https=)
EP (1) EP1922627B1 (https=)
JP (1) JP5058167B2 (https=)
KR (1) KR101262313B1 (https=)
CN (1) CN101258476B (https=)
DE (1) DE602006018959D1 (https=)
TW (1) TWI426387B (https=)
WO (1) WO2007032866A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8195903B2 (en) * 2006-06-29 2012-06-05 Oracle America, Inc. System and method for metering requests to memory
CN102203752B (zh) * 2008-07-29 2014-04-30 新诺普系统公司 具有多个队列之间的仲裁的数据处理电路
TWI370361B (en) * 2008-08-21 2012-08-11 Ili Technology Corp Memory access controlling apparatus and control method thereof
CN101667448B (zh) * 2008-09-04 2012-11-07 奕力科技股份有限公司 存储器存取控制装置及其相关控制方法
JP5418193B2 (ja) * 2009-12-14 2014-02-19 富士ゼロックス株式会社 調停装置、画像処理装置、及び画像形成システム
US20120290810A1 (en) * 2011-04-18 2012-11-15 Jean-Jacques Lecler Memory Access Latency Metering
GB2518884A (en) * 2013-10-04 2015-04-08 Ibm Network attached storage system and corresponding method for request handling in a network attached storage system
WO2015065426A1 (en) * 2013-10-31 2015-05-07 Hewlett-Packard Development Company, L.P. Memory access for busy memory
US9646660B2 (en) * 2014-09-23 2017-05-09 Intel Corporation Selectable memory access time
CN107526534B (zh) * 2016-06-21 2020-09-18 伊姆西Ip控股有限责任公司 管理存储设备的输入输出(i/o)的方法和设备

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400771A (en) * 1975-12-04 1983-08-23 Tokyo Shibaura Electric Co., Ltd. Multi-processor system with programmable memory-access priority control
US5524220A (en) * 1994-08-31 1996-06-04 Vlsi Technology, Inc. Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems
US5892981A (en) 1996-10-10 1999-04-06 Hewlett-Packard Company Memory system and device
US6134625A (en) * 1998-02-18 2000-10-17 Intel Corporation Method and apparatus for providing arbitration between multiple data streams
US6105086A (en) * 1998-06-04 2000-08-15 Lsi Logic Corporation Data communication circuit and method for buffering data between a shared resource and multiple interfaces
TW514788B (en) * 1999-04-23 2002-12-21 Via Tech Inc Method of delayed transaction in bus system and device using the method
US6453401B1 (en) * 1999-07-02 2002-09-17 Rambus Inc. Memory controller with timing constraint tracking and checking unit and corresponding method
US6594730B1 (en) * 1999-08-03 2003-07-15 Intel Corporation Prefetch system for memory controller
US6499090B1 (en) * 1999-12-28 2002-12-24 Intel Corporation Prioritized bus request scheduling mechanism for processing devices
JP2002244919A (ja) * 2001-02-20 2002-08-30 Matsushita Electric Ind Co Ltd Ｄｒａｍインターフェース回路
US7093094B2 (en) * 2001-08-09 2006-08-15 Mobilygen Corporation Random access memory controller with out of order execution
US6745308B2 (en) * 2002-02-19 2004-06-01 Ati Technologies, Inc. Method and system for bypassing memory controller components
US6717834B2 (en) * 2002-03-26 2004-04-06 Intel Corporation Dual bus memory controller
US7099972B2 (en) * 2002-07-03 2006-08-29 Sun Microsystems, Inc. Preemptive round robin arbiter
JP4008307B2 (ja) * 2002-08-09 2007-11-14 松下電器産業株式会社 メモリインターフェース回路
US6857055B2 (en) * 2002-08-15 2005-02-15 Micron Technology Inc. Programmable embedded DRAM current monitor
JP3876816B2 (ja) * 2002-10-24 2007-02-07 日本電気株式会社 コンピュータの共有資源利用制限方法
US7093059B2 (en) * 2002-12-31 2006-08-15 Intel Corporation Read-write switching method for a memory controller
JP2004287576A (ja) * 2003-03-19 2004-10-14 Matsushita Electric Ind Co Ltd バスコントローラ

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