JP2009302334A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is equipped with a good ferroelectric capacitor by forming a good hard mask. <P>SOLUTION: The method of manufacturing a semiconductor device includes steps of: forming a first electrode film 33a above a substrate; forming a ferroelectric film 34a on the first electrode film 33a; forming a second electrode film 35a on the ferroelectric film 34a; forming an aluminum oxide film 41a, a first titanium nitride film 42a, a second titanium nitride film 43a, and a silicon oxide film in order on the second electrode film 35a and patterning them into a mask pattern; and etching the first electrode film 33a, the ferroelectric film 34a, and the second electrode film 35a using the mask pattern as a mask to form a ferroelectric capacitor. In the step of forming the mask pattern, the first titanium nitride film 42a is formed by a sputtering method and the second titanium nitride film 43a is formed by a self-ionized plasma method. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A ferroelectric memory device using spontaneous polarization of a ferroelectric material is expected as a nonvolatile memory device capable of low voltage operation and high speed operation. A ferroelectric memory device includes a large number of memory cells. Since a memory cell can be constituted by one switching element and one ferroelectric capacitor (1T1C), it can be integrated as high as a DRAM and is expected as a large-capacity memory device.

  In such a ferroelectric memory device, the ferroelectric capacitor is formed by sequentially forming a first electrode film, a ferroelectric film, and a second electrode film on the substrate, and then forming a mask pattern (on the second electrode film). The second electrode film, the ferroelectric film, and the first electrode film are sequentially etched using this as a mask (for example, Patent Document 1).

  As the hard mask, for example, a mask in which an aluminum oxide film, a titanium nitride film, and a silicon oxide film are sequentially laminated on a second electrode film has been proposed. In order to form such a hard mask, first, an aluminum oxide film and a titanium nitride film are sequentially formed on the second electrode film by sputtering. Then, a silicon oxide film is formed on the titanium nitride film by a CVD method. Then, a resist pattern is formed on the silicon oxide film, and this is used as a mask to etch the silicon oxide film and pattern it. Then, after removing the resist pattern, the titanium nitride film and the aluminum oxide film are sequentially etched using the patterned silicon oxide film as a mask. Thereby, a hard mask is obtained.

  By the way, if the silicon oxide film is etched during the formation of the hard mask, deposits derived from the etching gas may adhere to the side walls thereof. Further, when the resist pattern is removed, the residue may adhere to the titanium nitride film. In order to make the shape of the hard mask highly accurate, usually, APM cleaning (ammonia hydrogen peroxide solution) is performed before etching the titanium nitride film to remove deposits and residues.

In the ferroelectric memory device, a base conductive film may be formed on the base of the first electrode film. The base conductive film includes an oxygen barrier film, a crystallinity improving conductive film made of a metal having excellent self-orientation, and the like. Specifically, a film made of titanium aluminum nitride (TiAlN) or a film made of titanium nitride (TiN) is used, and the resistance is increased by oxidation of plugs and wirings provided on the lower layer side of the underlying conductive film. And the crystallinity of the ferroelectric film can be improved. These films are also etched and patterned using the hard mask as a mask.
JP 2007-81013 A

However, even if such a hard mask is used, the shape cannot be maintained for the following reasons, and the ferroelectric capacitor may not be formed in a good shape.
The titanium nitride film formed by the sputtering method is wet-etched by APM cleaning, and the film may be reduced or the surface may be roughened. Therefore, it is also conceivable to form a dense titanium nitride film by using a self-ionized plasma method (Self-Ionized Plasma method, hereinafter referred to as SIP method), and to lower the etching rate in the APM cleaning of this film. However, arcing (abnormal discharge) may occur during film formation by the SIP method, and film peeling may occur due to this. Further, since the film formed by the SIP method has a dense film quality and a large film stress, if it is formed to have a film thickness necessary for the hard mask, the film stress accumulates and the film is not easily peeled off. Needless to say, the hard mask in which film peeling has occurred cannot function normally in etching.

  Further, when the underlying conductive film is etched using the hard mask as a mask, the hard mask may penetrate. Specifically, both the base insulating film and the hard mask are formed of a titanium-containing metal, and it is difficult to secure an etching selectivity between them. Usually, the titanium nitride film of the hard mask is also used when etching the base conductive film. Etched. After the titanium nitride film of the hard mask is removed, the aluminum oxide film functions as a mask.

  However, the aluminum oxide film formed by the sputtering method may be removed when the base conductive film is etched. As a result, the ferroelectric capacitor is over-etched, causing a shape collapse such as a shoulder drop. In addition, even if an aluminum oxide film is formed to be thick, the silicon oxide film is remarkably reduced when it is patterned, and the shape of the hard mask cannot be maintained.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a good ferroelectric capacitor by forming a good hard mask.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first electrode film above a substrate, a step of forming a ferroelectric film on the first electrode film, and a second step on the ferroelectric film. A step of forming an electrode film, and an aluminum oxide film, a first titanium nitride film, a second titanium nitride film, and a silicon oxide film are sequentially formed on the second electrode film, and a mask pattern is formed by patterning. And using the mask pattern as a mask, etching the first electrode film, the ferroelectric film, and the second electrode film to form a ferroelectric capacitor. In the forming step, the first titanium nitride film is formed by a sputtering method, and the second titanium nitride film is formed by a self-ionization plasma method.

  When the silicon oxide film is etched and patterned, foreign matter may adhere to the exposed second titanium nitride film. The foreign matter is, for example, a removed resist pattern residue or a deposit during etching. Usually, foreign matters are removed by APM cleaning with ammonia hydrogen peroxide solution. However, a titanium nitride film formed by sputtering may be wet etched by APM cleaning, resulting in film loss or surface roughness. As a result, the ferroelectric capacitor cannot be satisfactorily patterned.

  In the method of the present invention, since the second titanium nitride film is formed by the self ionization plasma method (SIP method), the film quality is denser than the film formed by the sputtering method. Therefore, the amount of etching of the second titanium nitride film by APM cleaning can be remarkably reduced, and the film thickness reduction and surface roughness can be suppressed, and the first titanium nitride film can be protected from APM cleaning. Can do. Therefore, the thickness of the first titanium nitride film and the second titanium nitride film can be ensured and the surface thereof can be improved, and the mask pattern can function normally by etching in the process of forming the ferroelectric capacitor. it can. Thereby, the ferroelectric capacitor can be formed in a desired shape, and a highly reliable ferroelectric capacitor can be formed. As described above, according to the present invention, a good semiconductor device including a good ferroelectric capacitor can be manufactured.

  Further, the first titanium nitride film is formed by the sputtering method, and the film stress can be reduced as compared with the case where it is formed by the SIP method. Therefore, the first titanium nitride film is prevented from peeling from the aluminum oxide film, and the mask pattern can function normally. Thereby, a favorable ferroelectric capacitor can be formed.

In the step of forming the mask pattern, the aluminum oxide film is preferably formed by an atomic layer growth method.
A film formed by atomic layer deposition (hereinafter referred to as ALD method) has a denser film quality than a film formed by sputtering. Therefore, when films having the same film thickness are compared, a film formed by the ALD method has a lower etching rate than a film formed by the sputtering method. Therefore, it can function well as part of the mask pattern. For example, even when the first titanium nitride film and the second titanium nitride film are removed by etching, the mask pattern can function normally. Thereby, a highly reliable ferroelectric capacitor can be formed.

  In addition, before the step of forming the first electrode, there is a step of forming a base conductive film above the substrate, and after the step of forming the ferroelectric capacitor, the mask pattern is used as a mask. Preferably, the method includes a step of etching the base conductive film. In this case, the step of forming the base conductive film includes a process of forming an oxygen barrier film constituting at least a part of the base conductive film. Preferably, the oxygen barrier film is more preferably formed of a titanium-containing metal.

  If the base conductive film is formed, for example, the function of improving the orientation of the ferroelectric film can be given to the base conductive film, and a good ferroelectric capacitor can be formed thereon. If the underlying conductive film is etched using the mask pattern as a mask, it is possible to omit the process of forming the mask pattern separately, so that it is possible to efficiently form a good ferroelectric capacitor. Become. Moreover, since the aluminum oxide film is formed by the ALD method as described above, it is prevented from being removed during the etching of the underlying conductive film, and a highly reliable ferroelectric capacitor can be formed.

In general, the ferroelectric film is formed of a metal oxide such as lead zirconate titanate ((Pb (Zi, Ti) O ₃ ), hereinafter referred to as PZT). When the ferroelectric film is reduced, its characteristics deteriorate. Therefore, the film forming process is usually performed in an oxygen atmosphere. On the other hand, conductive parts such as plugs and wirings that are electrically connected to the first electrode increase in resistance when oxidized.
If the oxygen barrier film constituting the base conductive film is formed, the conductive portion can be prevented from being oxidized in the ferroelectric film forming process, and a good semiconductor device can be obtained.

  Further, if the oxygen barrier film is formed of a titanium-containing metal, titanium is a material particularly excellent in self-orientation, so that an oxygen barrier film having a good crystal orientation can be formed. Therefore, it is possible to form a first electrode having a good crystal orientation on the oxygen barrier film, reflecting the crystal orientation, and to form a ferroelectric film having a good crystal orientation on the first electrode. it can. In this way, a good ferroelectric capacitor can be formed.

When the oxygen barrier film is formed of a titanium-containing metal, the etching selectivity is ensured between this film and the first titanium nitride film made of titanium-containing metal or the second titanium nitride film made of titanium-containing metal. It becomes difficult to do. Therefore, when the oxygen barrier film is etched, the first titanium nitride film and the second titanium nitride film are also etched. In an extreme case, these are completely removed.
According to the present invention, even when the first titanium nitride film and the second titanium nitride film are completely removed, the aluminum oxide film formed by the ALD method on the lower layer side functions well as a mask pattern. Therefore, a ferroelectric capacitor can be formed without causing shape collapse. Further, the aluminum oxide film can function as a stopper film to pattern the base conductive film and remove the first titanium nitride film and the second titanium nitride film. This increases the efficiency of the process of removing the mask pattern.

  Hereinafter, although one embodiment of the present invention is described, the technical scope of the present invention is not limited to the following embodiment. In the following description, various structures are illustrated using drawings, but in order to show the characteristic parts of the structures in an easy-to-understand manner, the structures in the drawings are shown in different sizes and scales from the actual structures. There is. First, the configuration of an example of a semiconductor device obtained by the manufacturing method of the present invention will be described. The semiconductor device of this example includes a large number of memory cells having ferroelectric capacitors and switching elements.

  FIG. 1 is a side sectional configuration diagram showing the main part of the ferroelectric memory device of this example. As shown in FIG. 1, the ferroelectric memory device 1 has a stack type structure, and includes a base 2 having a transistor 22 and a ferroelectric capacitor 3 provided on the base 2.

The base 2 includes a transistor 22 provided on a silicon substrate (substrate) 21 made of, for example, single crystal silicon, and a base insulating film 23 made of SiO ₂ provided so as to cover the transistor 22. . An element isolation region 24 is provided on the surface layer of the silicon substrate 21, and the space between the element isolation regions 24 corresponds to one memory cell.

  The transistor 22 includes a gate insulating film 221 provided on the silicon substrate 21, a gate electrode 222 provided on the gate insulating film 221, source regions 223 provided on both sides of the gate electrode 222 on the surface of the silicon substrate 21, and The drain region 224 and sidewalls 225 provided on the side surfaces of the gate electrode 222 are configured. In this example, a first plug 25 that is electrically connected to the source region 223 is provided, and a second plug 26 that is electrically connected to the source region 223 is provided to the drain region 224.

  The first plug 25 and the second plug 26 are made of a conductive material such as W (tungsten), Mo (molybdenum), Ta (tantalum), Ti, or Ni (nickel). In this example, the first plug 25 is electrically connected to a bit line (not shown), and the source region 223 and the bit line are electrically connected through the first plug 25.

In the present embodiment, a crystallinity improving conductive film (underlying conductive film) 31 and an oxygen barrier film (underlying conductive film) 32 are formed in order from the lower layer side on the second plug 26 and the underlying insulating film 23 around it. Yes. A ferroelectric capacitor 3 is formed on the oxygen barrier film 32.
The ferroelectric capacitor 3 includes a lower electrode (first electrode film) 33 formed on the oxygen barrier film 32, a ferroelectric film 34 formed thereon, and an upper electrode (first electrode) formed thereon. 2 electrode film) 35. The lower electrode 33 is electrically connected to the second plug 26 through the oxygen barrier film 32 and the crystallinity improving conductive film 31. That is, the lower electrode 33 and the drain region 224 are electrically connected.

  The crystallinity improving conductive film 31 is made of a conductive material such as TiN, and the oxygen barrier film 32 is made of a conductive material having an oxygen barrier property such as TiAlN, TiAl, TiSiN, TiN, TaN, and TaSiN. It is. The crystallinity improving conductive film 31 and the oxygen barrier film 32 are preferably made of a material containing Ti that is particularly excellent in self-orientation. In this way, the crystal orientation of the lower electrode 33 and the ferroelectric film 34 is changed. Can be good.

  The lower electrode 33 is made of a single layer film or a multilayer film. As the film constituting the lower electrode, at least one of Ir (iridium), Pt (platinum), Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), or an alloy thereof, Alternatively, a film made of these oxides can be used. The lower electrode 33 of this example is a multilayer film in which an iridium film, an iridium oxide film, and a platinum film (not shown) are sequentially laminated from the lower layer side.

The ferroelectric film 34 is made of a ferroelectric material having a perovskite crystal structure represented by a general formula of ABO ₃ . For example, the A-site metal is composed of Pb or a part of Pb substituted with La (lanthanum), Ca (calcium), or Sr (strontium). Further, for example, the B-site metal is made of Zr (zirconium) or Ti, and V (vanadium), Nb (niobium), Ta, Cr (chromium), Mo (molybdenum), W (tungsten), and Mg (magnesium). ) May be added.

Specific examples of the ferroelectric material include PZT, SBT, (Bi, La) ₄ Ti ₃ O ₁₂ (bismuth lanthanum titanate: BLT), and the like. Since PZT has a track record as a ferroelectric material, it can be made highly reliable by using it. In the case of using PZT, it is preferable to make the Ti content larger than the Zr content from the viewpoint of increasing the spontaneous polarization amount. In this case, from the viewpoint of improving the hysteresis characteristics, it is preferable that the crystal structure has a (111) orientation belonging to the face-centered cubic crystal.

  In this example, the upper electrode 35 is electrically connected to a ground line (not shown) and is made of a single layer film or a multilayer film. As the film constituting the upper electrode, a film made of Al (aluminum), Ag (silver), Ni (nickel), or the like can be used in addition to the film applicable to the lower electrode described above. In this example, a multilayer film in which a platinum film, an iridium oxide film, and an iridium film (not shown) are sequentially laminated from the lower layer side.

  With the above structure, when a voltage is applied to the gate electrode 222 of the transistor 22, an electric field is applied between the source region 223 and the drain region 224 to turn on the channel, and a current flows therethrough. It becomes possible. When the channel is turned on, an electric signal from the bit line electrically connected to the source region 223 is transmitted to the drain region 224 and further to the lower electrode of the ferroelectric capacitor 3 electrically connected to the drain electrode 224. 33. Thereby, a voltage can be applied between the upper electrode 35 and the lower electrode 33 of the ferroelectric capacitor 3, and charges (data) can be accumulated in the ferroelectric film 34. As described above, the ferroelectric memory device 1 can read or write data (charges) by switching the electric signal to the ferroelectric capacitor 3 with the transistor 22.

  Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described. This embodiment will be described based on a method for manufacturing the ferroelectric memory device 1.

  2 (a) to (c), FIG. 3 (a) to (c), FIG. 4 (a) to (c), FIG. 5 (a) to (c), and FIG. 6 (a) to (c). FIG. 6 is a cross-sectional process diagram illustrating a method for manufacturing the ferroelectric memory device 1. In FIG. 2B and subsequent figures, the lower layer structure of the base 2 such as the transistor 22 is omitted.

  First, as shown in FIG. 2A, the base 2 is formed using a known method or the like. Specifically, for example, the element isolation region 24 is formed on the silicon substrate 21 by the LOCOS method, the STI method, or the like, and the gate insulating film 221 is formed on the silicon substrate 21 between the element isolation regions 24 by the thermal oxidation method or the like. Then, a gate electrode 222 made of polycrystalline silicon or the like is formed on the gate electrode 222. Then, impurities are implanted into the surface layer of the silicon substrate 21 between the element isolation region 24 and the gate electrode 222 to form doped regions 223 and 224. Then, a sidewall 225 is formed using an etch back method or the like. Then, impurities are again implanted into the doped regions 223 and 224 outside the sidewall 225 to form high-concentration impurity regions. In this embodiment, the doped region 223 functions as a source region, and the doped region 224 functions as a drain region.

Then, a base insulating film 23 is formed on the silicon substrate 21 on which the transistor 22 is formed by depositing SiO ₂ by, for example, a CVD method. Then, the base insulating film 23 on the source region 223 and the drain region 224 is etched to form a through hole that exposes the source region 223 and a through hole that exposes the drain region 224. Then, in each of these through holes, for example, Ti and TiN are sequentially formed by sputtering to form an adhesion layer (not shown).

  Then, tungsten is formed on the entire surface of the base insulating film 23 including the inside of the through hole by, for example, a CVD method, and the tungsten is embedded in the through hole. Then, the tungsten on the base insulating film 23 is removed by polishing the base insulating film 23 by a CMP method or the like. In this way, the first plug 25 is embedded in the through hole on the source region 223, and the second plug 26 is embedded in the through hole on the drain region 224. The base 2 is obtained as described above.

Next, as shown in FIG. 2B, a crystallinity improving conductive film 31a is formed on the second plug 26 and on the underlying insulating film 23 around it. Specifically, the surface of the second plug 26 and the base insulating film 23 is exposed to NH ₃ plasma to improve the self-orientation of titanium. Then, a titanium film is formed on the base insulating film 23 by using, for example, a CVD method or a sputtering method. Titanium has a high self-orientation and is enhanced by the surface treatment, so that it can have a good crystal orientation and a (001) -oriented close-packed film belonging to hexagonal crystal is formed. The Then, the crystallinity-improving conductive film 31a made of TiN is formed by a nitriding process in which the film is subjected to a heat treatment (for example, 500 ° C. or more and 650 ° C. or less) in a nitrogen atmosphere. When the temperature of the heat treatment is less than 650 ° C., the thermal effect on the transistor 22 can be reduced. If the temperature is 500 ° C. or higher, the nitriding treatment can be shortened. The formed crystallinity improving conductive film 31a has a (111) orientation belonging to the face-centered cubic crystal, reflecting the orientation of Ti in the original metal state.

  Next, as shown in FIG. 2C, a TiAlN film is formed on the crystallinity improving conductive film 31a by sputtering to form an oxygen barrier film 32a. The oxygen barrier film 32a can be formed in an epitaxial-like manner by matching the crystal orientation with the crystallinity improving conductive film 31a serving as the base. That is, the (111) oriented oxygen barrier film 32a can be formed reflecting the crystal orientation of the crystallinity improving conductive film 31a.

Next, as shown in FIG. 2D, the stacked body 3a is formed on the oxygen barrier film 32a. The multilayer body 3a will later become the ferroelectric capacitor 3 (see FIG. 1).
First, iridium, iridium oxide, and platinum are sequentially formed on the oxygen barrier film 32a by a sputtering method to form a lower electrode 33a composed of these three layers. The lower electrode 33a film can control the crystallinity by reflecting the crystal orientation of the oxygen barrier film 32a, and the uppermost platinum film can be formed in the (111) orientation. Then, on the lower electrode 33a, for example, PZT is formed by a sol-gel method (CSD method), a sputtering method, an MOCVD method, or the like to form a ferroelectric film 34a. The ferroelectric film 34a can be formed in the (111) orientation reflecting the crystal orientation of the lower electrode 33 serving as the base. Then, platinum, iridium oxide, and iridium are sequentially formed on the ferroelectric film 34a by a sputtering method to form the upper electrode 35a composed of these three layers.

Next, a hard mask (mask pattern) is formed on the stacked body 3a.
First, as shown in FIG. 3A, an aluminum oxide film 41a is formed on the upper electrode 35a by ALD. Specifically, the substrate 2 on which the laminate 3a is formed is placed in the film forming chamber of the ALD apparatus. If necessary, the upper electrode 35 is subjected to a surface treatment, and the end of the bond on the surface is a hydroxyl group (OH). Then, an aluminum-containing source gas, for example, trimethylaluminum (Al (CH ₃ ) ₃ ) is supplied into the film forming chamber, and this source gas is reacted with the hydroxyl group on the surface of the upper electrode 35a. Thereby, one of the hydrogen atom of the hydroxyl group and the methyl group of trimethylaluminum is removed, and dimethylaluminum (—Al (CH ₃ ) ₂ ) is bonded to the surface of the upper electrode 35a via the oxygen atom. Then, after exhausting trimethylaluminum and the like in the film formation chamber, water vapor is supplied into the film formation chamber to react with dimethylaluminum. As a result, the methyl group of dimethylaluminum is replaced with a hydroxyl group, and the hydrogen atom of the hydroxyl group is partially removed, so that the oxygen atom is bonded to two aluminum atoms. In this way, an atomic layer of aluminum oxide can be formed on the upper electrode 35a. By repeating this process, the atomic layer is laminated to form an aluminum oxide film having a desired thickness.

  According to the ALD method, the surface of each atomic layer can be controlled, and the aluminum oxide film 41a having a finer film quality than that obtained by the sputtering method can be formed. Therefore, a film formed by the ALD method has a thinner film thickness required to function as a mask than a film formed by the sputtering method. In other words, the selectivity with respect to a film made of titanium nitride or the like can be improved without increasing the thickness. Here, the aluminum oxide film 41a is formed to a thickness equivalent to a normal thickness (for example, about 20 nm).

  Next, as shown in FIG. 3B, a first titanium nitride film 42a is formed on the aluminum oxide film 41a by sputtering. Specifically, the substrate 2 on which the aluminum oxide film 41a is formed is placed in the film forming chamber of the sputtering apparatus. Then, using a target made of titanium, the substrate temperature is set to 200 ° C., nitrogen gas (reactive gas) and argon gas (inert gas) are circulated in the film forming chamber, and an aluminum oxide film is formed by reactive sputtering. Titanium nitride is deposited on 41a. In this way, the first titanium nitride film 42a having a thickness of, for example, about 150 nm is formed.

  Next, as shown in FIG. 3C, a second titanium nitride film 43a is formed on the first titanium nitride film 42a by the SIP method. Specifically, the substrate 2 on which the first titanium nitride film 42a is formed is placed in the film forming chamber of a sputtering apparatus using SIP technology. The SIP technology is a technology that realizes a high ionization density by high-density plasma by applying a high DC voltage on a magnetic field distribution having a strong electron confinement capability. Then, the substrate temperature is set to 200 ° C., nitrogen gas (reactive gas) and argon gas (inert gas) are circulated in the film forming chamber, and titanium nitride is deposited on the first titanium nitride film 42a by reactive sputtering. Form a film. Thereby, for example, a second titanium nitride film 43a having a thickness of about 50 nm is formed. As described above, the first titanium nitride film 42a and the second titanium nitride film 43a having different film qualities are stacked so that the total thickness of the stacked films is about 200 nm. Hereinafter, the difference in characteristics between the film formed by the sputtering method and the film formed by the SIP method will be described.

  FIGS. 7A to 7C are graphs showing a comparison of physical property values of a film formed by a sputtering method and a film formed by a SIP method. FIG. 7A shows a comparison of film densities, and FIG. Shows a comparison of wet etching rates, and FIG. 7C shows a comparison of dry etching rates. In FIGS. 7A to 7C, the symbol A indicates a titanium nitride film formed by sputtering, and the symbol B indicates a titanium nitride film formed by SIP.

The film A formed by the sputtering method uses ENDURA (manufactured by APPLICED MATLS INC.) As a sputtering apparatus, and its 101 chamber is used as a film formation chamber. The film was formed at a power of 8 kW for 50 seconds.
The film B formed by the SIP method is formed by using the ENDURA SIP chamber as a film formation chamber, forming a film for 50 seconds at an argon gas flow rate of 16 sccm, a nitrogen gas flow rate of 75 to 100 sccm, and a film formation power of 18 kW.

  As shown in FIG. 7A, it can be seen that the film by the SIP method has a higher film density than the film by the sputtering method and has a dense film quality. Further, as shown in FIG. 7B, the film by the SIP method has a wet etching rate by APM cleaning or the like of about 1/10 that of the film by the sputtering method. As shown in FIG. 7C, the dry etching rate of the film by the SIP method is about twice that of the film by the sputtering method.

  Note that the same tendency applies to films formed using other sputtering apparatuses. For example, when a CERAUS ZX-1000 (manufactured by ULVAC) is used as a sputtering apparatus, a film is formed for 246 seconds with an argon gas flow rate of 10 sccm, a nitrogen gas flow rate of about 20 sccm, and a film formation power of 2.5 kW. Results were obtained.

In the SIP method, the film is formed by using high-density plasma and increasing the film formation power as compared with the normal sputtering method. For this reason, abnormal discharge called arcing may occur during film formation, and film peeling may occur starting from a portion damaged by the abnormal discharge. In addition, since the film stress is larger than that of a film formed by a normal sputtering method, the film may be peeled off when attempting to form a film with a certain thickness (for example, 200 nm).
In the present invention, since only the second titanium nitride film 43a is formed by the SIP method among the laminated films of the first titanium nitride film 42a and the second titanium nitride film 43a, the lamination is performed without causing film peeling. The film can be of a predetermined thickness.

  Next, as shown in FIG. 4A, a silicon oxide film 44a is formed on the second titanium nitride film 43a. Specifically, the substrate 2 on which the second titanium nitride film 43a is formed is disposed in the film forming chamber of the CVD apparatus. Then, the substrate temperature is set to 390 ° C., and a mixed gas composed of TEOS gas (tetraethoxysilane), oxygen gas, helium, etc. is circulated in the film forming chamber. Then, a silicon oxide film having a thickness of about 700 to 800 nm is formed on the second titanium nitride film 43a by a CVD method to form a silicon oxide film 44a.

Next, as shown in FIG. 4B, after a resist material is formed on the silicon oxide film 44a by a coating method or the like, this film is patterned using a photolithography method and an etching technique to form a resist pattern R. Form.
Next, as shown in FIG. 4C, the silicon oxide film 44a is etched using the resist pattern R as a mask, and is patterned.

  Next, as shown in FIG. 5A, the resist pattern R is removed by ashing or the like. When the silicon oxide film 44a is patterned, deposits derived from the etching gas may adhere to the side walls. In addition, a residue of the resist pattern R may adhere to the second titanium nitride film 43a exposed between the silicon oxide films 44a. Here, the deposits and residues are removed by APM cleaning using ammonia hydrogen peroxide solution. When APM cleaning is performed, the second titanium nitride film 43a is wet etched. The second titanium nitride film 43a is formed by the SIP method, and as shown in FIG. 7B, the wet etching rate is remarkably lower than the film formed by the sputtering method. Therefore, film loss due to wet etching (APM cleaning) and surface roughness due to side etching or the like are significantly reduced. Therefore, the second titanium nitride film 43a can be maintained in a good state, and the first titanium nitride film 42a covered with the second titanium nitride film 43a can be protected from wet etching.

  Next, as shown in FIG. 5B, the second titanium nitride film 43a, the first titanium nitride film 42a, and the aluminum oxide film 41a are sequentially dry-etched using the patterned silicon oxide film 44a as a mask. The silicon oxide film 44a is also etched by dry etching, and the film thickness is reduced. For example, reactive ion etching (RIE) or sputter etching is used to etch with a high degree of anisotropy. If physical etching is made stronger than chemical etching, the selectivity can be ensured depending on the material. It becomes difficult. That is, the amount of etching of the silicon oxide film 44a when patterning the aluminum oxide film 41a mainly depends on the thickness of the aluminum oxide film 41a. As described above, since the aluminum oxide film 41a is formed without increasing the thickness, the silicon oxide film 44a is prevented from penetrating when it is patterned. Therefore, the second titanium nitride film 43a is exposed in the penetrating portion, and is prevented from being etched and damaged. As described above, a good hard mask 4 composed of the silicon oxide film 44a, the second titanium nitride film 43a, the first titanium nitride film 42a, and the aluminum oxide film 41a patterned is obtained.

Next, as shown in FIG. 5C, the upper electrode 35a, the ferroelectric film 34a, and the lower electrode 33a are sequentially dry-etched and patterned using the hard mask 4 as a mask to form the ferroelectric capacitor 3. . Here, patterning is performed by plasma etching using a mixed gas of hydrogen bromide (HBr), oxygen gas, argon, and octafluorocyclobutane (C ₄ F ₈ ) as an etching gas. Since the good hard mask 4 is formed as described above, the ferroelectric capacitor 3 can be formed in a good shape.
In the middle of this process or a later process, one layer or two or more layers constituting the hard mask 4 may be completely removed by etching. In the present invention, when at least a part of the initial hard mask formed functions, it is also referred to as a hard mask even when some of the layers are removed.

Next, as shown in FIG. 6A, if the silicon oxide film 44a remains, it is removed by dry etching or wet etching.
Next, as shown in FIG. 6B, using the hard mask 4 from which the silicon oxide film 44a has been removed as a mask, the oxygen barrier film 32a and the crystallinity improving conductive film 31a are sequentially dry etched and patterned. To do. Here, patterning is performed using the base insulating film 23 as a stopper film, and the first titanium nitride film 42a and the second titanium nitride film 43a are removed by the dry etching using the aluminum oxide film 41a as a stopper film. Since the aluminum oxide film 41a is a dense film formed by the ALD method, the aluminum oxide film 41a is prevented from being penetrated by dry etching. As a result, surface roughness or the like is prevented from occurring in the upper electrode 35, and a good ferroelectric capacitor 3 can be obtained. In addition, the process of removing the first titanium nitride film 42a and the second titanium nitride film 43a after forming the ferroelectric capacitor 3 can be omitted.
Note that if the base insulating film is composed of a plurality of layers, and the uppermost layer is formed of a material (for example, SiN) that can ensure the selection ratio with respect to the crystallinity-improving conductive film 31a, it can function well as a stopper film. be able to.

In the present embodiment, the aluminum oxide film 41a is retained without being removed, and recovery annealing is performed after appropriately performing APM cleaning or the like. Specifically, the substrate 2 on which the ferroelectric capacitor 3 is formed is heat-treated in an oxygen atmosphere. In the case where oxygen vacancies are generated in the ferroelectric film 34 of the ferroelectric capacitor 3, this can be recovered, and a good ferroelectric capacitor 3 can be obtained. If recovery annealing is performed with the upper surface of the upper electrode exposed, surface roughening may occur here. In the present embodiment, since the aluminum oxide film 41a is satisfactorily held during the patterning of the oxygen barrier film 32a and the crystallinity improving conductive film 31a, the upper electrode 35 can be protected by the aluminum oxide film 41a during the recovery annealing. In addition, since it is not necessary to separately form a film for protecting the upper electrode 35, the process is simplified.
Further, the ferroelectric memory device 1 shown in FIG. 1 is obtained by removing the aluminum oxide film 41a. When a hydrogen barrier film is formed so as to cover the ferroelectric capacitor 3, the aluminum oxide film 41a may not be removed but may be part of the hydrogen barrier film.

  In the method for manufacturing a semiconductor device according to the present invention, the second titanium nitride film 43a is formed by the SIP method on the first titanium nitride film 42a by the sputtering method. A good hard mask 4 that does not cause film loss or surface roughness by APM cleaning can be obtained. Therefore, by using a good hard mask 4 as a mask, the etching is stabilized, and the ferroelectric capacitor 3 can be formed satisfactorily. Therefore, a highly reliable ferroelectric capacitor 3 can be obtained, and a good semiconductor device including the same can be manufactured.

1 is a side cross-sectional configuration diagram showing a main part of a ferroelectric memory device. (A)-(d) is process drawing which shows the manufacturing method of a ferroelectric memory device. (A)-(c) is process drawing which continues from FIG.2 (d). (A)-(c) is process drawing which continues from FIG.3 (c). (A)-(c) is process drawing which continues from FIG.4 (c). (A)-(c) is process drawing which continues from FIG.5 (c). (A)-(c) is a graph which shows the difference in the film quality by the difference in the film-forming method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 3 ... Ferroelectric capacitor, 31, 31a ... Crystallinity improvement electrically conductive film (underlying conductive film), 32, 32a ... Oxygen barrier film (underlying electrically conductive film), 33, 33a ... Lower electrode (first electrode film), 34, 34a ... Ferroelectric film, 35, 35a ... Upper electrode (second electrode film), 4 ... Hard mask (mask pattern), 41a ... aluminum oxide film, 42a ... first titanium nitride film, 43a ... second titanium nitride film, 44a ... silicon oxide film

Claims (5)

Forming a first electrode film above the substrate;
Forming a ferroelectric film on the first electrode film;
Forming a second electrode film on the ferroelectric film;
Forming an aluminum oxide film, a first titanium nitride film, a second titanium nitride film, and a silicon oxide film in order on the second electrode film, and patterning to form a mask pattern;
Etching the first electrode film, the ferroelectric film, and the second electrode film using the mask pattern as a mask to form a ferroelectric capacitor, and forming the mask pattern Then, the first titanium nitride film is formed by a sputtering method, and the second titanium nitride film is formed by a self-ionized plasma method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the mask pattern, the aluminum oxide film is formed by an atomic layer growth method.   Before the step of forming the first electrode, there is a step of forming a base conductive film over the substrate, and after the step of forming the ferroelectric capacitor, the mask pattern is used as a mask. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of etching the conductive film.   The method for manufacturing a semiconductor device according to claim 3, wherein the step of forming the base conductive film includes a process of forming an oxygen barrier film constituting at least a part of the base conductive film.   The method of manufacturing a semiconductor device according to claim 4, wherein the oxygen barrier film is formed of a titanium-containing metal.

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