JP2003258201A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can efficiently etch a ferroelectric capacitor structure, and to provide a method for manufacturing a semiconductor device which can form a ferroelectric capacitor structure having a sidewall almost vertical by dry etching. <P>SOLUTION: The method for manufacturing the semiconductor device comprises (a) the step of sequentially laminating an oxygen barrier conductive layer, a lower electrode layer, a ferroelectric layer and an upper electrode layer on a semiconductor substrate for exposing a conductive surface for a contact in an insulting surface, (b) the step of forming a hard mask including a first layer and a second layer on the upper electrode layer, and (c) the step of forming a capacitor structure by etching the upper electrode layer, the ferroelectric layer, the lower electrode layer and the oxygen barrier conductive layer by plasma etching with the hard mask used as an etching mask. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a ferroelectric capacitor.

[0002]

2. Description of the Related Art A ferroelectric random access memory (FeRAM) using a ferroelectric capacitor as a memory element.
Can form a non-volatile memory cell with 1 transistor / 1 capacitor. An oxide perovskite type ferroelectric is often used as the ferroelectric.

In order to improve the degree of integration of FeRAM, a conductive plug embedded in an interlayer insulating film is formed on the source / drain regions of the field effect transistor, and the conductive plug is connected to the plug to form a ferroelectric capacitor on the interlayer insulating film. Planar stack capacitor structures that form In order to form a capacitor having an electrode facing area as large as possible within a limited area, it is desired to pattern the capacitor structure in a direction as close to vertical as possible.

Conventionally, the electrodes and the ferroelectric film of the ferroelectric capacitor are patterned by etching using a photoresist pattern as a mask. Photoresist is
Vertical etching was extremely difficult because of insufficient etching resistance.

When attempting to etch a capacitor structure vertically, it is desirable to use a hard mask instead of a resist mask. When the hard mask is formed of a single-layer silicon oxide film, peeling easily occurs at the interface between the hard mask and the upper electrode under the high bias conditions required when etching the ferroelectric or noble metal electrode. Further, if the hard mask of the silicon oxide film is removed by dry etching, the etching gas causes a change in the film quality of the upper electrode and damages.

A single-layer hard mask made of a barrier material such as TiN is easy to remove after the etching process by a process that does not damage the upper electrode. However, if etching is performed in the absence of oxygen, the hard mask and P
It is difficult to obtain a high etch selectivity with a ferroelectric film such as bZrTiO ₃ (PZT). When oxygen is added,
The etch selectivity can be increased, but the etch rate of the ferroelectric substance is reduced, and taper is likely to occur.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of efficiently etching a ferroelectric capacitor structure.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of forming a ferroelectric capacitor structure having side walls close to vertical by dry etching.

[0009]

According to one aspect of the present invention, a) an oxygen barrier conductive layer, a lower electrode layer, a ferroelectric layer and an upper portion on a semiconductor substrate having a contact conductive surface exposed in an insulating surface. Stacking an electrode layer, (b) forming a hard mask including a first layer and a second layer on the upper electrode layer, and (c) plasma etching using the hard mask as an etching mask to form the upper portion. Provided is a method for manufacturing a semiconductor device, comprising the steps of etching an electrode layer, a ferroelectric layer, a lower electrode layer, and an oxygen barrier conductive layer to form a capacitor structure.

[0010]

1 (A) to 3 (J) are sectional views showing the main processes of a method of manufacturing a semiconductor device according to an embodiment of the present invention. This embodiment includes a plurality of modified examples.

As shown in FIG. 1A, an element isolation region 12 of silicon oxide or the like is formed on the surface of a silicon substrate 11 having a p-type surface region. The element isolation region 12 is formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). The element isolation region 12 defines a plurality of active regions on the surface of the silicon substrate 11. An insulating gate electrode G is formed on the surface of each active region by stacking the gate insulating film 13, the polycrystalline silicon gate electrode 14, and the silicide gate electrode 15. N-type source / drain regions 16 are formed on the surface of the silicon substrate on both sides of the insulated gate electrode G by ion implantation or the like.

An interlayer insulating film 18 made of, for example, silicon oxide covers the gate electrode G to form a flat insulating surface. A layer that functions as an etch stopper such as silicon nitride may be provided as the surface layer of the interlayer insulating film 18. A through hole is formed through the interlayer insulating film 18 and a conductor such as tungsten is embedded to form a conductor plug 19 leading the source / drain region 16 to the surface. The surface of the conductor plug 19 is made flush with the surface of the interlayer insulating film 18 by chemical mechanical polishing (CMP) or the like, and a laminated layer forming a ferroelectric capacitor structure is formed on the surface.

First, the oxygen barrier conductor layer 1 is made of Ir.
A layer, a TiN layer, a TiAlN layer, etc. are created. Ir, Pt, I as the lower electrode layer 2 is formed on the oxygen barrier conductor layer 1.
A single layer or a laminated layer of rO, SRO (SrRuO _x ) or the like is formed. An oxide ferroelectric layer 3, such as PZT (PbZrTiO _x ), SBT (SrBiTa), is formed on the lower electrode 2.
An oxide perovskite type ferroelectric layer such as O _x ), BLT (BiLaTiO _x ) or the like is formed. On the oxide ferroelectric layer 3, a noble metal such as Pt or Ir as the upper electrode layer 4, Ir
A single layer or a stack of oxide conductor layers such as O, SRO, and PtO is formed.

A stack including a first layer 5 and a second layer 6 for a hard mask is formed on the upper electrode layer 4. For example, the first
The layer 5 is formed of TiN, TaN, TiAlN or the like. The second layer 6 is formed of a SiO ₂ film formed by, for example, CVD, plasma CVD, spin-on-glass (SOG) or the like.

As shown in FIG. 1B, a photoresist layer is formed on the hard mask layers 5 and 6 and exposed and developed to form a photoresist pattern PR. The photoresist pattern PR is formed on the region forming the capacitor structure. Using the photoresist pattern PR as an etching mask, the hard mask layers 5 and 6 underneath are etched. After patterning the hard masks 5 and 6, the photoresist pattern PR is removed.

As shown in FIG. 1 (C), the laminated hard masks 5 and 6 are used as etching masks, and the upper electrode layer 4, the ferroelectric layer 3, the lower electrode layer 2 and the oxygen barrier conductor layer 1 below the hard masks 5 and 6 are formed. The ferroelectric capacitor structure is formed under the hard mask layers 5 and 6 by successively performing high density plasma etching.

FIG. 4 shows the structure of an inductively coupled plasma etching apparatus for performing high density plasma etching. The chamber 30 is provided with a coil 31 on the outer side of the quartz side wall, and the coil 31 is connected to a high frequency power supply 32. High frequency can be applied to the chamber by inductive coupling.

Counter electrodes 34 and 35 are provided in the chamber 30. The lower electrode is a stage, on which the workpiece 8 such as a wafer is placed. Stage 35
Is connected to a low frequency power supply 37 of 400 to 450 kHz. Further, the stage 35 is provided with a pipe 36, and the stage 35 can be kept at a constant temperature by water cooling.

As shown in FIG. 2D, the second hard mask layer 5 formed of silicon oxide may disappear during the etching of the ferroelectric capacitor structure. The second hard mask layer 6 is removed by dry etching, or the second hard mask layer 6 is removed after dry etching,
The first hard mask layer 5 is exposed.

As shown in FIG. 2E, a TiO ₂ layer, A
An encapsulation film 8 covering the ferroelectric capacitor structure is formed by an insulating layer having a hydrogen shielding function such as an l ₂ O ₃ layer. An insulating thin layer having such an encapsulation function may be laminated as a part of the first layer of the hard mask layer.

As shown in FIG. 2F, an interlayer insulating film 9 such as a silicon oxide layer is formed so as to cover the encapsulation layer 8 and the surface is flattened. A via hole 20 reaching the upper electrode 4 of each ferroelectric capacitor from the surface of the interlayer insulating film 9 is formed, and a W layer or the like is embedded to form a conductor plug 2
1 is formed. A wiring layer is formed on the interlayer insulating film 9 and patterned to form the wiring 22 connected to the conductor plug 21. The conductor plug 21 and the wiring
22 and 22 may be integrally formed.

Although a part of the hard mask layer is left as it is in the above-mentioned embodiment, it is not essential to leave the hard mask layer. The example will be described below. Figure 3
As shown in (G), hard mask stacks 5 and 6 having sufficient etching resistance are formed, and the ferroelectric mask structures 4 and 3 are formed using the hard masks as etching masks.
2, 1 are successively etched to form a ferroelectric capacitor structure.

As shown in FIG. 3H, the hard mask stacks 6 and 5 are removed. For example, when an etch stopper layer is formed on the surface of the interlayer insulating film 18, the silicon oxide layer 6 is removed with diluted hydrofluoric acid, and the first hard mask layer such as TiN is removed with (ammonium fluoride + hydrogen peroxide). May be removed.
All of the hard mask stack used to etch the ferroelectric capacitor structure is removed to expose the ferroelectric capacitor structure.

As shown in FIG. 3 (I), the ferroelectric capacitor structure is covered with an encapsulation film 8 having a hydrogen shielding function, and an interlayer insulating film 9 is formed thereon. The surface of the interlayer insulating film 9 is flattened by CMP or the like. A via hole 20 is formed from the surface of the interlayer insulating film 9 to the upper electrode of the ferroelectric capacitor structure, and a conductor plug 21 is embedded therein.
The wiring 22 is formed on the surface of the conductor plug 21. The wiring 22 and the conductor plug 21 may be formed in separate steps, but may be integrally formed in the same step.

The etching performed in the step of FIG. 1C may be performed at room temperature, but may be performed at a high temperature of 200 ° C. or higher to promote the etching rate. Hereinafter, an example of room temperature etching and an example of high temperature etching will be described respectively.

The structure of the low temperature etching ferroelectric capacitor structure is as follows: oxygen barrier conductor layer 1: Ir layer, thickness 90 nm, lower electrode layer 2: upper Pt layer / IrO ₂ layer, thickness 100 n
m / 50 nm, ferroelectric layer 3: PZT layer, thickness 220 nm (made by chemical solution deposition, CSD), upper electrode layer 4: upper IrO ₂ layer / lower SRO layer, thickness 7
5 nm / 15 nm was used.

The structure of the hard masks 5 and 6 is as follows. First layer hard mask 5: TiN layer, thickness 150 nm
(Prepared by sputtering), 2nd layer hard mask 6: SiO ₂ layer, thickness 500 nm
(Prepared by CVD of plasma TEOS) was used.

For etching, the stage was cooled to 20 ° C., 1400 W was applied to the RF electrode, and about 4 times was applied between the opposing electrodes.
About 800 W of low frequency of 00 kHz was applied and etching gas pressure was 0.7 Pa.

The etching gas conditions are: Cl ₂ : O ₂ = flow rate 30:20 for the upper electrode layer 4, etch time 40 seconds, Cl ₂ : Ar: O ₂ : CF ₄ for the ferroelectric layer 3. = Flow rate 16:20:20:
8. Etching time 65 seconds For the lower electrode 2 + oxygen barrier conductive layer 1, Cl ₂ : O ₂ = flow rate 30:20 and etching time 80 seconds.

Under the above etching conditions, the second hard mask layer 5 disappeared during the etching. O ₂ is mixed in the etching gas for the ferroelectric layer 3 in order to increase the etching rate ratio of the ferroelectric layer to the hard mask. However, when O ₂ is added, the etching rate of the ferroelectric layer is lowered and the microloading effect is also generated.

The first hard mask layer 5 is formed with ammonia water (2
9%) / hydrogen peroxide solution (31%) = 1: 5 solution at 25 ° C.
Removed in. Then, the step of FIG. 3 (I) was performed to further form a W plug, a wiring layer, a W plug, and the like.

FIG. 5 shows a photograph of a cross section of the prepared sample. The sidewall of the ferroelectric capacitor structure exhibits a taper angle of about 70 degrees with respect to the horizontal plane. High temperature etching
Although high temperature etching increases the etching rate, the etching conditions become severe, so it is desirable to strengthen the hard mask layer and the like. The specific conditions were as follows.

As the ferroelectric capacitor structure, oxygen shielding conductive layer 1: Ir layer, thickness 200 nm Lower electrode layer 2: upper Pt layer / lower IrO ₂ layer, thickness 10
A 0 nm / 50 nm ferroelectric layer 3: PZT layer, thickness 200 nm (created by sputtering), upper electrode layer 4: IrO ₂ layer, thickness 200 nm were used.

As the hard mask structure, the first hard mask layer 5: TiN layer, thickness 200 nm
(Created by sputtering), second hard mask layer 6: SiO ₂ layer, thickness 100 n
m (created by CVD of plasma TEOS) was used.

The etching conditions are a stage temperature of 350 ° C.
And the input power is 1400W / 8 as in room temperature etching.
00 W, and the etching gas pressure was set to 0.7 Pa as in the room temperature etching. The etching gas is Cl ₂ : O ₂ = flow rate 16:20 for the upper electrode layer 4, etch time 20 seconds, Cl ₂ = flow rate 100 for the ferroelectric layer 3, etch time 35 seconds lower electrode 2 + oxygen. For the shielding conductive layer 1, Cl ₂ : O ₂ = flow rate 30: 100 and etching time 60 seconds.

FIG. 6 shows the shape of the ferroelectric capacitor structure immediately after batch etching. The second layer hard mask is
Although the upper surface is deformed into a chevron shape, it covers the entire upper surface of the underlying first hard mask layer. The upper electrode 4, the ferroelectric layer 3, the stock electrode 2, and the oxygen barrier conductive layer 1 are etched at a more nearly constant angle. The side surface of the ferroelectric capacitor structure was at an angle of about 82 to 83 degrees with respect to the horizontal plane. By such high temperature etching, the ferroelectric capacitor structure can be patterned into a shape having side surfaces having an angle close to vertical of 80 degrees or more.

If the first TiN hard mask layer is omitted, peeling occurs at the interface between the hard mask layer and the upper electrode layer during etching. However, by interposing the TiN layer, peeling can be prevented. did it. Similar results can be expected when a TaN layer or a TiAlN layer is used instead of the TiN layer as the first hard mask layer.

When the first hard mask layer is not removed, a TiO ₂ layer, an Al ₂ O ₃ layer or the like may be used as the first hard mask layer or a part thereof. Further, when the first hard mask layer 5 is formed, in order to prevent reduction of the oxide ferroelectric layer, it is preferable to form the first hard mask layer by a method that does not involve hydrogen generation. . For example, the first hard mask layer is formed by sputtering.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, changes, and combinations can be made.

The features of the present invention will be additionally described below. (Supplementary Note 1) (1) (a) A step of laminating an oxygen barrier conductive layer, a lower electrode layer, a ferroelectric layer, and an upper electrode layer on a semiconductor substrate in which a conductive surface for contact is exposed in an insulating surface,
(B) forming a hard mask including a first layer and a second layer on the upper electrode layer, and (c) using the hard mask as an etching mask, plasma etching the upper electrode layer, the ferroelectric layer, A step of forming a capacitor structure by etching the lower electrode layer and the oxygen barrier conductive layer,
A method for manufacturing a semiconductor device, including:

(Supplementary Note 2) (2) The method for producing a semiconductor device according to Supplementary Note 1, further comprising (d) a step of removing at least a part of the remaining hard mask after etching.

(Additional remark 3) The first layer of the hard mask has a function of an adhesive layer, the second layer is an insulating layer, and the step (d) removes the second layer. Of manufacturing a semiconductor device of.

(Supplementary Note 4) The method for producing a semiconductor device according to Supplementary Note 3, wherein the first layer of the hard mask includes a thin film having a hydrogen shielding function. (Supplementary Note 5) The semiconductor device according to Supplementary Note 2, wherein the first layer of the hard mask is a layer having a function of an adhesive layer, the second layer is an insulating layer, and the step (d) removes all the hard mask. Manufacturing method.

(Supplementary Note 6) (3) The method for producing a semiconductor device according to any one of Supplementary Notes 1 to 5, further including (e) a step of forming a hydrogen barrier insulating layer covering the capacitor structure.

(Supplementary Note 7) (4) The supplementary notes 1 to 6, wherein the upper electrode and the lower electrode contain a noble metal element and the ferroelectric layer contains an oxide perovskite type ferroelectric. Manufacturing method of semiconductor device.

(Supplementary Note 8) The method for producing a semiconductor device according to Supplementary Note 7, wherein the upper electrode contains a noble metal oxide. (Additional remark 9) The method for manufacturing a semiconductor device according to additional remark 7, wherein the lower electrode includes a stack of a noble metal oxide electrode and a noble metal electrode.

(Supplementary Note 10) The method for producing a semiconductor device according to Supplementary Note 7, wherein the oxide perovskite type ferroelectric contains any one of PZT, SBT and BLT. (Supplementary Note 11) (5) The hard mask is made of TiN, T
Item 11. In any one of Supplementary Notes 1 to 10, including a lower first layer formed of either aN or TiAlN, and a second layer formed of silicon oxide and disposed on the first layer. A method for manufacturing a semiconductor device as described above.

(Supplementary Note 12) The hard mask is made of Ti.
11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, which is composed of a lower first layer of N and an upper second layer of silicon oxide.

(Supplementary Note 13) The method for producing a semiconductor device according to Supplementary Note 11 or 12, wherein the step (b) forms the first layer by sputtering. (Supplementary Note 14) In the step (b), CV is applied to the second layer.
14. The method for manufacturing a semiconductor device according to any one of appendices 11 to 13, which is formed by any one of D, plasma CVD, and a coating method.

(Supplementary Note 15) Any one of Supplementary Notes 1 to 14 in which the step (c) is performed using inductively coupled plasma.
A method of manufacturing a semiconductor device according to item. (Supplementary Note 16) In the step (c), Cl ₂ , SiCl ₄ , BCl ₃ , CF ₄ , C ₄ F ₈ and HBr are used as etching gas.
16. The method for manufacturing a semiconductor device according to any one of appendices 1 to 15, which is performed using at least one of the above.

(Supplementary Note 17) The method for producing a semiconductor device according to Supplementary Note 16, wherein the step (c) includes a step of adding O ₂ or (O ₂ + N ₂ ) to an etching gas for etching.

(Supplementary Note 18) The oxygen barrier layer is made of Ir.
Note 1 to 1 containing either TiN or TiAlN
8. The method for manufacturing a semiconductor device according to claim 7. (Supplementary note 19) Supplementary note 1 wherein the oxygen barrier layer is an Ir layer
8. The method for manufacturing a semiconductor device according to item 8.

[0053]

As described above, according to the present invention,
The ferroelectric capacitor forming stack can be patterned by continuous dry etching using the same mask.

By making the taper angle of the side wall of the ferroelectric capacitor structure steep, it is easy to improve the integration degree of the FeRAM device.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a schematic cross-sectional view showing the configuration of an inductively coupled plasma etching apparatus.

FIG. 5: FeR prepared according to an example of the present invention
It is an electron micrograph which shows the cross-sectional structure of an AM apparatus.

FIG. 6 is an electron micrograph showing a structure after patterning a ferroelectric capacitor structure according to another example of the present invention.

[Explanation of symbols] 1 Oxygen barrier conductive layer 2 Lower electrode 3 Ferroelectric layer 4 Upper electrode 5 Hard mask (first layer) 6 Hard mask (second layer) 11 Silicon substrate 12 element isolation region 13 Gate insulating film 14 Polycrystalline silicon gate electrode 15 Silicide gate electrode 16 Source / drain region 18 Interlayer insulation film 19 W plug

Claims (5)

[Claims] 1. A step of laminating an oxygen barrier conductive layer, a lower electrode layer, a ferroelectric layer, and an upper electrode layer on a semiconductor substrate in which a conductive surface for contact is exposed in an insulating surface, and (b) the above. Forming a hard mask including a first layer and a second layer on the upper electrode layer, and (c) using the hard mask as an etching mask, plasma etching the upper electrode layer, the ferroelectric layer,
And a step of etching the lower electrode layer and the oxygen barrier conductive layer to form a capacitor structure. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (d) removing at least a part of the remaining hard mask after etching. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of (e) forming a hydrogen barrier insulating layer covering the capacitor structure. 4. The manufacturing of a semiconductor device according to claim 1, wherein the upper electrode and the lower electrode contain a noble metal element, and the ferroelectric layer contains an oxide perovskite type ferroelectric. Method. 5. The hard mask comprises TiN, TaN,
5. A lower first layer formed of any of TiAlN and a second layer formed of silicon oxide and arranged on the first layer. 5. Of manufacturing a semiconductor device of.