JP2009295707A - Probe inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for preventing formation of a probe mark on a surface of a test pad in performing probe inspection using a probe card having a probe. <P>SOLUTION: An opening part on the pad 32 includes an opening part 33 opened on a surface of a chip 31, and an opening part 34 opened on a bottom part of the opening part 33 and reaching the pad 32. The opening part 33 includes a plane size larger than the opening part 34. With a predetermined amount of conductive fluid 36 filled only in the opening parts 33, 34, a chip end of a probe needle 15 is brought into in contact with the conductive fluid 36 and electric conduction between the pad 32 and the probe needle 15 is made without contacting the probe needle 15 with the pad 32 to perform the probe inspection. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a probe inspection technique, and more particularly to a technique effective when applied to a process of inspecting an integrated circuit formed on a semiconductor wafer by pressing a probe of a probe card against an electrode pad.

  There is a probe inspection as an inspection technique for a semiconductor integrated circuit device. This probe inspection includes a function test for confirming whether or not the device operates according to a predetermined function, a test for determining a non-defective product / defective product by performing a DC operation characteristic and an AC operation characteristic test, and the like. In probe inspection, probe inspection is performed in the wafer state in response to demands for wafer shipment (quality differentiation), KGD (Known Good Die) support (MCP (Multi-Chip Package) yield improvement), and total cost reduction. Technology to do is used.

“Semiconductor Manufacturing Equipment Glossary” edited by Japan Semiconductor Manufacturing Equipment Association, 6th edition, Nikkan Kogyo Shimbun, September 27, 2006, p. 322-370 (Non-Patent Document 1) discloses an outline of the probe inspection process and various members used in the probe inspection process.
“Semiconductor Manufacturing Equipment Glossary” edited by Japan Semiconductor Manufacturing Equipment Association, 6th edition, Nikkan Kogyo Shimbun, September 27, 2006, p. 322-370

  In recent years, semiconductor integrated circuit devices have become more multifunctional, and it has been promoted to create a plurality of circuits on one semiconductor chip (hereinafter simply referred to as a chip). Further, in order to reduce the manufacturing cost of the semiconductor integrated circuit device, the semiconductor element and the wiring are miniaturized to reduce the area of the semiconductor chip (hereinafter simply referred to as a chip), and the semiconductor wafer (hereinafter simply referred to as the wafer). Increasing the number of chips acquired per sheet is underway. Therefore, not only the number of test pads (bonding pads) is increased, but also the arrangement of test pads is narrowed, and the area per test pad is also reduced. Under such circumstances, the present inventors have found that the following problems exist in performing probe inspection using a probe card having various probes such as a cantilever shape.

  That is, when the probe comes into contact with the test pad, a trace of contact with the probe, so-called probe trace, remains on the surface of the test pad. Due to the presence of this probe mark, when a bonding wire for chip mounting is connected to the test pad later, a gap is generated between the bonding wire and the test pad, resulting in a poor connection of the bonding wire. There is concern.

  In addition, the cantilever-shaped probe slides a predetermined amount on the surface of the test pad in contact with the test pad (hereinafter referred to as “overdrive”) so that the surface of the test pad is naturally oxidized. It is required that the film be broken and securely connected to the test pad. However, because the test pad itself has been reduced in area, there is a concern that the tip of the overdriven probe will be caught by the surface protective film around the test pad, causing damage or peeling of the surface protective film. Is done. When the film thickness of the pad itself is thin, there is a concern that the probe may break through the pad due to overdrive.

  Further, the needle pressure due to the contact of the probe with the test pad acts as a load not only on the test pad but also on the probe card provided with the probe. As the number of test pads increases, the number of probes also increases (multiple pins), but the sum of the needle pressures from the individual probes increases as the number of pins increases. Since the sum of the needle pressures from the individual probes acts as a load on the probe card, the load acting on the probe card increases due to the increase in the sum of the needle pressures, causing the probe card to warp. There are concerns about defects. When the probe card is warped, there is a concern that it is difficult to align the tip of the probe and the test pad in the subsequent probe inspection process. In addition, since the same needle pressure also acts on the wafer stage on which the wafer is placed, the wafer stage is raised against the wafer stage with rigidity capable of withstanding the needle pressure and against the needle pressure. Therefore, a sufficient torque is required.

  An object of the present invention is to provide a technique capable of preventing probe marks from remaining on the surface of a test pad when a probe inspection is performed using a probe card having a probe.

  Another object of the present invention is to prevent a problem that a test pad and a surface protective film around the test pad are damaged or peeled when a probe inspection is performed using a probe card having a probe. It is to provide technology that can.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The probe inspection method according to the present invention includes:
(A) A plurality of chip areas are partitioned, and an integrated circuit is formed in each of the plurality of chip areas, and a plurality of electrodes electrically connected to the integrated circuit on a main surface and a protection covering the plurality of electrodes A step of preparing a semiconductor wafer formed with an insulating film and having a plurality of first openings reaching each of the plurality of electrodes in the protective insulating film;
(B) preparing a probe card having a plurality of contact terminals to be electrically connected to the plurality of electrodes, and a circuit to be electrically connected to the plurality of contact terminals and a tester;
(C) filling each of the plurality of first openings with a conductive fluid;
(D) Under the situation where the conductive fluid is injected into each of the plurality of first openings, the plurality of contact terminals are inserted into the plurality of first openings, and the conductive fluid is inserted. And electrically connecting each of the plurality of contact terminals with the corresponding plurality of electrodes,
(E) performing an electrical inspection of the integrated circuit in a state where each of the plurality of contact terminals is electrically connected to the corresponding plurality of electrodes;
including.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) When performing probe inspection using a probe card having a probe, it is possible to prevent the probe and the test pad from coming into direct contact with each other, thereby preventing probe marks from remaining on the surface of the test pad. be able to.

  (2) When performing probe inspection using a probe card having a probe, it is possible to prevent the probe and the test pad from coming into direct contact with each other, so that the surface protective film around the test pad and the test pad may be damaged. It is possible to prevent the problem of peeling off.

  (3) When performing probe inspection using a probe card having a probe, it is possible to prevent direct contact between the probe and the test pad, so the sum of the needle pressures from the individual probes becomes a load. It can prevent acting on the probe card. Therefore, it is possible to prevent the probe card from being warped.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  Probe needles, probe needles or simply needles have a needle-shaped contact terminal with a narrowed tip, a pyramid-shaped contact terminal, bump electrodes with other shapes, etc. Shall be included.

  The probe inspection is an electrical test performed on a wafer for which a wafer process has been completed, using a prober, and a semiconductor integrated circuit in which the tip of the probe needle is applied to an electrode formed on the main surface of the chip region. In other words, a non-defective product / defective product is discriminated by performing a function test for confirming whether or not the device operates in accordance with a predetermined function and a DC operation characteristic and an AC operation characteristic test. This is distinguished from a screening test (final test) that is performed after dividing into chips (or after packaging is completed).

  A tester (Test System) is for electrically inspecting a semiconductor integrated circuit and generates a signal such as a predetermined voltage and a reference timing. In addition, it is equipped with a detection circuit that detects that the probe needle is in contact with the electrode formed on the main surface of the tip area by resistance measurement. The detection circuit incorporates a diode to prevent reverse current generation. is doing.

  A test head is a probe that is electrically connected to a tester, receives a voltage and a signal transmitted from the tester, generates a signal such as a voltage and detailed timing to a semiconductor integrated circuit, and is a probe described later via a pogo pin or the like. The one that sends a signal to the card.

  The OSC (Oscillator System Clock) circuit refers to a system clock generation circuit that generates a reference clock for operating a CPU (Central Processing Unit) and peripheral functions. When the system clock is input to the device, the frequency is divided by a counter of several tens of bits in the device, and the divided clock becomes an internal clock of the built-in peripheral module.

  The X'tal circuit is mainly a clock generation circuit for a clock timer. When a clock timer clock (for example, 32.768 kHz and 38.4 kHz) is input to the device, the clock is divided by a counter of several bits in the device, and the divided clock is used for the time base operation of the timer clock. This is the clock to use.

  The bypass circuit refers to a circuit that removes power supply noise, and removes high-frequency noise and low-frequency noise using an electrolytic capacitor and a ceramic capacitor.

  An AD / DA circuit refers to a circuit that converts an analog signal into a digital signal and converts the digital signal into an analog signal.

  The contact ring refers to a device that is electrically connected to a probe card, which will be described later, via a pogo pin or the like and sends a signal sent from the test head to the probe card.

  A probe card is a structure that is electrically connected to a contact ring via a pogo pin or the like and has a probe needle and a multilayer wiring board that come into contact with a wafer to be inspected, and a signal sent from the contact ring. What is sent to the target wafer. In some cases, an OSC circuit, an X′tal circuit, a bypass circuit, an AD / DA circuit, and the like are provided to generate a signal that cannot be generated by the tester and send the signal to a wafer to be inspected.

  The prober refers to an inspection apparatus having a sample support system including a contact stage, a probe card, and a wafer stage on which a wafer to be inspected is placed.

  Pogo pin (POGO pin) is a contact that makes electrical connection to the electrode by pressing the contact pin (plunger (contact needle)) against the electrode (terminal) by the elastic force of the spring (coil spring). A needle is called, and a spring arranged in a metal tube transmits elastic force to a contact pin via a metal ball.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes sub-elements, additions Things, additional elements, etc. are not excluded. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  In addition, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the present embodiment, even a plan view may be partially hatched to make the drawings easy to see.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is an explanatory diagram showing the configuration of the tester 1 and jig used in the probe inspection process in the present embodiment and the flow of test signals. As shown in FIG. 1, the jig is formed of a test head 2, a contact ring 4, a probe card 5, a wafer stage 6 and the like, and the probe card 5 and the wafer stage 6 are accommodated in a prober 7. . The contact ring 4 is included in the test head 2.

  The test head 2 provided with various circuits therein is electrically connected to the tester 1.

  The contact ring 4 is provided with a plurality of pogo pins 11 that are electrically connected to a circuit provided therein. The circuit in the contact ring 4 is electrically connected to the circuit in the test head 2 and the tester 1. The tip of the pogo pin 11 is directed toward the probe card 5 in the prober 7. Further, the tips of the plurality of pogo pins 11 are connected to the connect pads provided on the probe card 5, whereby the contact ring 4 and the probe card 5 can be electrically connected.

  The probe card 5 is provided with a plurality of probe needles (contact terminals) 15 so as to face the wafer 14 to be inspected placed on the wafer stage 6. The plurality of probe needles 15 are electrically connected to the contact ring 4 through a predetermined circuit included in the probe card 5. The main surface of the wafer 14 is partitioned into a plurality of chip regions, and a semiconductor integrated circuit and a plurality of pads electrically connected to the semiconductor integrated circuit are formed in each chip region. The wafer stage 6 sucks and fixes the wafer 14 and performs horizontal and height operations by the X stage XSG, Y stage YSG, and Z stage ZSG provided on the stage base STB. The semiconductor stage formed in the tester 1, test head 2, contact ring 4, probe card 5, and wafer 14 by the wafer stage 6 being raised by the operation of the Z stage ZSG and the plurality of probe needles 15 coming into contact with these pads. The probe test can be performed by electrically connecting the integrated circuit and sending a test signal to the semiconductor integrated circuit.

  FIG. 2 is a plan view of the probe card 5, and FIG. 3 shows a cross section taken along the line AA in FIG. FIG. 4 is a plan view of the wiring board 18 that forms the probe card 5.

  As shown in FIGS. 2 to 4, the main surface of the wiring board 18 is electrically connected to, for example, the outer peripheral pad region 20 in which the connect pads 17 are arranged from the outer periphery and the probe needle 15 attached to the rear surface of the wiring board 18. An inner peripheral pad region 22 where the pads 21 to be connected are arranged and an electronic component mounting region 23 where electronic components are mounted are provided. Connect pads 17 and pads 21 are electrically connected to each other through wiring provided inside the wiring board 18.

  In the present embodiment, the probe card 5 is provided with inspection circuits such as an OSC circuit, an X′tal circuit, a bypass circuit, and an AD / DA circuit. These inspection circuits are electrically connected to electronic components such as relays 26 and 27, a capacitor 28, a crystal oscillator 29, and an IC 30 attached to the upper surface (main surface) of the wiring board 18, and these electronic components. The wiring board 18 is formed from wiring or the like provided inside.

  The relays 26 and 27 are arranged in a line along the outer periphery of the electronic component mounting area 23. Further, by selecting relays 26 and 27 that satisfy the characteristics required for forming the inspection circuit and having the smallest possible external dimensions, the relays 26 and 27 can be prevented from being crowded. Therefore, the heat generated from the relays 26 and 27 can be easily released. That is, it is possible to prevent malfunction of the relays 26 and 27 due to temperature rise. Further, since the heat generated from the relays 26 and 27 can be easily released, the thermal load applied to the electronic components including the relays 26 and 27 can be reduced, so that the lifetime of the electronic components can be extended.

  When the inspection circuit is provided on a member above the probe card 5, the following problems occur with the miniaturization of the semiconductor integrated circuit formed on the wafer 14 and the speeding up of the circuit operation. Concerned. That is, when a signal sent from, for example, the test head 2 passes near a clock generator such as the OSC circuit and the X′tal circuit, noise due to crosstalk or the like is generated, and a normal clock (signal waveform) is generated. ) Cannot be generated. A semiconductor integrated circuit to be inspected that has received a signal mixed with noise is liable to malfunction, and there is a concern that the probe cannot be accurately inspected. For this reason, it is preferable to provide the above-described inspection circuit at a position as close as possible to the wafer 14 to be inspected, that is, on the probe card 5.

  FIG. 5 is a plan view of the wafer 14 in which a plurality of chips 31 are partitioned. The probe inspection according to the present embodiment is performed on the wafer 14 on which the plurality of chips 31 are partitioned. FIG. 6 shows the plane of the chip 31 and an enlarged view of a part thereof. The chip 31 is made of, for example, a single crystal silicon substrate. In addition, a large number of pads (electrodes) 32 that are electrically connected to a semiconductor integrated circuit formed in the chip 31 are arranged on the periphery of the main surface of the chip 31.

  The chip 31 is formed by forming various semiconductor integrated circuits and input / output terminals (pads 32) using a semiconductor manufacturing technique in a large number of chip regions defined on the main surface of the wafer 14, and then dicing the wafer 14. Thus, it can be manufactured by dividing the chip area into individual pieces. In the present embodiment, the probe inspection is performed on each chip area before dicing the wafer 14. In the following description of the probe inspection (the step in which the pad 32 and the probe needle 15 come into contact), unless otherwise specified, the chip 31 indicates each chip region before the wafer 14 is diced.

  7 and 8 show a cross section of the main part in the vicinity of the pad 32 in the chip 31. FIG.

  The opening (first opening) on the pad 32 opens at the opening (second opening) 33 opening on the surface of the chip 31 and a part of the bottom of the opening 33 and reaches the pad 32. An opening (third opening) 34 is formed, and the opening 33 has a larger planar size than the opening 34. Since the pads 32 are arranged along the four sides of the chip 31, the pads 32 are not arranged in a relatively planar direction inside the chip 31, and an opening 33 having a large planar size is formed. be able to.

  Here, FIGS. 9 to 11 show various plane patterns of the openings 33 and 34. The openings 33 and 34 having such a structure are newly formed after the pattern of the openings 33 is formed by etching the surface protection film 35 on the pad 32 using, for example, a photoresist film patterned by photolithography as a mask. The pattern of the opening 34 can be realized by etching the surface protective film (protective insulating film) 35 below the opening 33 using a photoresist film patterned by photolithography as a mask. The surface protective film 35 is formed from a silicon oxide film, a silicon nitride film, or a laminated film thereof.

  In the present embodiment, the probe inspection is performed in a state where a predetermined amount of the conductive fluid 36 is filled only in the openings 33 and 34 as described above. The conductive fluid 36 is preferably one that can be removed by cleaning the wafer 14 after probe inspection, and examples thereof include mercury or conductive ink.

  In the probe inspection according to the present embodiment, the pad 32, the probe needle 15 and the probe needle 15 are contacted with the tip of the probe needle 15 in contact with the conductive fluid 36 in a state where the openings 33 and 34 are filled with the conductive fluid 36. It is implemented by taking electrical continuity. As described above, the opening 33 is formed in a larger plane size than the opening 34. Depending on the plane pattern of the opening 33, the pad 33 is filled with the conductive fluid 36 depending on the opening 33, 34. Even when the size of the pad 32 is reduced, the planar size of the pad 32 can be increased in a pseudo manner. Thereby, even when the pad 32 is downsized, the probe needle 15 and the pad 32 can be easily brought into electrical contact.

  As the planar pattern of the opening 33, a pattern (see FIG. 9) in which the planar pattern of the opening 34 is directly expanded in the plane inner direction of the chip 31, and the planar pattern of the opening 34 is expanded in the plane inner direction of the chip 31. Furthermore, a pattern (see FIG. 10) enlarged in the arrangement direction of the pads 32 can be exemplified. Further, the planar pattern of the specific opening 33 may be extended to a specific position on the main surface of the chip 31 (see FIG. 11). The reason will be described later.

  As described above, when the pad 32 is reduced in size especially in the plane size, as shown in FIG. 10, the plane pattern of the opening 33 is expanded also in the arrangement direction of the pad 32, thereby The plane size can be increased as much as possible in a pseudo manner. However, when the spacing between adjacent pads 32 is close, it may be difficult to expand the planar pattern of the opening 33 in the direction in which the pads 32 are arranged. In such a case, as shown in FIG. 11, the planar pattern of the opening 33 can be routed to a desired position on the main surface of the chip 31, so that the desired position on the main surface of the chip 31 can be obtained. Thus, the opening 33 can be provided in a desired size. In addition, since it is possible to provide the opening 33 with a desired size at a desired position on the main surface of the chip 31, even if the number of pins of the pad 32 is increased, the probe card 5 has a margin. It is possible to hold the probe needle 15 by holding the needle.

  In the present embodiment, when the tip of the probe needle 15 comes into contact with the conductive fluid 36, the semiconductor integrated circuit in the chip 31 electrically connected to the pad 32 and the probe needle 15 are electrically connected, A significant change appears in the resistance value of the probe needle 15. In the tester 1, a detection circuit corresponding to each of the probe needles 15 is individually provided. By monitoring a change in the resistance value of the probe needle 15 by the detection circuit, the tip of the probe needle 15 is electrically connected. The contact with the sexual fluid 36 can be detected. That is, when the tester 1 detects contact between the tips of all the probe needles 15 and the conductive fluid 36, the tip of the probe needles 15 is moved to the pads 32 by stopping the ascent of the wafer stage 6 on which the wafer 14 is mounted. Alternatively, contact with the surface protective film 35 under the opening 33 can be prevented. As a result, it is possible to prevent the probe marks due to the probe needles 15 from remaining on the surface of the pad 32 after the probe inspection. That is, it is possible to prevent the bonding wire for mounting the chip 31 connected to the pad 32 from causing a connection failure in a later process.

  In particular, when a plurality of inspections are performed by bringing the probe needles 15 into electrical contact with a single pad 32 for a plurality of purposes, if the probe needles 15 are in direct contact with the pad 32, the pads 32. However, according to the present embodiment in which the probe needle 15 and the pad 32 are not in direct contact, such a problem can be prevented.

  Further, according to the present embodiment, probe inspection can be performed without bringing the tip of the probe needle 15 into contact with the pad 32, so that overdrive of the probe needle 15 becomes unnecessary. As a result, the pad 32 can be prevented from being damaged due to the contact of the probe needle 15. Furthermore, since the tip of the probe needle 15 contacts the conductive fluid 36 through the opening 33 having a large planar size, the tip of the probe needle 15 can be prevented from being caught by the side wall of the opening 33. That is, the surface protective film 35 can be prevented from being peeled off due to the tip of the probe needle 15 being caught on the side wall of the opening 33.

  In addition, according to the present embodiment, the tip of the probe needle 15 and the pad 32 are not in direct contact with each other, so that it is possible to prevent the shavings of the pad 32 due to overdrive from adhering to the tip of the probe needle 15. . Such shavings of the pad 32 cause a conduction failure at the tip of the probe needle 15 and therefore must be periodically removed by cleaning. According to the present embodiment, the cleaning itself is performed. Can be omitted.

  By the way, at the time of probe inspection according to the present embodiment, the tip of the probe needle 15 is not directly in contact with the pad 32 but is in electrical contact with the pad 32 by being in contact with the conductive fluid 36. The contact position between the front end of the conductive fluid 36 and the conductive fluid 36 may be anywhere in the opening 33, but preferably the position where the opening 34 does not open in the lower part of the opening 33. This is to prevent the tip of the probe needle 15 from coming into contact with the pad 32 when the probe card 5 and the wafer 14 are brought close to each other. Further, the probe needle provided on the probe card 5 may be a pogo pin-like probe needle (contact terminal) 15A as shown in FIG. 12 instead of the cantilever-like probe needle 15 as shown in FIGS. . In the pogo pin-like probe needle 15A shown in FIG. 12, a spring (elastic body) SPR disposed in a metal tube (holding member) TUB transmits an elastic force to a contact pin (contact needle) PLG via a metal ball MBL. Even if the contact pin PLG comes into contact with the pad 32, the spring SPR absorbs the impact at the time of contact, and it is possible to prevent damage to the pad 32.

  Further, at the time of the probe inspection of the present embodiment, the tip of the probe needle 15 and the pad 32 are not in direct contact with each other, so that it is possible to prevent the wiring and the semiconductor element provided below the pad 32 from being damaged. That is, as shown in FIGS. 7 and 8, on the main surface (element formation surface) of the semiconductor substrate 41 (wafer 14) on which the chip 31 is formed, a p-type semiconductor region 42, n serving as a semiconductor element, is formed below the pad 32. The type semiconductor region 43 and the wirings 44 and 45 can be formed.

  By the way, when the pad 32 is increased, the probe needle 15 is also multi-pinned. When the probe needle 15 directly contacts the pad 32, the needle pressure by the probe needle 15 acts as a load not only on the pad 32 but also on the probe card 5 on which the probe needle 15 is provided. Therefore, the sum of the needle pressures from the individual probe needles 15 increases as the number of pins increases. In such a case, since the sum of the needle pressures from the individual probe needles 15 acts as a load on the probe card 5, the load acting on the probe card 5 increases as the sum of the needle pressures increases. However, there is a concern that the probe card 5 may be warped. If the probe card 5 is warped, there is a concern that it is difficult to align the tip of the probe needle 15 and the pad 32 in the subsequent probe inspection process. In addition, since the same stylus pressure also acts on the wafer stage 6 on which the wafer 14 is placed, the wafer stage 6 is required to have rigidity capable of withstanding the stylus pressure, and the wafer stage 6 is raised. For the Z stage ZSG, sufficient torque is required to raise the wafer stage 6 against the needle pressure.

  On the other hand, according to the present embodiment, as described above, the tip of the probe needle 15 is not in direct contact with the pad 32 but in contact with the conductive fluid 36. Does not occur or is close to it. Therefore, even when the number of pins of the probe needle 15 is increased, a load from the probe needle 15 does not act on the probe card 5, so that the warp of the probe card 5 can be prevented. In addition, since the wafer stage 6 can be made rigid enough to withstand the needle pressure from the probe needle 15, the structure design of the wafer stage 6 can be facilitated. Furthermore, since the Z stage ZSG can also eliminate the need for torque for raising the wafer stage 6 against the needle pressure, the Z stage ZSG structure can be easily designed.

  If the probe needle 15 and the pad 32 cannot be electrically connected even when the probe needle 15 comes into contact with the conductive fluid 36, it is considered that a natural oxide film is formed on the surface of the pad 32. It is done. In such a case, before performing the probe inspection, a process of removing a natural oxide film formed on the surface of the pad 32 by processing the wafer 14 using a solvent that dissolves aluminum oxide in advance is added. May be.

(Embodiment 2)
In the first embodiment, in the jig used in the probe inspection process shown in FIG. 1, the contact ring 4 and the probe card 5 are connected via a plurality of pogo pins 11.

  By the way, the number of pogo pins 11 corresponds to the number of probe needles 15 provided on the probe card 5, for example. As the number of pogo pins 11 increases as the number of probe needles 15 increases, the load acting on the probe card 5 from the pogo pins 11 increases, and the probe card 5 is warped or damaged by the load from the pogo pins 11. There is concern about malfunctions that may occur.

  Therefore, in the second embodiment, the probe card 5 receives a plurality of pogo pins 11 with the same conductive fluid as the conductive fluid 36 described in the first embodiment (see FIGS. 7 and 8). To do.

  That is, as shown in FIGS. 13 and 14, a plurality of cup-shaped receiving portions 5A corresponding to each of the plurality of pogo pins 11 are provided on the upper surface of the probe card 5, and a predetermined amount of conductive fluid 5B is provided in the receiving portion 5A. Fill. When the pogo pin 11 is electrically connected to the probe card 5, it contacts only the conductive fluid 5B and does not contact the cup 5A. Thereby, the pogo pin 11 (contact ring 4) and the probe card 5 can be electrically connected, but the load from the pogo pin 11 can be prevented from being applied to the probe card 5. As a result, it is possible to prevent a problem that the probe card 5 is warped or damaged by the load from the pogo pin 11.

  The probe inspection method of the present invention can be applied to a probe inspection process performed by bringing a probe needle into contact with a pad on the chip surface.

It is explanatory drawing which shows the structure of the tester and jig | tool used at the probe test | inspection process which is one embodiment of this invention. It is a top view of the probe card shown in FIG. It is sectional drawing along the AA line in FIG. It is a top view of the wiring board which forms the probe card shown in FIG. It is a top view of the semiconductor wafer in which the semiconductor chip area | region of the object which performs a probe test | inspection using the probe card which is one embodiment of this invention was formed. It is a top view of the semiconductor chip of the object which carries out a probe test using the probe card which is one embodiment of the present invention. It is principal part sectional drawing of the semiconductor chip of the object which carries out a probe test | inspection using the probe card which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor chip of the object which carries out a probe test | inspection using the probe card which is one embodiment of this invention. It is a principal part top view of the semiconductor chip of the object which performs a probe test | inspection using the probe card which is one embodiment of this invention. It is a principal part top view of the semiconductor chip of the object which carries out a probe test | inspection using the probe card which is one embodiment of this invention. It is a principal part top view of the semiconductor chip of the object which performs a probe test | inspection using the probe card which is one embodiment of this invention. It is sectional drawing which shows an example of the probe needle | hook of the pogo pin shape provided in the probe card which is one embodiment of this invention. It is principal part sectional drawing explaining the connection state of the contact ring and probe card in the jig | tool used at the probe test | inspection process which is one embodiment of this invention. It is principal part sectional drawing which shows the connection part of the contact ring and probe card in the jig | tool used at the probe test | inspection process which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Tester 2 Test head 4 Contact ring 5 Probe card 5A Receiving part 5B Conductive fluid 6 Wafer stage 7 Prober 11 Pogo pin 14 Wafer 15, 15A Probe needle (contact terminal)
18 Wiring board 20 Peripheral pad area 21 Pad 22 Inner peripheral pad area 23 Electronic component mounting area 26, 27 Relay 28 Capacitor 29 Crystal oscillator 30 IC
31 chip 32 pad (electrode)
33 opening (second opening)
34 opening (third opening)
35 Surface protective film (protective insulating film)
36 conductive fluid 41 semiconductor substrate 42 p-type semiconductor region 43 n-type semiconductor region 44, 45 wiring MBL metal ball PLG contact pin (contact needle)
SPR spring (elastic body)
STB stage base TUB tube (holding member)
XSG X stage YSG Y stage ZSG Z stage

Claims (7)

(A) A plurality of chip areas are partitioned, and an integrated circuit is formed in each of the plurality of chip areas, and a plurality of electrodes electrically connected to the integrated circuit on a main surface and a protection covering the plurality of electrodes A step of preparing a semiconductor wafer formed with an insulating film and having a plurality of first openings reaching each of the plurality of electrodes in the protective insulating film;
(B) preparing a probe card having a plurality of contact terminals to be electrically connected to the plurality of electrodes, and a circuit to be electrically connected to the plurality of contact terminals and the tester;
(C) filling each of the plurality of first openings with a conductive fluid;
(D) In a situation where each of the plurality of first openings is filled with the conductive fluid, each of the plurality of contact terminals is inserted into the plurality of first openings and the conductive fluid is inserted. And electrically connecting each of the plurality of contact terminals with the corresponding plurality of electrodes,
(E) performing an electrical inspection of the integrated circuit in a state where each of the plurality of contact terminals is electrically connected to the corresponding plurality of electrodes;
A probe inspection method comprising: The probe inspection method according to claim 1,
Each of the plurality of first openings is formed of a second opening and a third opening that reaches the electrode from a part of the bottom of the second opening. Probe inspection method. The probe inspection method according to claim 1 or 2,
A probe inspection method, wherein wirings or semiconductor elements forming the integrated circuit are formed below the plurality of electrodes. In the probe inspection method according to any one of claims 1 to 3,
The tester has a plurality of detection circuits respectively corresponding to the plurality of contact terminals,
The step (d) and the step (e) are performed under the condition where the semiconductor wafer is placed and sucked on a wafer stage,
The step (d) is performed by raising the wafer stage in a state where the semiconductor wafer is adsorbed to the wafer stage, and the contact terminals, the conductive fluid, and the corresponding detection circuits respectively correspond to the plurality of detection circuits. A probe inspection method, wherein the rising of the wafer stage is stopped when it is detected that the contact is made. In the probe inspection method according to any one of claims 1 to 4,
The probe inspection method, wherein the step (d) and the step (e) are performed a plurality of times for one chip region. In the probe inspection method according to any one of claims 1 to 5,
The probe inspection method, wherein the conductive fluid is mercury or conductive ink. In the probe inspection method according to any one of claims 1 to 6,
Each of the contact terminals includes a contact needle that contacts the conductive fluid in the step (d), an elastic body that supplies elasticity to the contact needle, and a holding member that holds the contact needle and the elastic body. A probe inspection method characterized by being formed.

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