JP2009273079A - Transmission apparatus, transmission method, receiving apparatus, receiving method, program, and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To wirelessly communicate a digital signal while having a high error correction capability with a relatively simple circuit configuration. <P>SOLUTION: A shift register 103 converts RF digital signals serially inputted from an antenna into n-bit parallel carrier patterns. An LUT memory 104 refers to an LUT held therein to convert n-bit carrier patterns inputted from the shift register 103 into 1-bit BB signals and outputs them. An LUT 104a is generated by learning processing on the basis of regularity in wireless communication characteristics of a housing 51. The present invention may be applicable to wireless communication in the case where wireless communication characteristics inside the housing or the like are regular. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission device, a transmission method, a reception device, a reception method, a program, and a communication system, and in particular, wireless communication in an environment where continuity is recognized in wireless communication characteristics, for example, inside a housing of an electronic device. The present invention relates to a transmission device, a transmission method, a reception device, a reception method, a program, and a communication system that are suitable for use in the case of performing communication.

  2. Description of the Related Art Conventionally, electronic devices typified by personal computers and various AV devices communicate various signals between their constituent parts (for example, LSI (Large Scale Integration)) via wires. However, in recent years, it is sometimes difficult for an electronic device to wire a wire for communication due to narrowing of a casing, multilayering of substrates, various types of components, diversification, and the like.

  For these reasons, it has been proposed that various types of signals be communicated wirelessly between constituent parts in a casing that constitutes an electronic device without using a wired connection.

  However, when wireless communication is performed in the housing, the effects of white noise (noise caused by heat) and colored noise (noise generated from electronic parts) in the housing, and radio signals such as wall surfaces and substrates in the housing are reflected. Therefore, it is necessary to improve the deterioration of communication quality due to multipath caused by diffraction.

  As a method for improving the degradation of communication quality caused by multipath, for example, a method using OFDM (Orthogonal Frequency Multiplexing) for modulation / demodulation (see, for example, Patent Document 1), a method using SS (Spread Spectrum) and rake reception Can be considered. Further, as a method for preventing the occurrence of multipath in the housing, a method of attaching a radio wave absorber in the housing (for example, see Patent Document 2) can be considered.

Japanese Patent No. 1289356 (Japanese Patent Publication No. 60-13344) JP 2004-220264 A

  Here, a conventional wireless transmission device and wireless reception device will be considered.

  FIG. 1 shows an example of a configuration of a conventional wireless transmission apparatus. The wireless transmission device 10 includes an encoder 11, a local oscillator 12, a mixer 13, a post amplifier 14, and an antenna 15.

  In the wireless transmission device 10, a baseband signal (hereinafter referred to as a BB signal) indicating information to be transmitted input from the previous stage is encoded by the encoder 11 and supplied to the mixer 13.

  For encoding by the encoder 11, for example, OFDM (Orthogonal Frequency Multiplexing) encoding or the like is used. In addition to being able to implement digital operations by sampling in the time direction and n-bit quantization in the level direction, OFDM coding can perform complex quantized analog operations while suppressing noise in the encoded results. This is known as an efficient encoding method that can be used (see, for example, Patent Document 1).

  The mixer 13 is supplied with a very stable carrier wave generated by the local oscillator 12, and the carrier wave is modulated by the encoded signal by the mixer 13, and a nonlinear RF signal obtained as a result of this modulation is converted into a post-amplifier. 14 is amplified and transmitted by radio from the antenna 15.

  By the way, although the circuit configuration of the wireless transmission device 10 in FIG. 1 is basically intended for analog wireless communication, a digital BB signal can also be transmitted. However, when the BB signal indicating the information to be transmitted is a digital signal and the signal rate is high-speed digital wireless communication, the circuit configuration of the wireless transmission device 10 has high functional redundancy and performs continuous operation. Since there are many parts, it is difficult to reduce power consumption.

  FIG. 2 shows an example of the configuration of a conventional radio receiving apparatus for receiving a radio signal transmitted from the radio transmitting apparatus 10. The radio receiving apparatus 20 includes an antenna 21, a low noise amplifier 22, a local oscillator 23, a mixer 24, a low-pass filter 25, and a decoder 26.

  In the wireless reception device 20, the RF signal received by the antenna 21 is amplified by the low noise amplifier 22 and supplied to the mixer 24. Further, the mixer 24 is supplied with a high frequency signal (same as the carrier wave output from the local oscillator 12 of the wireless transmission device 10) from the local oscillator 23. The RF signal from the low noise amplifier 22 is demodulated by the mixer 24 based on the high frequency signal from the local oscillator 23, and further supplied to the demodulator 26 via the low-pass filter 25 to be decoded into the BB signal.

  Since the mixer 24 performs a non-linear operation, the local oscillator 23 that supplies a high-frequency signal to the mixer 24 is required to have high stability like the local oscillator 12 of the wireless transmission device 10.

  By the way, the circuit configuration of the wireless receiving device 20 is basically for analog wireless communication as in the case of the wireless transmitting device 10 described above. However, even when a digital BB signal is transmitted, Can be received. However, when the BB signal indicating transmitted information is a digital signal and the signal rate is high-speed digital wireless communication, the circuit configuration of the wireless reception device 20 has high functional redundancy and continuous operation. Since there are many parts, it is difficult to reduce power consumption.

  Next, for example, referring to FIG. 3 for conventional error correction in consideration of the inter-code distance applied to encoding in the encoder 11 of the wireless transmission device 10 and decoding in the decoder 26 of the wireless reception device 20 To explain.

  For example, when communicating a 3-bit encoded signal, there are eight patterns (000, 001,..., 111) of patterns (hereinafter referred to as 3-bit codes). Among these eight 3-bit codes, the patterns with the longest intercode distance are, for example, (111) and (000), (101) and (010), and the intercode distance is 3.

  Here, if the 3-bit code to be transmitted is limited to two (111) and (000), an error has occurred if the received 3-bit code is not (111) or (000). . In this case, the received 3-bit code is corrected so that the inter-code distance between the received 3-bit code and (111) or (000) is shorter.

  For example, if the received 3-bit code is (100), an error has occurred. In this case, the intercode distance between the received (100) and (111) is 2, and the intercode distance between the received (100) and (000) is 1. Therefore, the intercode distance is corrected to the shorter (000). Is done.

  For example, if the received 3-bit code is (101), an error has occurred. In this case, the inter-code distance between the received (101) and (111) is 1, and the inter-code distance between the received (101) and (000) is 2. Therefore, the inter-code distance is corrected to the shorter (111). Is done.

  According to the error correction of the above-described example (an example in which an inter-code distance of 3 among 8 types of 3-bit codes is transmitted), only one bit of the transmitted 3-bit codes has an error. If it occurs, it will be corrected correctly. However, if an error occurs in two or more bits of the transmitted 3-bit code, it cannot be corrected correctly.

  That is, for example, when a 3-bit code (111) is transmitted, an error occurs in 2 bits of the code, and a 3-bit code (100) is received, the received 3-bit code (100) and (111) ) Is 2 and the distance between the received 3-bit codes (100) and (000) is 1, so in this case, the distance between codes is corrected to (000), which is the shorter distance. It will end up.

  As described above, in the error correction based on the conventional inter-code distance, there may be a case where an error caused by communication cannot be corrected correctly. Therefore, as shown in FIG. 4, there is a need for a method that can correct a generated error correctly according to the channel characteristics.

  The present invention has been made in view of such a situation, and enables a digital signal to be wirelessly communicated while having high error correction capability with a relatively simple circuit configuration.

  The transmitting apparatus according to the first aspect of the present invention includes encoding means for encoding a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern, and the n-bit transmission input in parallel. Serial conversion means for generating an RF digital signal by serially converting the carrier wave pattern in synchronization with a clock signal, and transmission means for wirelessly transmitting the RF digital signal.

  The encoding means may encode a digital baseband signal to be transmitted into a predetermined n-bit transmission carrier pattern for each bit.

  The encoding means may encode a digital baseband signal to be transmitted into an n-bit transmission carrier pattern using a lookup table.

  The clock signal may have a variable oscillation frequency.

  The serial conversion means can be constituted by a shift register.

  A transmission method according to a first aspect of the present invention is a transmission method of a transmission device including an encoding unit, a serial conversion unit, and a transmission unit, and a digital baseband signal to be transmitted by the encoding unit is transmitted. An RF digital signal obtained by serially converting the n-bit transmission carrier pattern inputted in parallel by the serial conversion means in synchronization with a clock signal, and encoding step for encoding into a discrete n-bit transmission carrier pattern And a serial conversion step of generating the RF digital signal by a transmission means.

  A program according to a first aspect of the present invention is a program for controlling a transmission apparatus including an encoding unit, a serial conversion unit, and a transmission unit, and is a digital base to be transmitted by the encoding unit. An encoding step for encoding a band signal into a discrete n-bit transmission carrier pattern, and serial conversion of the n-bit transmission carrier pattern input in parallel by serial conversion means in synchronization with a clock signal. The computer of the transmission apparatus is controlled to perform processing including a serial conversion step of generating an RF digital signal and a transmission step of wirelessly transmitting the RF digital signal by a transmission unit.

  In the first aspect of the present invention, a digital baseband signal to be transmitted is encoded into a discrete n-bit transmission carrier pattern, and the n-bit transmission carrier pattern input in parallel is synchronized with a clock signal. Then, an RF digital signal is generated by serial conversion, and the RF digital signal is wirelessly transmitted.

  A receiving apparatus according to a second aspect of the present invention includes a receiving unit that receives a wirelessly transmitted RF digital signal, and n bits by performing parallel conversion on the received RF digital signal in synchronization with a clock signal. Based on the relationship between the parallel conversion means for converting the received carrier pattern into the received carrier pattern and the previously learned transmission carrier pattern and the received carrier pattern, the n-bit received carrier pattern is converted into a baseband signal corresponding to the transmitted carrier pattern. Decoding means for decoding.

  The decoding means is configured to decode the n-bit received carrier pattern into one bit of a baseband signal corresponding to the transmitted carrier pattern based on the relationship between the previously learned transmitted carrier pattern and the received carrier pattern. can do.

  The decoding means decodes the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on a lookup table indicating a relationship between a transmission carrier pattern learned in advance and the received carrier pattern. Can be.

  The receiving apparatus according to the second aspect of the present invention further includes learning means for learning the relationship between a known transmission carrier pattern transmitted from the transmitting apparatus and the received carrier pattern, and generating the lookup table. be able to.

  The parallel conversion means can be constituted by a shift register.

  A receiving method according to a second aspect of the present invention is a receiving method of a receiving apparatus including a receiving means, a parallel converting means, and a decoding means, and a receiving step of receiving a wirelessly transmitted RF digital signal by the receiving means. A parallel conversion step of converting the received RF digital signal by the parallel conversion means into an n-bit received carrier pattern by performing parallel conversion in synchronization with the clock signal, and a learning by the decoding means in advance. And a decoding step of decoding the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on the relationship between the transmitted carrier pattern and the received carrier pattern.

  A program according to a second aspect of the present invention is a program for controlling a receiving device including receiving means, parallel converting means, and decoding means, and receives a radio frequency transmitted RF digital signal by the receiving means. A receiving step, a parallel converting step for converting the received RF digital signal into an n-bit received carrier pattern by performing parallel conversion in synchronization with a clock signal, and a decoding unit, A computer of a receiving apparatus including a decoding step of decoding the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on the relationship between the learned transmitted carrier pattern and the received carrier pattern Let me control.

  In the second aspect of the present invention, a wirelessly transmitted RF digital signal is received, and the received RF digital signal is converted into an n-bit received carrier pattern by performing parallel conversion in synchronization with a clock signal. Then, based on the relationship between the transmission carrier pattern and the reception carrier pattern learned in advance, the n-bit reception carrier pattern is decoded into a baseband signal corresponding to the transmission carrier pattern.

  A communication system according to a third aspect of the present invention is a communication system including a transmission device and a reception device, wherein the transmission device converts a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern. Encoding means for encoding; serial conversion means for generating an RF digital signal by serially converting the n-bit transmission carrier pattern input in parallel in synchronization with a clock signal; and wireless transmission of the RF digital signal And receiving means for receiving the RF digital signal transmitted wirelessly, and by converting the received RF digital signal into parallel in synchronization with the clock signal, n bits. Parallel conversion means for converting to the received carrier pattern, the transmission carrier pattern learned in advance and the Based on the relationship between the signal carrier pattern, and a decoding means for receiving a carrier wave pattern of said n bits, decodes the baseband signal.

The serial conversion unit of the transmission device and the parallel conversion unit of the reception device may be configured by shift registers having the same configuration.

  In the third aspect of the present invention, a digital baseband signal to be transmitted is encoded into a discrete n-bit transmission carrier pattern by a transmission device, and an n-bit transmission carrier pattern inputted in parallel is An RF digital signal is generated by serial conversion in synchronization with the clock signal, and the RF digital signal is wirelessly transmitted. Then, the RF digital signal transmitted by radio is received by the receiving device, and the received RF digital signal is converted into an n-bit received carrier pattern by performing parallel conversion in synchronization with the clock signal, and learned in advance. Based on the relationship between the transmitted carrier pattern and the received carrier pattern, the n-bit received carrier pattern is decoded into a baseband signal corresponding to the transmitted carrier pattern.

  According to the first aspect of the present invention, a digital signal can be wirelessly transmitted with a relatively simple circuit configuration so that a high error correction capability can be exhibited on the reception side.

  According to the second aspect of the present invention, it is possible to receive a wirelessly transmitted digital signal with a high error correction capability with a relatively simple circuit configuration.

  According to the third aspect of the present invention, a digital signal can be wirelessly communicated with a high error correction capability with a relatively simple circuit configuration.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 5 shows a configuration example of an AV signal processing apparatus according to an embodiment of the present invention.

The AV signal processing device 50 includes a housing 51 and a plurality of substrates 52-1 to 52-n housed in the housing 51. The board 52-1 is provided with an LSI 61-1 that performs wireless communication with another board or the LSI 61-2, and the LSI 61-1 is provided with an antenna 62-1.
The board 52-1 is provided with an LSI 61-2 that performs wireless communication with another board or the LSI 61-1, and the LSI 61-2 is provided with an antenna 62-2.

  The substrates 52-2 to 52-n are configured similarly to the substrate 52-1. Hereinafter, when it is not necessary to distinguish the substrates 52-1 to 52-n from each other, they are simply referred to as the substrate 52. The same applies to LSI 61-1 and LSI 62-2.

  That is, a plurality of substrates 52 are provided inside the casing 51, and a plurality of LSIs 61 that perform wireless communication with each other are provided.

  Here, general wireless communication characteristics inside the housing will be described.

  As described above, communication failures such as multipath occur in the housing. When various signals are wirelessly communicated in the housing, especially high-speed and large-capacity signals represented by video signals are wirelessly communicated. In this case, a loss occurs in the radio signal due to a DC offset or the like generated due to multipath, making it difficult to perform communication.

  Specifically, the radio signal transmitted in the casing is added with white noise, colored noise existing in the casing, or a signal reflected or diffracted by a wall surface or a substrate in the casing. As a result, the waveform of the received signal becomes a distorted waveform different from the waveform of the transmitted signal.

  In particular, the deterioration due to the reflected wave entering the reception point with the same magnitude as the transmitted signal power is serious. The reflected wave is a signal that is the same as the signal waveform that is originally desired to be received, but whose path is different (transmission time is shifted). If the reflected wave overlaps with a signal to be received at the receiving end, the waveform of the received signal is distorted, making decoding difficult. The effect of such multipath becomes more serious as the wireless communication speed increases.

Next, the multipath continuity inside the housing will be described with reference to FIG.
FIG. 6A shows a waveform at the time of transmitting a radio signal (modulation method is ASK modulation) transmitted in the housing. FIG. 6B shows the waveform of the waveform when the radio signal whose waveform is shown in FIG. 6A is received. As is clear from comparison between FIG. A and FIG. B, it can be seen that there is a large difference between the waveform at the time of transmission and the waveform at the time of reception.

  However, the waveform at the time of transmission shown in FIG. 6A is divided at predetermined time intervals so that each peak (14 peaks in the case of FIG. 1A) is included, and their phases are aligned. When superimposed, the result is as shown in FIG. 3C, and it can be seen that the waveform during transmission is a stable rectangle.

  Similarly, the waveform at the time of reception shown in Fig. B is divided at predetermined time intervals so that each peak (in the case of Fig. B, there are 14 peaks) is included, and their phases are aligned. When they are overlapped, the result is as shown in FIG. 4D. The waveform at the time of reception is different from that at the time of transmission, but the shape is stable, that is, it has continuity. Recognize.

  In other words, when the waveform shown in FIG. C is transmitted, the waveform shown in FIG. D is steadily received. Therefore, on the receiving side. If the correspondence between the waveform at the time of reception and the waveform at the time of transmission is learned in advance, for example, when the waveform shown in FIG. D is received, it can operate as if the waveform shown in FIG. .

  In the present invention, wireless communication is performed after learning the relationship between a code to be transmitted in advance and a code to be received by utilizing the continuity of communication characteristics inside the casing as described above.

  Next, a configuration example of the wireless transmission device built in the LSI 61 of FIG. 5 will be described with reference to FIG.

  The wireless transmission device 70 includes a 1-bit DAC (digital / analog converter) 71 that encodes a digital BB signal and converts it into an RF digital signal, and an antenna 72 corresponding to the antenna 62 of FIG. The

  FIG. 8 shows a detailed configuration example of the encoded 1-bit DAC 71. The encoded 1-bit DAC 71 includes a control unit 81, a multiplication unit 82, an LUT (look-up table) memory 83, and a shift register 84.

  The control unit 81 controls the entire encoded 1-bit DAC 71. The multiplier 82 multiplies the clock signal P that is commonly supplied to the LSIs 61 of the AV signal processing device 50 and supplies the clock signal S obtained as a result to the shift register 84. Here, clock signal S = n × clock signal P, where n is an integer. Note that the clock signal P and the multiplication factor n can be changed as appropriate.

  The LUT memory 83 generates a corresponding n-bit parallel carrier pattern for each bit of the BB signal input from the previous stage based on the held LUT 83a, and the n-bit in synchronization with the latch signal from the shift register 84. The carrier pattern is input to the shift register 84 in parallel.

  The shift register 84 performs serial conversion by shifting the n-bit carrier pattern input in parallel from the LUT memory 83 in synchronization with the clock signal S, and outputs the resulting RF digital signal to the antenna 72 at the subsequent stage. To do. That is, the RF digital signal from the shift register 84 can be changed by changing the transmission speed of the clock signal S.

  In addition, the shift register 84 outputs a latch signal to the LUT memory 83 in synchronization with the clock signal P, and the n-bit carrier pattern from the LUT memory 83 is stored in the built-in 1-bit shift register 201A (FIG. 11). Load.

  FIG. 9 shows an example of the LUT 83 a held in the LUT memory 83. The LUT 83a holds an n-bit carrier pattern corresponding to 1 bit (0 or 1) of the BB signal for each LSI as a transmission destination. Note that the transport pattern corresponding to the BB signal is set to be different for each transmission destination.

  For example, in the LUT 83 that holds the LUT 83a shown in the figure, when the LSI 102 is designated as the transmission destination, an n-bit carrier pattern 010101... Is output corresponding to 0 of the BB signal.

  For example, when the LSI 102 is designated as the transmission destination, n-bit carrier patterns 10101010... Are output corresponding to 1 of the BB signal.

  FIG. 10 shows another example of the LUT 83 a held in the LUT memory 83. In this example, the LUT 83a holds a plurality of n-bit carrier patterns corresponding to one bit (0 or 1) of the BB signal for each LSI as a transmission destination. In this way, a plurality of carrier wave patterns are prepared for the same BB signal, and one of the carrier wave patterns is selected and transmitted, so that the design change (for example, the board 52 to the AV signal processing device 50). Add, change of wireless communication speed, etc.).

  Next, a detailed configuration example of the shift register 84 will be described.

  FIG. 11 shows a configuration example corresponding to one bit of n-bit carrier patterns inputted in parallel inputted from the LUT memory 83.

  The 1-bit configuration example includes two 1-bit shift registers 201A and 201B and an AND (logical product) circuit 202.

  Each of the 1-bit shift registers 201A and 201B has a reset terminal (not shown), and clears held information in accordance with a reset signal input from the control unit 81 via the reset terminal.

  The 1-bit shift register 201A is for holding a carrier pattern for 1 bit. The 1-bit shift register 201A loads one bit of the carrier pattern from the LUT 83 in synchronization with the rising or falling of the clock signal P, and outputs the 1 bit held so far from the OUT terminal. Note that whether the clock signal P is synchronized with the rising edge or the falling edge is determined by the relationship with the clock signal S.

  The 1-bit shift register 201B is for generating a latch signal to be supplied to the LUT 83. The 1-bit shift register 201B is set to 1 after the first reset in synchronization with the rise or fall of the clock signal P. Note that whether the clock signal P is synchronized with the rising edge or the falling edge is determined by the relationship with the clock signal S.

  The AND circuit 202 calculates the logical product of the clock signal P and the latch signal, and outputs the calculation result to the 1-bit shift register 201B.

  The 1-bit configuration example can also be adopted when configuring the shift register 103 (FIG. 21) of the wireless reception device 90 described later, and the OUT terminal of the 1-bit shift register 201A configures the shift register 84. Sometimes the IN terminal is used when the shift register 103 is constructed.

  When the shift register 84 corresponding to the n-bit carrier pattern from the LUT memory 83 is configured based on the 1-bit configuration example, a 1-bit shift is performed after the 1-bit shift registers 201A and 201B. The registers 201A and 201B may be configured by connecting (n-1) stages.

  For example, FIG. 12 shows a configuration example of the shift register 84 corresponding to a case where a 2-bit carrier pattern is input in parallel from the LUT memory 83. As shown in the figure, the shift register 84 corresponding to the 2-bit carrier pattern is configured by connecting the 1-bit shift registers 201A and 201B for one stage to the configuration example of FIG.

  FIG. 13 is a timing chart for explaining the operation of the shift register 84 corresponding to the 2-bit carrier pattern shown in FIG. In the figure, a is a clock signal P, b is a clock signal S, c is loaded into the 1-bit shift register 201A1, d is loaded into the 1-bit shift register 201A2, and e is an output of the 1-bit shift register 201A2. . Further, f is a load to the 1-bit shift register 201B1, g is a load to the 1-bit shift register 201B2, and h is a latch signal.

  As shown in the figure, the transmission speed (output speed) of the RF digital signal output from the shift register 84 is changed by adjusting the clock signal P and the clock signal S. In other words, the transmission speed (output speed) of the RF digital signal output from the shift register 84 can be adjusted by controlling the frequencies of the clock signal P and the clock signal S.

  That is, the transmission speed of the RF digital signal can be adjusted by selecting the carrier pattern of the LUT 83a according to the frequency relationship between the clock signal P and the clock signal S.

  For example, when the frequency of the clock signal S is four times the frequency of the clock signal P, four types of carrier patterns corresponding to the BB signal (1 or 0) in the LUT 83a can be set, for example, 1010, 0101, 0011, 1100. .

  In this case, if the carrier patterns 1010 and 0101 are selected and transmitted by the LUT 83a, the transmission speed of the RF digital signal is increased twice as compared with the case where the carrier patterns 0011 and 1100 are selected and transmitted.

  Conversely, if the frequencies of the clock signal P and the clock signal S are determined in accordance with the relationship of the carrier pattern of the LUT 83a, the transmission frequency of the RF digital signal can be adjusted.

  For example, in the LUT 83a, two types of carrier wave patterns corresponding to 1 bit of the BB signal. For example, assume that 10101010 and 0010101 are set. Further, the transmission frequency of the RF digital signal when the frequency of the clock signal P is set to four times the frequency of the clock signal S is assumed to be ff. In this case, if the frequency of the clock signal P is set to double the frequency of the clock signal S, the transmission frequency of the digital signal is ff / 2. If the frequency of the clock signal P is set to 8 times the frequency of the clock signal S, the transmission frequency of the digital signal is 2 × ff.

  Next, FIG. 14 shows a first configuration example of the shift register 84 corresponding to a case where an n-bit carrier pattern is input from the LUT memory 83 in parallel. In the first configuration example, the shift register 84 corresponding to the n-bit carrier pattern is configured by connecting (n−1) -stage 1-bit shift registers 201A and 201B to the configuration example of FIG.

  When the carrier pattern is 2 bits or more, the clock signal S is always faster than the clock signal P, so that the timing of the latch signal becomes strict. Further, since the clock signal S is used as the output timing of the RF digital signal, it becomes more severe than usual. Therefore, a device is also required for the arrangement of the n-stage 1-bit shift registers 201A and 201B constituting the shift register 84.

  FIG. 15 shows a second configuration example of the shift register 84 corresponding to a case where an n-bit carrier pattern is input from the LUT memory 83 in parallel. The second configuration example is a configuration example specialized especially when n is an even number. As shown in the figure, the n-stage 1-bit shift register 201A and the n-stage 1-bit shift register 201B are arranged symmetrically in two columns of (n / 2) stages, respectively. The speed of the latch signal can be made to correspond to the signal S).

  FIG. 16 shows a third configuration example that is symmetric to the second configuration example shown in FIG. Also in the third configuration example, the n-stage 1-bit shift register 201A and the n-stage 1-bit shift register 201B are arranged symmetrically in two columns of (n / 2) stages, respectively, so that the speed of the RF digital signal ( The speed of the latch signal can be made to correspond to the clock signal S).

  FIG. 17 shows a fourth configuration example of the shift register 84 corresponding to a case where an n-bit carrier pattern is input from the LUT memory 83 in parallel. The fourth configuration example is a configuration example specialized especially when n is an odd number. As shown in the figure, n-stage 1-bit shift register 201A and n-stage 1-bit shift register 201B are arranged symmetrically in two columns of (n / 2) stages and ((n / 2) -1), respectively. Thus, the speed of the latch signal can be made to correspond to the speed of the RF digital signal (clock signal S).

  Although illustration is omitted, the shift register 84 corresponding to the case where n (n is an odd number) bit carrier pattern is input in parallel may be arranged symmetrically with the fourth configuration example shown in FIG. it can.

  Next, FIG. 18 shows a fifth configuration example of the shift register 84 corresponding to the case where an n-bit carrier pattern is input from the LUT memory 83 in parallel. In the fifth configuration example, a switch 211A is provided between two columns of the (n / 2) -stage 1-bit shift register 201A in the second configuration example shown in FIG. 15, and (n / 2) -stage A switch 211B is provided between two columns of the 1-bit shift register 201B.

  As shown in the figure, if the connection of the 1-bit register 201A can be changed by the switch 211A and the connection of the 1-bit register 201B can be changed by the switch 211B, it can cope with various RF digital signals and their communication speeds. Is possible.

  Further, by adjusting the frequencies of the clock signal P and the clock signal S, for example, intermittent operation of the RFF digital signal and pulse wave communication are possible.

  Next, FIG. 19 shows a sixth configuration example of the shift register 84 corresponding to the case where an n-bit carrier pattern is input in parallel from the LUT memory 83. In the sixth configuration example, n-stage 1-bit shift registers 201A are arranged in a ring, and a switch 221A is provided for the connection, and n-stage 1-bit shift registers 201B are arranged in a ring, A switch 221B is provided for connection.

  As shown in the figure, if the connection of the 1-bit register 201A can be changed by the switch 221A and the connection of the 1-bit register 201B can be changed by the switch 221B, it can cope with various RF digital signals and their communication speeds. Is possible.

  Further, the number of stages of the 1-bit shift registers 201A and 201B may be determined in accordance with specifications of the maximum speed and the minimum speed of the RF digital signal assumed in the future.

  Next, a configuration example of the wireless reception device built in the LSI 61 of FIG. 5 will be described with reference to FIG.

  This wireless reception device 90 corresponds to the wireless transmission device 70 shown in FIG. 7, receives the RF digital signal transmitted from the wireless transmission device 70, and converts the finally transmitted BB signal to the subsequent stage. Output to.

  The wireless receiving device 90 includes an antenna 91 corresponding to the antenna 62 in FIG. 5 and a 1-bit ADC (analog / digital converter) 92 with decoding that generates a BB signal based on an RF digital signal received by the antenna 91. The

  FIG. 21 shows a detailed configuration example of the 1-bit ADC 92 with decoding. The 1-bit ADC 92 with decoding includes a control unit 101, a multiplication unit 102, a shift register 103, and an LUT (look-up table) 104.

  The control unit 101 controls the entire 1-bit ADC 92 with decoding. The multiplier 102 multiplies the clock signal P that is commonly supplied to the LSIs 61 of the AV signal processing device 50 and supplies the clock signal S obtained as a result to the shift register 103. Here, clock signal S = n × clock signal P, where n is an integer. The control unit 101 can be integrated with the control unit 81 of the encoded 1-bit DAC 71.

  The shift register 103 shifts the RF digital signal serially input from the antenna 91 in synchronization with the clock signal S. Further, the shift register 103 outputs a latch signal to the LUT memory 104 in synchronization with the clock signal P, and information (1 of the RF digital signal) loaded in each built-in 1-bit shift register 201A (FIG. 11). Bit) to the LUT memory 104. As a result, an n-bit parallel carrier pattern is supplied from the shift register 103 to the LUT memory 104.

  The LUT memory 104 refers to the held LUT 104a (FIG. 22), converts the n-bit carrier pattern input from the shift register 103 into a 1-bit BB signal and outputs it. The LUT 104a is generated by a learning process described later based on the continuity of the wireless communication characteristics of the casing 51.

  FIG. 22 shows an example of the LUT 104 a held in the LUT memory 104. In the LUT 104a, one bit (0 or 1) of the BB signal is associated with each of a plurality of carrier patterns that may be received for each LSI serving as a transmission source.

  For example, in the case where the LUT 104a shown in FIG. 10 is held, when the transmission source is the LSI 101 and an n-bit carrier pattern 010101... Is received, 0 of the BB signal is output.

  For example, when the transmission source is the LSI 101 and the n-bit carrier pattern 110011... Is received, 1 of the BB signal is output.

  Next, a detailed configuration example of the shift register 103 will be described. As described above, the shift register 103 can be configured by connecting n configuration examples corresponding to one bit of the n-bit carrier pattern shown in FIG. 11 for n stages.

  FIG. 23 shows a configuration example of the shift register 103 corresponding to a case where an RF digital signal is converted into an n-bit carrier pattern and output to the LUT memory 104 in parallel. In this configuration example, similarly to the second configuration example of the shift register 84 shown in FIG. 15, each of the n-stage 1-bit shift register 201A and the n-stage 1-bit shift register 201B includes (n / 2) stages. They are arranged in two rows symmetrically.

  Note that the arrangement of the shift register 103 can be devised in the same manner as each configuration example of the shift register 84 illustrated in FIGS.

  Further, as is clear by comparing the configuration example of the shift register 103 shown in FIG. 23 with the second configuration example of the shift register 84 shown in FIG. 15, the difference is shown in FIG. The configuration example of the shift register 103 uses the IN terminal of the 1-bit shift register 201A1, whereas the second configuration example of the shift register 84 shown in FIG. 15 uses only the OUT terminal of the 1-bit shift register 201An. It is.

  Therefore, as shown in FIG. 24, if the switch 231 for switching the IN terminal of the 1-bit shift register 201A1 and the OUT terminal of the 1-bit shift register 201An is provided, the shift register 84 or the shift register 103 can be used depending on the switch switching. A functioning shared shift register 230 can be constructed.

  If the shift register 84 of the encoded 1-bit DAC 71 in FIG. 8 and the shift register 104 of the decoded 1-bit ADC 92 in FIG. 21 are replaced with the shared register 230, respectively, the encoded 1-bit DAC 71 and the decoded signal are decoded. The attached 1-bit ADC 92 can be integrated. That is, the wireless transmission device 70 of FIG. 7 and the wireless reception device 90 of FIG. 20 can be integrated, and mounting on the LSI 61 is realized at low cost.

  Next, the operation of the LSI 61 on which the wireless transmission device 70 and the wireless reception device 90 are mounted will be described with reference to the flowchart of FIG. Before this operation is started, the operation to be performed is a learning mode for learning the LUT 104a held in the LUT memory 104 of the 1-bit ADC 92 with decoding of the wireless reception device 90, and a transmission for transmitting information. It is assumed that the mode, the reception mode for receiving information, or the standby mode waiting for the determination of the mode to be executed is determined.

  In particular, regarding the timing at which the operation to be executed is determined in the learning mode, for example, when the configuration in the casing 51 changes (for example, the substrate 52 is added or deleted), the AV signal processing device 50 is turned on. When it is done, it may be every predetermined period (considering secular change, for example, every several months), or when the specification of the AV signal processing device 50 is changed.

  In step S1, the LSI 61 (the control units 81 and 101 thereof) determines whether or not the operation to be executed is determined as the learning mode. If it is determined that the operation to be performed is determined as the learning mode, the process proceeds to step S2. In step S <b> 2, the control unit 101 controls the 1-bit ADC 92 with decoding of the wireless reception device 90 to execute a learning process (details will be described later). If it is determined in step S1 that the operation to be executed is not determined to be the learning mode, step S2 is skipped and the process proceeds to step S3.

  In step S3, the LSI 61 (the control units 81 and 101 thereof) determines whether or not the operation to be executed is determined as the transmission mode. If it is determined that the operation to be performed is determined as the transmission mode, the process proceeds to step S4. In step S4, the control unit 81 controls the encoded 1-bit DAC 71 of the wireless transmission device 70 to execute transmission processing (details will be described later). If it is determined in step S3 that the operation to be executed is not determined as the transmission mode, step S4 is skipped and the process proceeds to step S5.

  In step S5, the LSI 61 (the control units 81 and 101 thereof) determines whether or not the operation to be executed is determined as the reception mode. If it is determined that the operation to be performed is determined as the reception mode, the process proceeds to step S6. In step S <b> 6, the control unit 101 controls the 1-bit ADC 91 with decoding of the wireless reception device 90 to execute reception processing (details will be described later). If it is determined in step S5 that the operation to be performed is not determined as the reception mode, step S6 is skipped and the process proceeds to step S7.

  In step S7, the LSI 61 (the control units 81 and 101 thereof) determines whether or not the operation to be executed is determined as the standby mode. When it is determined that the operation to be performed is determined to be the standby mode, the process returns to step S1 and the subsequent processing is repeated. If it is determined in step S7 that the operation to be executed is not determined to be the standby mode, the operation of the LSI 61 is terminated. This is the end of the description of the operation of the LSI 61.

  Next, the learning process in step S2 of FIG. 25 will be described in detail with reference to the flowchart of FIG.

  This learning process is a process executed by each LSI 61 to learn and generate the LUT 104a used at the time of reception, and wireless communication is performed with a known carrier pattern determined in advance with an LSI other than itself as a wireless communication partner. To execute.

  That is, in step S11, the control unit 101 of the wireless reception device 90 mounted on the LSI 61 determines one of the LSIs other than itself as a wireless communication partner as the transmission source. In step S12, the control unit 101 initializes a repetition parameter h indicating the number of repetitions of steps S13 to S18 to zero.

  In step S <b> 13, the control unit 101 causes the transmission source LSI (the wireless transmission device 70) to transmit a known carrier pattern, which is determined in advance for use in the learning process, by the control unit 101 itself. This known carrier pattern is transmitted wirelessly as an RF digital signal.

  In step S14, the control unit 101 calculates a correlation value between the RF digital signal received by the antenna 91 of the wireless reception device 90 and the transmitted known carrier pattern, and determines the position where the calculated correlation value is maximum. By detecting, the head position of the received RF digital signal is determined.

  In step S <b> 16, the control unit 101 increments the reception frequency of the received RF digital signal pattern by one in the plot diagram showing each pattern of the RF digital signal that can be received and the reception frequency. The plot in step S16 will be described later with reference to FIGS. 27 and 28.

  In step S17, the control unit 101 determines whether or not the repetition parameter h has reached a predetermined upper limit value j (very large number). If it is determined that the repetition parameter h has not reached the predetermined upper limit value j, the control unit 101 advances the processing to step S18 and increments the repetition parameter h by 1. Thereafter, the process returns to step S13, and steps S13 to S18 are repeated.

  When communication with a known carrier pattern is repeated j times with the current transmission source, it is determined in step S17 that the repetition parameter h has reached a predetermined upper limit value j, and the process proceeds to step S19. .

  In step S19, the control unit 101 creates an LUT 104a to be used for decoding the carrier pattern from the RF digital signal transmitted from the LSI determined as the transmission source in step S11, based on the plot result in the process of step S16. It is held in the LUT memory 104.

  In step S <b> 20, the control unit 101 determines whether or not there remains any LSI other than itself that is a wireless communication partner that has not been determined as the transmission source in the process of step S <b> 11. When it determines with remaining, the control part 101 returns a process to step S11, and repeats step S11 thru | or S20. If it is determined in step S20 that all LSIs other than the self that are wireless communication partners have been determined as transmission sources, the learning process ends.

  Here, FIG. 27 and FIG. 28 show examples of plot diagrams showing the reception frequency of each pattern of the received RF digital signal plotted in the process of step S16.

  In the example of FIG. 27, the reception frequency of each pattern of the received RF digital signal when 000 or 111 is transmitted as a known carrier pattern is shown. The horizontal axis represents the pattern of the received RF digital signal, and the vertical axis represents the reception frequency. Also, the RF digital signal pattern received when the known carrier pattern 000 is transmitted is indicated by a colorless (white) bar, and the RF digital signal pattern received when the known carrier pattern 111 is transmitted. Is indicated by a colored (shaded pattern) bar.

  According to FIG. 27, when the carrier wave pattern 000 is transmitted, the RF digital signal pattern 000 is received most frequently. Further, when the carrier wave pattern 111 is transmitted, the RF digital signal pattern 111 is received most frequently.

  However, attention should be paid to the RF digital signal patterns 010 and 101 in FIG.

  The RF digital signal pattern 010 is converted to 000 according to the error correction based on the conventional intersymbol distance. However, according to FIG. 27, the RF digital signal pattern 010 is hardly received when the carrier pattern 000 having a shorter inter-code distance is transmitted among the carrier patterns 000 and 111, and the inter-code distance is less. When the farther carrier pattern 111 is transmitted, it is received. Therefore, when the RF digital signal pattern 010 is received, it is learned to convert it to 111.

  Further, the RF digital signal pattern 101 is converted to 111 according to the error correction based on the conventional intersymbol distance. However, according to FIG. 27, the RF digital signal pattern 101 is hardly received when the carrier pattern 111 with the shorter inter-code distance is transmitted among the carrier patterns 000 and 111, and the inter-code distance is smaller. When the farther carrier pattern 000 is transmitted, it is received. Therefore, when the RF digital signal pattern 101 is received, it is learned to convert it to 000.

  In the example of FIG. 28, when 110101 or 000111 is transmitted as a known carrier pattern, the reception frequency of each pattern of 3 bits extracted every other bit from the MSB (Most Significant Bit) side of the received RF digital signal is shown. Show. For example, when 110101 is received as an RF digital signal, the pattern is 100. For example, when 000111 is received as an RF digital signal, the pattern is 001.

  The horizontal axis indicates a 3-bit pattern extracted every other bit from the MSB side of the received RF digital signal, and the vertical axis indicates the reception frequency. Also, the RF digital signal pattern received when the known carrier pattern 110101 is transmitted is indicated by a colorless (white) bar, and the RF digital signal pattern received when the known carrier pattern 000111 is transmitted. Is indicated by a colored (shaded pattern) bar.

  Of note in FIG. 28 are the 3-bit patterns 100 and 001 of the received RF digital signal.

  The 3-bit pattern 100 of the RF digital signal originally corresponds to the carrier pattern 110101, but the reception frequency is higher when the carrier pattern 000111 is transmitted. Therefore, when the 3-bit pattern 100 of the RF digital signal is received, the LUT 104a is learned so that it can also be converted into the carrier pattern 000111.

  The RF digital signal pattern 001 originally corresponds to the carrier pattern 000111, but the frequency of reception is higher when the carrier pattern 110101 is transmitted. Therefore, when the 3-bit pattern 001 of the RF digital signal is received, the LUT 104a is learned so that it can also be converted into the carrier wave pattern 110101.

  This is the end of the description of the learning process.

  Next, the transmission process in step S4 of FIG. 25 will be described in detail with reference to the flowchart of FIG.

  In step S <b> 31, the LSI 61 receives a radio signal in order to confirm communication by an LSI other than itself by the mounted radio receiving device 90. However, it is not necessary here to generate the BB signal from the RF digital signal. In step S32, the LSI 61 determines whether or not an RF digital signal has been received in the process of step S31. If it is determined that the RF digital signal has been received, the process proceeds to step S33.

  In step S33, the LSI 61 waits for a predetermined time in order to detect a communication interval between LSIs other than itself. After this standby, the process returns to step S31, and the subsequent processes are repeated.

  In step S32, if it is determined in step S31 that the RF digital signal is not received, the process proceeds to step S34. In step S34, the LSI 61 waits for the communication interval of communication by the LSI other than itself detected in the process of step S33, and then advances the process to step S35.

  In steps S35 to S38, the wireless transmission device 70 of the LSI 61 performs wireless communication of information to be transmitted. That is, in step S35, the LSI 61 adds identification information indicating the destination LSI to the information to be transmitted, generates a BB signal, and outputs the BB signal to the LUT memory 83 of the encoded 1-bit DAC 71.

  In step S36, the LUT memory 83 generates an n-bit parallel carrier pattern corresponding to each bit of the input BB signal based on the held LUT 83a, and is synchronized with the latch signal from the shift register 84. A bit carrier pattern is input to the shift register 84 in parallel.

  In step S37, the shift register 84 performs serial conversion by shifting the n-bit carrier pattern input in parallel from the LUT memory 83 in synchronization with the clock signal S, and converts the resulting RF digital signal into the subsequent stage. Output to the antenna 72.

  In step S38, the wireless transmission device 70 of the LSI 61 determines whether all information to be transmitted has been transmitted. And when the information which should be transmitted remains, it determines with not transmitting all the information which should be transmitted, and the wireless transmission apparatus 70 returns to step S35, and repeats the process after it. If it is determined in step S38 that all the information to be transmitted has been transmitted, the wireless transmission device 70 ends this transmission process. This is the end of the description of the transmission process.

  Next, the transmission process in step S6 of FIG. 25 will be described in detail with reference to the flowchart of FIG.

  In step S <b> 51, the LSI 61 receives the RF digital signal by the mounted wireless reception device 90. Specifically, the RF digital signal is received by the antenna 91 and supplied to the 1-bit ADC 92 with decoding. In step S52, the shift register 103 of the 1-bit ADC 92 with decoding converts the RF digital signal into an n-bit parallel carrier pattern and supplies it to the LUT memory 104.

  In step S53, the LUT memory 104 outputs one bit at a time of the BB signal corresponding to the input n-bit parallel carrier pattern based on the held LUT 104a.

  In step S54, the radio reception device 90 of the LSI 61 determines whether or not reception is completed. If it is determined that the reception has not ended, the wireless reception device 90 returns to step S51 and repeats the subsequent processing. If it is determined in step S54 that reception has ended, the wireless reception device 90 ends the reception process. This is the end of the description of the reception process.

  In addition, when a plurality of wireless communications are performed simultaneously in the housing 51, as a method of preventing the interference, a method of making the clock signals P used in the respective communication systems orthogonal to each other, and the respective communications A method of orthogonalizing the carrier pattern in the LUT 83a used at the time of system transmission can be considered.

  The method of making the clock signals P used in each communication system orthogonal to each other is, for example, that the frequency of the clock signal P of one communication system is 4 GHz and the frequency of the clock signal P of the other communication system is 8 GHz. do it.

The method of orthogonalizing the carrier pattern in the LUT 83a used at the time of transmission of each communication system is, for example, that in one communication system, 1 of the BB signal is changed to the carrier pattern 1001110, 0 of the BB signal is changed to the carrier pattern 0110001,
In the other communication system, 1 of the BB signal may be set to the carrier pattern 1001011 and 0 of the BB signal may be set to the carrier pattern 0110100.

  Whether the clock signals P used in the respective communication systems are orthogonal to each other (for example, the frequency of the clock signal P of one communication system is 4 GHz and the frequency of the clock signal P of the other communication system is 8 GHz). The carrier pattern to be transmitted is orthogonal

  As described above, according to the wireless transmission device and the wireless reception device to which the present invention is applied, the RF digital signal can be flexibly changed. By providing such flexibility, it becomes easy to redesign the carrier wave pattern even after being manufactured as a product such as the AV signal processing device 50, for example. Therefore, even after being manufactured as a product such as the AV signal processing apparatus 50, it is possible to easily cope with the evolution or expansion of functions. In addition, it can be expected that the manufactured product can be easily verified.

  By the way, the above-described series of processing can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a recording medium in a general-purpose personal computer or the like.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  The program may be processed by a single computer, or may be distributedly processed by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows an example of a structure of the conventional radio | wireless transmitter. It is a block diagram which shows an example of a structure of the conventional radio | wireless receiver. It is a figure explaining error correction based on the distance between codes. It is a figure explaining the error correction made into an ideal. It is a figure which shows the structural example of the AV signal processing apparatus to which this invention is applied. It is a figure explaining the continuity of the radio | wireless communication characteristic in a housing | casing. It is a block diagram which shows the structural example of the radio | wireless transmitter to which this invention is applied. It is a block diagram which shows the structural example of 1 bit DAC with an encoding of FIG. It is a figure which shows the example of LUT used at the time of transmission. It is a figure which shows the example of LUT used at the time of transmission. It is a block diagram which shows the structural example for 1 bit of the shift register of FIG. It is a block diagram which shows the structural example of the shift register of FIG. 8 corresponding to a 2-bit carrier wave pattern. 13 is a timing chart for explaining the operation of the shift register of FIG. 12. FIG. 9 is a block diagram illustrating a first configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. FIG. 9 is a block diagram illustrating a second configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. FIG. 9 is a block diagram illustrating a third configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. FIG. 9 is a block diagram illustrating a fourth configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. FIG. 9 is a block diagram illustrating a fifth configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. FIG. 9 is a block diagram illustrating a sixth configuration example of the shift register of FIG. 8 corresponding to an n-bit carrier pattern. It is a block diagram which shows the structural example of the radio | wireless receiving apparatus to which this invention is applied. FIG. 21 is a block diagram illustrating a configuration example of a 1-bit ADC with decoding in FIG. 20. It is a figure which shows the example of LUT used at the time of reception. It is a block diagram which shows the structural example of the shift register of FIG. 21 corresponding to a n-bit carrier wave pattern. It is a block diagram which shows the structural example of the shared shift register corresponding to a n-bit carrier wave pattern. 6 is a flowchart illustrating an operation performed by an LSI equipped with a wireless communication device and a wireless reception device. FIG. 26 is a flowchart detailing a learning process in step S <b> 2 of FIG. 25. It is a figure explaining the process of step S16 of FIG. It is a figure explaining the process of step S16 of FIG. FIG. 26 is a flowchart detailing a transmission process in step S4 of FIG. 25. FIG. FIG. 26 is a flowchart detailing a reception process in step S <b> 2 of FIG. 25.

Explanation of symbols

  51 casing, 61 LSI, 71 1-bit DAC with encoding, 81 control unit, 82 multiplication unit, 83 LUT memory, 83a LUT, 84 shift register, 90 wireless receiver, 92 1-bit ADC with decoding, 101 control unit, 102 multiplication unit, 103 shift register, 104 LUT memory, 104a LUT, 201 1-bit shift register, 202 AND circuit, 211 switch, 221 switch

Claims (16)

Encoding means for encoding a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern;
Serial conversion means for generating an RF digital signal by serially converting the n-bit transmission carrier pattern input in parallel in synchronization with a clock signal;
Transmitting means comprising: a transmitting means for wirelessly transmitting the RF digital signal. The transmission device according to claim 1, wherein the encoding means encodes a digital baseband signal to be transmitted into a predetermined n-bit transmission carrier pattern for each bit. The transmission device according to claim 1, wherein the encoding unit encodes a digital baseband signal to be transmitted into an n-bit transmission carrier pattern using a lookup table. The transmission device according to claim 1, wherein an oscillation frequency of the clock signal is variable. The transmission device according to claim 1, wherein the serial conversion unit includes a shift register. Encoding means;
Serial conversion means;
In a transmission method of a transmission device comprising a transmission means,
An encoding step of encoding a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern by an encoding means;
A serial conversion step of generating an RF digital signal by serially converting the n-bit transmission carrier pattern inputted in parallel by the serial conversion means in synchronization with a clock signal;
A transmission method comprising: a transmission step of wirelessly transmitting the RF digital signal by a transmission means. Encoding means;
Serial conversion means;
A program for controlling a transmission device comprising a transmission means,
An encoding step of encoding a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern by an encoding means;
A serial conversion step of generating an RF digital signal by serially converting the n-bit transmission carrier pattern inputted in parallel by the serial conversion means in synchronization with a clock signal;
A program for causing a computer of a transmission apparatus to control a process including a transmission step of wirelessly transmitting the RF digital signal by a transmission means. Receiving means for receiving a wirelessly transmitted RF digital signal;
Parallel conversion means for converting the received RF digital signal into an n-bit received carrier pattern by performing parallel conversion in synchronization with a clock signal;
And a decoding unit configured to decode the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on a relationship between the transmission carrier pattern learned in advance and the received carrier pattern. The decoding means decodes the n-bit received carrier pattern into one bit of a baseband signal corresponding to the transmitted carrier pattern based on a relationship between the previously learned transmitted carrier pattern and the received carrier pattern. 9. The receiving device according to 8. The decoding means decodes the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on a lookup table indicating a relationship between a transmission carrier pattern learned in advance and the received carrier pattern. The receiving device according to claim 8 or 9. The receiving device according to claim 10, further comprising learning means for learning the relationship between a known transmission carrier pattern transmitted from the transmission device and the received carrier pattern to generate the lookup table. The transmission device according to claim 8, wherein the parallel conversion unit includes a shift register. Receiving means;
Parallel conversion means;
In a receiving method of a receiving device comprising:
A receiving step of receiving a wirelessly transmitted RF digital signal by a receiving means;
A parallel conversion step of converting the received RF digital signal by a parallel conversion means into a n-bit received carrier pattern by performing parallel conversion in synchronization with a clock signal;
And a decoding step of decoding the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on a relationship between the transmission carrier pattern learned in advance and the received carrier pattern by a decoding means. Method. Receiving means;
Parallel conversion means;
A program for controlling a receiving device comprising:
A receiving step of receiving a wirelessly transmitted RF digital signal by a receiving means;
A parallel conversion step of converting the received RF digital signal by a parallel conversion means into a n-bit received carrier pattern by performing parallel conversion in synchronization with a clock signal;
And a decoding step of decoding the n-bit received carrier pattern into a baseband signal corresponding to the transmitted carrier pattern based on a relationship between the previously learned transmitted carrier pattern and the received carrier pattern by a decoding unit. Program for controlling the computer of the transmission device. In a communication system composed of a transmission device and a reception device,
The transmitter is
Encoding means for encoding a digital baseband signal to be transmitted into a discrete n-bit transmission carrier pattern;
Serial conversion means for generating an RF digital signal by serially converting the n-bit transmission carrier pattern input in parallel in synchronization with a clock signal;
Transmitting means for wirelessly transmitting the RF digital signal;
The receiving device
Receiving means for receiving the RF digital signal transmitted wirelessly;
Parallel conversion means for converting the received RF digital signal into an n-bit received carrier pattern by performing parallel conversion in synchronization with the clock signal;
A communication system comprising: decoding means for decoding the n-bit received carrier pattern into the baseband signal based on a relationship between the transmission carrier pattern and the received carrier pattern learned in advance. The communication system according to claim 15, wherein the serial conversion unit of the transmission device and the parallel conversion unit of the reception device are configured by shift registers having the same configuration.

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