JP5510330B2 - Demodulator and demodulation method - Google Patents

Description

(Description of related applications)
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-232281 (filed on Sep. 10, 2008), the entire contents of which are incorporated herein by reference. Shall.

  The present invention relates to a demodulator and a demodulation method, and more particularly to a technique for demodulating a multi-level phase modulation signal.

  As a system for modulating a carrier wave with digital data, ASK (amplitude modulation) for controlling the amplitude of the carrier wave corresponding to the digital data value, FSK (frequency modulation) for controlling the frequency, and PSK (phase modulation) for controlling the phase are used. It is roughly divided into species. PSK can achieve the best bit error rate if the received signal has the same SNR (signal to noise power ratio). By the way, when demodulating PSK, unlike the case of ASK and FSK, it is inevitable to compare the phase-shifted carrier wave signal with the received signal. As the PSK, for example, in the case of a quaternary phase modulation (QPSK) signal, as shown in the digital radio receiver described in Patent Document 1, a generated regenerated carrier wave, a 90 degree phase delayed regenerated carrier wave, 180 degrees The four-phase reference signal of the phase-delayed reproduced carrier and the 270-degree phase delayed reproduced carrier is simultaneously compared with the received QPSK signal at each of times t and t + 1 / fs (fs is the frequency of the sampling clock).

As a related technique, Non-Patent Document 1 describes configurations of a phase detector and a charge pump.
International Publication No. 2006/046632 Pamphlet Behzad Rezavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill, 2001, p. 554-p. 556

  The entire disclosure of the above patent documents and non-patent documents is incorporated herein by reference. The following analysis is given by the present invention.

  The conventional demodulator described with reference to Patent Document 1 requires N (N is an integer of 2 or more) phase-shifted reference signals, and these N reference signals and received signals N comparison circuits are required to simultaneously compare. Therefore, the number of comparison circuits increases as the multivalue level increases, and the circuit and power consumption increase.

  Therefore, an object of the present invention is to provide a demodulator and a demodulation method with low power consumption and area saving even when the multilevel value of phase modulation becomes high.

A demodulator according to one aspect of the present invention is a demodulator that demodulates an N-value (N is an integer of 2 or more) phase-modulated received signal, and has the same frequency as the carrier wave related to the received signal N phase shift clocks corresponding to each of the N values are serialized within one data symbol period using a predetermined serialized clock signal, and the serialized signal is output as a reference signal a reference signal generator, a comparator for comparing the received signal and the reference signal, the 1 data symbol period definitive comparator comparison results in the based, closest to that the reference phase difference of the received signal comprising a decoder for outputting a digital baseband data values corresponding to the position phase of the signal.

A demodulation method according to another aspect of the present invention is a method of demodulating an N-value (N is an integer of 2 or more) phase-modulated received signal, and has the same frequency as the carrier wave related to the received signal. And serializing N phase shift clocks corresponding to each of the N values within one data symbol period using a predetermined serialized clock signal, and outputting the serialized signal as a reference signal When the steps of comparing the received signal and the reference signal, the 1 data symbol period definitive in comparison, based on the result value corresponding to the position phase of the reference signal that is closest to the phase difference between the received signal Outputting the digital baseband data.

  According to the present invention, even when the multilevel value of the phase modulation is increased, it can be demodulated by a circuit with low power consumption and area saving.

It is a block diagram which shows the structure of the demodulator based on 1st Example of this invention. It is a timing chart showing operation of a demodulator concerning the 1st example of the present invention. It is a block diagram which shows the structure of the demodulator based on the 2nd Example of this invention.

11 reference signal generator 12 comparator 13, 13a decoder 14 selector 15 phase detector / charge pump / AD converter 21 0 degree shift clock signal 22 180 degree shift clock signal 23 serialized clock signal 24 reference signal 25 received signal 26 comparison Clock signal 27, 27a Comparison result signal 28 Demodulated signal

  The demodulator according to the embodiment of the present invention is a demodulator that demodulates an N-value (N is an integer of 2 or more) phase-modulated received signal (25 in FIG. 1), and is the same as the carrier wave related to the received signal. A reference signal generator (11 in FIG. 1) for generating a reference signal (24 in FIG. 1) having a frequency and sequentially phase-modulating all N values within one data symbol period, and a received signal and a reference signal And a decoder (13 in FIG. 1) that demodulates the received signal based on the comparison result of the comparator.

  In the demodulator of the present invention, the comparator obtains the phase difference between the received signal and the reference signal for each of the N phases within one data symbol period, and the decoder corresponds to the phase modulation with the smallest phase difference. The value may be decoded.

  In the demodulator of the present invention, the comparator may convert the phase difference between the received signal and the reference signal into a DC value and output the DC value as a digital value.

  In the demodulator of the present invention, the reference signal generator switches a signal that has been phase-modulated corresponding to all of the N values within one data symbol period in accordance with the timing specified by the serialized clock signal as a reference signal. You may make it provide the selector (14 of FIG. 1) to output.

  A demodulator according to another embodiment of the present invention is a device to which an electrical signal modulated with N phases p1, p2,... PN is input, and the communication is performed on the input signal. Is generated, and a phase modulation signal of N values is generated by completing all the phase shifts of p1, p2,..., PN within a data symbol period. A phase modulator, a comparator having a function of comparing the input signal and the signal output from the phase modulator, and a signal comparison result output from the demodulator. And a decoder characterized in that one of the N phase differences closest to the inputted signal phase is determined from the phase differences of p1, p2,... PN. Equipped with demodulating function of value phase modulation signal A demodulator phase modulated signal.

  In the demodulator of the present invention, it is preferable that p1, p2,..., PN are compared with the input signal within a data symbol period, and detection of all phase differences is completed.

  In the demodulator of the present invention, in the operation of comparing the input signal and the signal output from the phase modulator, the comparison of the voltage or current value of both signals is p1, p2,. Comparators that are possible in all ways may be included.

  In the demodulator of the present invention, in the operation of comparing the input signal and the signal output from the phase modulator, it is possible to convert the phase difference between them into a DC value and output it as a digital value. A comparator may be included.

  According to the demodulator as described above, it is possible to provide low power operability and area saving circuit realization that cannot be achieved by the multilevel PSK demodulation of the conventional configuration. The reason is that, conventionally, N comparison circuits are required to simultaneously reference N reference signals during N-value PSK demodulation. On the other hand, in the present invention, N reference signals are serialized and used as a reference signal for waveform comparison with the received signal, so that only one comparison circuit is required.

  Furthermore, it is possible to demodulate from BPSK to an arbitrary N-value PSK with the same configuration. The reason for this is that, in order to change the multi-value level at the time of demodulation, if the reference signal is serialized by an N: 1 selector, it can be handled by a control signal without changing the circuit.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a block diagram showing the configuration of the demodulator according to the first embodiment of the present invention. In FIG. 1, the demodulator includes a reference signal generator 11, a comparator 12, and a decoder 13. The reference signal generator 11 corresponds to a phase modulator and includes a selector 14. The selector 14 selects either the 0 degree shift clock signal 21 or the 180 degree shift clock signal 22 corresponding to the level of the serialized clock signal 23 and outputs the selected signal to the comparator 12 as the reference signal 24. The comparator 12 compares the received signal 25 with the reference signal 24 and outputs a comparison result signal 27 to the decoder 13. The decoder 13 outputs a demodulated signal 28 that is a decoded output based on the comparison result signal 27.

  In the demodulator having such a configuration, first, the received signal 25 received in communication is input to the comparator 12 that performs waveform comparison with the reference signal 24 for phase modulation. On the other hand, the 0-degree shift clock signal 21 and the 180-degree shift clock signal 22 are used as a reference when demodulating BPSK. These two clock signals are generated in the reference signal generator 11 and then serialized by switching the 0 degree shift clock signal 21 and the 180 degree shift clock signal 22 in accordance with the serialized clock signal 23 in the selector 14. The reference signal 24 is input to the comparator 12 in the same manner as the received signal 25.

  The comparator 12 also receives a comparison clock signal 26 that defines the timing for comparing the received signal 25 and the reference signal 24. Note that the comparator 12 is composed of a 1-bit quantizer, and the magnitude relationship between the received signal 25 and the reference signal 24, which are analog values, is compared according to the timing specified by the comparison clock signal 26, and the result of the comparison May be output as a comparison result signal 27 represented by binary values of 0 and 1. The comparison result signal 27 is input to the decoder 13 and appropriately subjected to arithmetic processing, and then output as a demodulated signal 28 which is desired digital baseband data.

  A feature of the demodulator configured as described above is that there is only one comparator 12 regardless of the multilevel. Note that a reference signal generator 11 is added as compared with the prior art. In this case, by switching the reference signal according to the data symbol clock at the time of transmission in the same block, the transmission side can be shared with the reception side as a modulator. Does not occur.

  Next, the operation of the demodulator will be described. FIG. 2 is a timing chart showing the operation of the demodulator according to the first embodiment of the present invention. Here, BPSK is considered in which digital baseband data “1” corresponds to 0 degree shift, and digital baseband data “0” corresponds to 180 degree shift. Further, consider an example in which the baseband data “0” is modulated in the data symbol period T1, that is, a case where the received BPSK signal is inverted 180 degrees with respect to the reference carrier phase.

  As soon as phase synchronization is completed between the signal received from the transmitter and the signal held on the receiving side by the separate transmission / reception synchronization, the reference signal generator 11 inverts the 0-degree shifted clock signal 21 and 180. A degree shift clock signal 22 is generated.

  Further, as shown in FIG. 2, the 0-degree shift clock signal 21 and the 180-degree shift clock signal 22 are switched within the data symbol period T1 in correspondence with the timing specified by the serialized clock signal 23 to obtain the reference signal 24. Output. Any of the switching orders may be first, but here, the 0-degree shift clock signal 21 is selected in the first half of the data symbol period T1, and is shifted 180 degrees in the second half (T2) of the data symbol period T1. The clock signal 22 is selected as the reference signal 24. Note that it is not always necessary that the clock allocation times of both are equally distributed within one data symbol.

  Next, the reference signal 24 is input to the comparator 12 together with the received signal 25 received. The comparator 12 compares the magnitude of the signal value between the reference signal 24 and the received signal 25 in accordance with the timing relationship defined by the comparison clock signal 26 such as the clock rising position, and outputs a digital value as the comparison result signal 27. To do. This comparison result signal 27 is sent to the decoder 13, and while the serialized clock signal 23 supplies the 0 degree shift clock signal 21 to the comparator 12 as the reference signal 24, a majority decision is made between the comparison results. To reduce the influence of noise and the like mixed instantaneously. The result of the calculation is held until the comparison result by the next 180-degree shift clock signal 22 is obtained. In addition, while the serialized clock signal 23 switches the selector 14 and supplies the 180-degree shifted clock signal 22 to the comparator 12, the majority processing and other processes in the decoder 13 are similarly performed on the comparison result signal 27. . Here, after the comparison result for the 180 degree shift clock signal 22 is obtained, the result obtained while the 0 degree shift clock signal 21 is selected and the 180 degree shift clock signal 22 is selected. The obtained result is compared in the decoder 13. In the data symbol period T1, the decoder 13 outputs the digital baseband data “0” as soon as it is determined that the phase of the received signal 24 is the same as that of the 180-degree shifted clock signal 22.

  Next, the operation when demodulating the QPSK signal in the configuration of the present embodiment will be described. Here again, as soon as phase synchronization is completed between the signal received from the transmitter and the signal held on the receiving side by separate transmission / reception synchronization, the timing relationship defined by the serialized clock signal 23 in the reference signal generator 11 is established. Correspondingly, in addition to the 0 degree shift clock signal 21 and the 180 degree shift clock signal 22 shown in FIG. To do. The order of this switching is not limited to which one is the same as in the case of the BPSK demodulation described above. Further, it is not necessary that the allocation time of the four clock signals is equally distributed in the data symbol.

  The reference signal 24 output here is input to the comparator 12 together with the reception signal 25, and in the same way as in BPSK, according to the comparison clock signal 26, a 0 degree shift clock signal, a 90 degree shift clock signal, a 180 degree shift clock signal, The respective signals of the 270 degree shifted clock signal and the waveform of the received signal 25 are sequentially compared, and the digital baseband data is output from the decoder 13 based on the clock signal having the matched waveform.

  As described above, the demodulator circuit of this embodiment can be used as both demodulator circuits by changing the reference signal 24 generated by the reference signal generator 11 from BPSK to QPSK without changing the configuration of the demodulator. Furthermore, a multilevel signal exceeding QPSK, for example, 8PSK, can be operated as a demodulator in the same manner without changing the configuration of the demodulator of the present invention only by increasing the number of shift clock signals to 8. it is obvious.

  According to this embodiment, the number of comparators can be reduced to one as compared with the prior art. Therefore, the circuit area can be reduced and the power consumption can be reduced. In addition, the demodulator configuration of this embodiment can demodulate BPSK, QPSK, or higher multilevel PSK signals. Therefore, as far as phase modulation is concerned, it is possible to cope with various communication systems on the same photomask and the same LSI.

  However, in the case of the demodulator of this embodiment, it is necessary to finish the comparison operation for each shift clock signal within a period of 1 / N of one data symbol. Therefore, Eb / No (energy per bit) is 1 / N of the conventional one, and the demodulation error rate and interference wave resistance tend to deteriorate. For this reason, it is a method suitable for a short-distance or a communication environment with few interference waves.

  FIG. 3 is a block diagram showing the configuration of the demodulator according to the second embodiment of the present invention. 3, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted. The demodulator according to the second embodiment includes a phase detector, a charge pump, and an AD converter 15 instead of the comparator 12 of FIG.

  The reception signal 25 and the reference signal 24 are input to the phase detector / charge pump / AD converter 15. Here, the phase difference between the reception signal 25 and the reference signal 24 in the phase detector and the charge pump is converted into a DC value and output from the charge pump. An example of the configuration of the phase detector / charge pump is referred to in Reference 1 and the like.

  The DC value output from the charge pump is input to the AD converter, and the AD converter converts the input DC value into a digital value and outputs it as a comparison result signal 27a to the subsequent decoder 13a. In the decoder 13a, the phase difference between the received signal 25 and the reference signal 24 is smaller when the comparison result signal 27a is smaller between the comparison with the 0 degree shift clock signal 21 and the comparison with the 180 degree shift clock signal 22. This means that the waveform is matched. Then, the data corresponding to the clock signal determined to be coincident is demodulated and output as digital baseband data.

  If the reference signal generator 11 outputs QPSK instead of BPSK and further multilevel PSK signal and compares the waveform with the received signal 25, multilevel PSK demodulation can be performed without changing the configuration of the demodulator of this embodiment. This is the same as in the first embodiment.

  As described above, according to the demodulator of the present embodiment, the phase difference is temporarily extracted as a continuous analog value in the phase detector / charge pump, and therefore an AD converter is required unlike the first embodiment. This is disadvantageous in terms of LSI cost and power consumption. However, a DC value is input to the AD converter, and there is no need to AD convert a signal having a certain frequency occupation bandwidth like a PSK modulation signal. For this reason, an increase in power consumption caused by the AD converter can be suppressed.

  It should be noted that the embodiments and examples can be changed and adjusted within the scope of the entire disclosure (including claims) of the present invention and based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (4)

A demodulator that demodulates a received signal that is N-valued (N is an integer of 2 or more) phase-modulated,
N phase shift clocks having the same frequency as the carrier wave related to the received signal and corresponding to each of the N values are serialized within one data symbol period using a predetermined serialized clock signal, A reference signal generator for outputting the converted signal as a reference signal;
A comparator for comparing the received signal and the reference signal;
Based on the comparison result of the comparator definitive to the one data symbol within a period, a decoder for outputting a digital baseband data values corresponding to the position phase of the reference signal that is closest to the phase difference between the received signal ,
A demodulator.   2. The demodulator according to claim 1, wherein the comparator converts a phase difference between the received signal and the reference signal into a DC value and outputs the DC value as a digital value when comparing the received signal with the reference signal. .   The reference signal generator includes a selector that switches a signal that has been phase-modulated corresponding to all of the N values within one data symbol period in accordance with a timing specified by the serialized clock signal and outputs the signal as the reference signal. The demodulator according to claim 1, comprising: a demodulator. A method for demodulating an N-value (N is an integer of 2 or more) phase modulated reception signal,
N phase shift clocks having the same frequency as the carrier wave related to the received signal and corresponding to each of the N values are serialized within one data symbol period using a predetermined serialized clock signal, Outputting the converted signal as a reference signal ;
Comparing the received signal with the reference signal;
And outputting the digital baseband data value on the basis of the said comparison results definitive in one data symbol period, corresponds to the position phase of the reference signal that is closest to the phase difference of the received signal,
The demodulation method characterized by including.

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