JP2004165988A - Digital quadrature demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital quadrature demodulator which has less fixed deterioration and has advantageous power consumption, a circuit scale and a price in high speed signal transmission. <P>SOLUTION: The demodulator includes A/D converters 100, 110 for receiving intermediate frequency signals and quantizing them with clock signals 20, 21 each having a frequency S/T and a phase difference of T/2S; an interpolation circuit 210 for compensating for an error from an ideal time point of the quantization timing of the A/D converter 110; a delay circuit 200 for delaying the output of the A/D converter 100 by the processing time of the interpolation circuit 210; a sign inverting circuit 300 for inverting the output of the delay circuit 200; a sign inverting circuit 310 for inverting the output of the interpolation circuit 210; and a selection circuit 400 for distributing the output of the delay circuit 200, the output of the interpolation circuit 210, and outputs of the sign inverting circuits 300, 310 to an in-phase output 50 or a quadrature output 60. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital quadrature demodulator in a receiver for high-speed digital signal transmission.
[0002]
[Prior art]
In signal transmission by a digital modulation method such as QPSK (Quadrature Phase Shift Keying) or multi-level QAM (Quadrature Amplitude Modulation), two signals (in-phase and quadrature) in which received signals are orthogonalized are used. A quadrature demodulator for separating the signals into orthogonal channel components and outputting them as baseband signals is required. The quadrature demodulator can be configured by (1) a method of obtaining a baseband signal using an analog quadrature demodulator, (2) performing A / D conversion on the received signal, and implementing quadrature demodulation by digital signal processing. Method. In the case of heterodyne reception, a received RF signal is input to a quadrature demodulation circuit after band limitation and level adjustment, frequency conversion to an IF (intermediate frequency) frequency.
[0003]
FIG. 7 shows a circuit configuration according to the prior art (1) described above. The analog quadrature demodulator 800 receives the received signal 10 and the reference carrier (cos ω) supplied from the carrier input 30. _c t) and a signal (sin ω) delayed by 90 degrees in phase by the π / 2 phase shifter 860. _c t) is input. The analog quadrature demodulator 800 is composed of a power divider and an analog multiplier. The input received signal is divided into two by the power divider and then multiplied by carrier waves having a phase shift of 90 degrees. Since the output of the analog quadrature demodulator 800 contains a frequency component twice as high as the IF frequency, unnecessary harmonic components are removed by the low-pass filters 810 and 820. The two systems of signals thus obtained are baseband signals modulated by independent data sequences (in-phase and quadrature channels). This low-pass filter output is subjected to signal processing such as band limitation and identification. However, these are rarely realized by analog signal processing, and are quantized by A / D converters 830 and 840 as shown in FIG. And is often realized by digital signal processing.
[0004]
The above-described low-pass filters 810 and 820 need to be designed to sufficiently suppress a frequency component equal to or more than １ ／ of the sampling frequency so that aliasing does not occur in subsequent A / D converters 830 and 840. The original digital data sequence transmitted is reproduced by subjecting the A / D converted baseband signals 50 and 60 to band limitation and identification as described above.
[0005]
FIG. 8 shows a circuit configuration according to the prior art (2) described above. The IF signal 10 after passing through the low-pass filter is quantized by the A / D converter 850. The difference from the previous example is that demodulation signal processing such as quadrature demodulation, band limitation, identification, and the like are all realized by digital signal processing. Describing the quadrature demodulation processing, the carrier is a two-system digital data sequence read from the sine wave table 880, and the multiplication with the received signal is realized by the digital multiplication circuit 870.
[0006]
If the IF frequency is selected to be 4N (where N is a natural number and the number of oversamples S = 2N) times the symbol transmission rate of the baseband signal, a quadrature demodulator can be realized with a simple configuration as shown in FIG. 1 or Non-Patent Document 1. Hereinafter, the case of N = 1 will be described.
[0007]
FIG. 10 is a diagram showing carrier phase states and input / output signals in the digital quadrature demodulator described in Patent Document 1 or Non-Patent Document 1. Since the carrier frequency is １ ／ of the clock frequency, if carrier synchronization and timing synchronization are both established, cos ω at the time of quantization of the A / D converter (the time indicated by the vertical dotted line in FIG. 10). _c t and sin ω _c The value of t is
(Cosω _c t, sinω _c t) = (1,0), (0,1), (-1,0), (0, -1)
It becomes. Note that “0” in the in-phase / quadrature channel outputs 50 and 60 in FIG. 10 indicates that “0” is output, and the hatched portion indicates the output of the A / D converter 850 in FIG. 320 indicates that the output is inverted. Therefore, as apparent from FIG. 10, the multiplication of the received signal (A / D converter output) and the carrier can be realized by the sign inverting circuit 320, the selecting circuit 420, and the control circuit 450 for controlling the selecting circuit 420. .
[0008]
On the other hand, studies have been made on increasing the speed of the A / D converter itself. Non-Patent Documents 2 and 3 propose a method of increasing the operation speed of the A / D converter by using a plurality of A / D converters with a circuit configuration shown in FIG. A Time-Interleaved ADC that operates D converters in parallel has been reported. FIG. 11 is a circuit example when four A / D converters are operated in parallel. The input signal is held by sample and hold circuits 900 to 930, and a four-phase clock φ having a different phase by T / 4 (T is a clock cycle). ₁ ~ Φ ₄ Is quantized by The outputs of the four A / D converters 940 to 970 are sequentially switched and output by the selection circuit 980. For this reason, the operating speed of each A / D converter is reduced to 1/4 that of a single A / D converter.
[0009]
In this circuit configuration, the outputs of the plurality of A / D converters 940 to 970 are multiplexed and operated as one A / D converter. A signal spectrum which does not originally exist is generated as an image due to a sample timing error (hereinafter, timing error) due to a phase error of a supplied clock and an offset voltage and a gain of a supplied clock. Therefore, a compensation circuit and a calibration method have been proposed for each factor.
[0010]
[Patent Document 1] JP-A-6-244890 (page 2).
[0011]
[Non-patent Document 1] Okada, Shirato, "All-digital Multilevel Demodulator for Large-Capacity Digital Wireless Systems," IEEE GLOBECOM '93, 1993, Vol. 1, pp. 609-613, (T. Okada, T. Shirato, "A Fully Digitized Multi-level Demodulator for High-capacity Digital Radio Systems", IEEE GLOBECOM '93, vol.
[0012]
[Non-patent document 2]
Hohenjim, Edward KF Lee, "Digital Calibration Techniques for Minimizing Timing Errors in Time-Interleaved ADCs," IEEE Trans. Circuits and Systems II, July 2001, Vol. 47, No. 7, pp. 603-613 (Huawen Jin, Edward K. F. Lee, Infra-Technical Information Technology Association, Canada). 's, IEEE Trans. Circuits and Systems II, vol.47, No.7, pp.603-613, July 2001).
[0013]
[Non-Patent Document 3]
Shafiq M. Jamal, Daihofu, Paul J. Hearst, Stephen H. Lewis, "10b 120 MSample / s Time-Interleaved Analog-to-Digital Converter with Digital Calibration", IEEE ISSCC 2002, February 2002, pp. 172-173 (Shafiq M. Jamal). , Daihong Fu, Paul J. Hurst, Stephen H. Lewis, "A 10b 120 MSample / s Time-Interleaved Analog-to-Digital Converter with The Digital Bucket, 2nd ed., August 17, 2002.
[0014]
[Problems to be solved by the invention]
When an analog quadrature demodulator is used, it is widely known that there are deterioration factors due to hardware imperfections, such as a gain error between in-phase and quadrature outputs, a quadrature error, and a DC offset. In particular, when multi-level QAM is used, as the number of multi-levels increases, the characteristic degradation due to these factors increases, and the bit error rate deteriorates even at the same carrier-to-noise power ratio. In order to realize an analog quadrature demodulator in which these deterioration factors are small, it is necessary to select balanced components or individually fine-tune the circuit, so that the price is high.
[0015]
On the other hand, in the method of performing A / D conversion on a received signal after frequency conversion (IF frequency) and implementing quadrature demodulation by digital signal processing, the influence of the above-described deterioration factor is different from that of the analog quadrature demodulator. Very small in comparison. On the other hand, this method requires a high-speed A / D converter that operates at a sampling rate four times or more the symbol transmission rate. When the bit transmission rate is on the order of several 100 Mbit / s (symbol transmission rate is several tens Mbaud), the sampling rate of the A / D converter exceeds 100 MHz, and the restrictions on the A / D converter become severe.
[0016]
That is, even if there is a device that can be used in terms of the operating speed and the number of output bits, the power consumption of the A / D converter is enormous because of the high price and the high sampling speed. In addition, in the case of 8 to 10-bit A / D converters that are usually used for wireless applications, most products that operate at about 100 MHz or less consume 100 to 200 mW, but can operate at speeds higher than this. In many products, the power consumption often reaches several watts. It is expected that these will be improved in the future due to advances in device manufacturing technology, but for the time being it is necessary to solve these problems by some method.
[0017]
Also, in a high-speed A / D converter realized by using the method of Non-Patent Documents 2 and 3, compensation signal processing must be realized inside the A / D converter, and the processing is generally complicated. There are disadvantages. For example, Non-Patent Document 2 proposes a method of performing a compensation process for a gain error and a timing error offline using a known reference signal. The reference signal required here is a periodic signal such as a sine wave or a triangular wave. However, since high accuracy regarding the cycle and the waveform is required, it is necessary to incorporate a high-precision reference signal generation circuit.
[0018]
In Non-Patent Document 3, in order to equalize the positive and negative appearance probabilities in the output of each A / D converter regardless of the input signal for DC offset compensation, a pseudo-random number sequence is once applied to each A / D conversion output. Has been proposed to perform DC offset compensation after randomization and then multiply again by the same pseudo-random number sequence to restore the original signal. All of the above-mentioned methods have a heavy load on mounting, and are not suitable for application to an application as a quadrature demodulator.
[0019]
In view of the above, the present invention has a performance applicable to multi-valued QAM, has a small fixed degradation in high-speed signal transmission with a bit transmission rate of the order of 100 Mbit / s, and is advantageous in terms of power consumption, circuit scale, and price. It is an object to provide a quadrature demodulator.
[0020]
[Means for Solving the Problems]
The invention according to claim 1 is a digital quadrature demodulator which receives a received signal whose frequency has been converted to an intermediate frequency, wherein the sampling frequency is S / T (S is the number of oversamples, T is A first A / D converter that performs quantization with a first clock (symbol period), receives the received signal, has a sampling frequency of S / T, and has a phase of T / 2S with respect to the first clock. A second A / D converter that performs quantization with a different second clock, and is connected to one output side of the first and second A / D converters, from an ideal time point of the quantization timing. An interpolation circuit for compensating for the error of the interpolation circuit; a delay circuit connected to the other output side of the first and second A / D converters for delaying a signal by a processing delay time of the interpolation circuit; The second connected to the output side of the circuit A sign inversion circuit, a second sign inversion circuit connected to the output side of the delay circuit, an output side of the interpolation circuit, an output side of the delay circuit, and outputs of the first and second sign inversion circuits. And a selection circuit connected to the input side and having first and second outputs, an output of the interpolation circuit, an output of the delay circuit, an output of the first sign inversion circuit, and the second sign inversion circuit. A first control circuit for controlling the selection circuit so that the output of the selection circuit is periodically distributed to the first or second output; and a quantization timing for inputting the first and second outputs of the selection circuit. And a second control circuit for detecting the error of the interpolation circuit and controlling the interpolation circuit.
[0021]
According to a second aspect of the present invention, there is provided a digital quadrature demodulator which receives a reception signal whose frequency has been converted to an intermediate frequency, wherein the reception signal is input and the sampling frequency is S / T (S is the number of oversamples, T is A first A / D converter that performs quantization with a first clock (symbol period), receives the received signal, has a sampling frequency of S / T, and has a phase of T / 2S with respect to the first clock. A second A / D converter that performs quantization with a different second clock, and is connected to one output side of the first and second A / D converters, from an ideal time point of the quantization timing. An interpolation circuit for compensating for the error of the interpolation circuit; a delay circuit connected to the other output side of the first and second A / D converters for delaying a signal by a processing delay time of the interpolation circuit; Circuit output and the delay circuit A multiplexing circuit for time-multiplexing two systems of signals into one system signal, a sign inversion circuit connected to an output side of the multiplexing circuit, an output side of the interpolation circuit, and an output of the sign inversion circuit. A selection circuit having a first side connected to an input side and having first and second outputs, and a selector for periodically distributing an output of the multiplexing circuit and an output of the sign inverting circuit to the first or second output. A first control circuit for controlling the selection circuit, and a second control circuit for receiving the first and second outputs of the selection circuit, detecting a quantization timing error, and controlling the interpolation circuit. A digital quadrature demodulator characterized by comprising:
[0022]
According to a third aspect of the present invention, in the digital quadrature demodulator according to the first or second aspect, an average value calculation circuit for calculating an average value of the input signal, and an output of the average value calculation circuit is subtracted from the input signal. A first DC offset compensation circuit comprising a subtraction circuit, inserted between the one of the first and second A / D converters and the interpolation circuit; A digital quadrature demodulator characterized in that a second DC offset compensating circuit having the same configuration as that described above is inserted between the other of the first and second A / D converters and the delay circuit.
[0023]
According to a fourth aspect of the present invention, in the digital quadrature demodulator according to the third aspect, an average power calculation circuit for calculating a root-mean-square value of the input signal, and an output of the average power calculation circuit and a desired value of the average power. A first gain compensating circuit including a gain setting circuit for calculating a ratio of the first DC power and a multiplying circuit for multiplying an output of the gain setting circuit by an input signal to the average power calculating circuit. A second gain compensation circuit having the same configuration as that of the first gain compensation circuit is inserted between the offset compensation circuit and the interpolation circuit, and is inserted between the second DC offset compensation circuit and the delay circuit. A digital quadrature demodulator characterized by this.
[0024]
According to a fifth aspect of the present invention, in the digital quadrature demodulator according to the first, second, third or fourth aspect, the delay circuit is replaced with another interpolation circuit for compensating an error from an ideal time point of the quantization timing. A digital quadrature demodulator characterized in that the other interpolation circuit is controlled by the second control circuit.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
In the invention according to claim 1, in a digital quadrature demodulator that digitally performs quadrature demodulation on an IF signal after A / D conversion, two A / D converters are operated in parallel. The orthogonal demodulation processing itself is realized by a sign inversion circuit and a selection circuit arranged in two systems corresponding to two A / D converters. As reported in Non-Patent Document 2 and Non-Patent Document 3, when a timing error exists, an orthogonality error occurs and orthogonal inter-channel interference occurs. In the invention according to Claim 1, however, an interpolation circuit is provided on one side. The arrangement (arranged on both sides in the invention according to claim 5) compensates for the timing error and prevents the characteristic deterioration. Note that a control index for controlling the interpolation circuit is supplied from a second control circuit that receives an output of the selection circuit as an input.
[0026]
According to the second aspect of the present invention, the quadrature demodulation processing itself is realized by a sign inverting circuit and a selecting circuit in the same manner as in the first aspect. However, two systems of signals corresponding to two A / D converters are time-multiplexed. Then, quadrature demodulation is realized by sign inversion and replacement after one system.
[0027]
In the invention according to claim 3, by operating two A / D converters in parallel, a DC offset error generated by the same mechanism as the interleaved ADC described in Non-Patent Documents 2 and 3 can be prevented. A DC offset compensating circuit composed of an average value calculating circuit for calculating an average value for each A / D converter output, and a subtraction circuit for subtracting the average value calculating circuit output from each A / D converter output. To equip it.
[0028]
In the invention according to claim 4, by operating two A / D converters in parallel, a gain error generated by the same mechanism as the interleaved ADC described in Non-Patent Documents 2 and 3 is prevented. An average power calculation circuit for calculating a root mean square value of an input signal, and a ratio between an output of the average power calculation circuit and a desired value of average power are provided at a stage subsequent to the DC offset compensation circuit according to claim 3. A gain compensating circuit comprising a gain setting circuit and a multiplying circuit for multiplying the output of the gain setting circuit by an input signal is provided.
[0029]
As described above, in the digital quadrature demodulator that digitally performs quadrature demodulation on the IF signal after A / D conversion, high-speed signal transmission on the order of several hundred Mbit / s (symbol transmission speed of several tens Mbaud) is performed. If the target is used, quantization must be performed at a rate of 4N times the symbol transmission rate in the methods of Patent Document 1 and Non-Patent Document 1, but in the present invention, two A / D converters are operated in parallel. Accordingly, the operating speed per A / D converter can be suppressed to at most about 100 MHz. For this reason, as described above, it is possible to use an A / D converter that can be easily obtained at low power consumption and at low cost.
[0030]
On the other hand, when the above-described interleaved A / D converter is applied to a quadrature demodulator, if the number of A / D converters used exceeds two, the outputs of a plurality of A / D converters are output to one system. Are mixed, it becomes difficult to compensate for a gain error and a DC offset. On the other hand, in the present invention, similar gain errors and DC offsets become apparent, but since the number of A / D converters is two, the output of one A / D converter is only the in-phase channel. The output of the other A / D converter appears only in the orthogonal channel. Therefore, it is possible to easily compensate by arranging a compensation circuit for the gain error and the DC offset for each channel (in-phase / quadrature channel).
[0031]
Here, the factor of characteristic deterioration in the present invention will be considered. Since the deterioration factors accompanying the digital signal processing for realizing the quadrature demodulation can be neglected, the characteristic deterioration in the present invention includes (1) a timing error caused by a phase error of a two-phase clock, and (2) a plurality of A / Ds. This is due to individual differences in device (A / D converter) characteristics due to the use of the converter.
[0032]
In the inventions according to the first, second and fifth aspects, the former deterioration factor, that is, the timing error caused by the clock phase error is compensated by using an interpolation circuit. The signal information (amplitude, phase) at the "true sample time" is reproduced by performing interpolation on the preceding and following samples based on the output of the selection circuit, that is, the timing error information detected from the output of the quadrature demodulator of the present invention. Is done. The output of the control circuit for controlling the interpolation circuit is designed to exhibit an S-shaped input / output characteristic as shown in FIG. 6 with respect to the timing error. Thus, if the timing error is within the pull-in range (−Δ to + Δ), the timing error can be compensated by using the output of the control circuit as a control index of the above-described interpolation circuit.
[0033]
Considering the latter deterioration factor, considering the manufacturing accuracy of the A / D converter (both the gain error and the DC offset are about several% of the input full scale), the influence thereof is lower than when the analog quadrature demodulator is used. Is very small. For this reason, the characteristic deterioration in BPSK and QPSK is negligible, and the invention according to claims 1 and 2 does not include a compensation circuit for the latter deterioration factor. When QAM is applied, a characteristic deterioration compensation circuit is used as necessary. Therefore, the invention according to claims 3 and 4 includes a DC offset compensation circuit and a gain compensation circuit sequentially.
[0034]
[First Embodiment]
FIG. 1 shows a circuit configuration of an embodiment of the invention according to claim 1, and FIG. 2 shows a timing chart of the operation. Assuming Nyquist sampling (S = 2, S is the number of oversamples), the IF reception signal input from the reception signal input 10 has a sampling frequency of two A / D converters 100 and 110 connected in parallel. The quantization is performed by two-phase clocks 20 and 21 at 2 / T (T is a symbol period) and the phases are different by T / 4.
[0035]
It is assumed that there is no error in the phase of the clock 20 of the A / D converter 100 whose output appears on the in-phase channel, and there is a phase error in the clock 21 of the A / D converter 110 whose output appears on the quadrature channel.
[0036]
In this case, an interpolation circuit 210 for timing compensation is arranged at a stage subsequent to the A / D converter 110, and a delay circuit 200 for adjusting a delay by inserting the interpolation circuit 210 is provided at the output of the A / D converter 100. Is connected. Outputs of the interpolation circuit 210 and the delay circuit 200 are connected to sign inversion circuits 300 and 310 and a selection circuit 400, respectively. As in the case of the aforementioned Patent Document 1 and Non-Patent Document 1, the multiplication of the received signal and the carrier is realized by the sign inverting circuits 300 and 310, the selecting circuit 400, and the control circuit 450 as shown in FIG. You. For simplicity of explanation, the delay time in the interpolation circuit 210 and the delay circuit 200 is ignored in FIG. 2, and the outputs of the A / D converters 100 and 110 are sent to the sign inversion circuits 300 and 310 and the selection circuit 400 without delay. It was assumed to be entered.
[0037]
If carrier synchronization and timing synchronization are both established, cosω at the time of quantization by the A / D converters 100 and 110 (at the time indicated by the vertical dotted line in FIG. 2). _c t and sin ω _c The value of t is
(Cosω _c t, sinω _c t) = (1,0), (0,1), (-1,0), (0, -1)
It becomes. Note that "0" in the in-phase / quadrature channel outputs 50 and 60 in FIG. 2 indicates that "0" is output, and the hatched portion indicates that the sign of the output of the A / D converter is inverted. It is shown that.
[0038]
The control circuit 450 causes the selection circuit 400 to operate as follows. Assuming that the leftmost point in FIG. 2 is a starting point, first the output of the delay circuit 200 is selected for the in-phase output 50, then “0” is output, then the output of the sign inversion circuit 300 is selected, and then "0" is output, and this is repeated periodically thereafter. Similarly, first, "0" is output to the quadrature output 60, then the output of the interpolation circuit 210 is selected, then "0" is output, and then the output of the sign inversion circuit 310 is selected. Repeat periodically.
[0039]
The control circuit 500 for the interpolation circuit 210 detects a timing error from the output of the selection circuit 400, that is, the output of the present digital quadrature demodulator, and returns timing error information to the interpolation circuit 210. Timing error information of ± 0 to 1T is input to the control signal input of the interpolation circuit 210, and the signal information (amplitude and phase) at the “true quantization time point” is reproduced by interpolation from previous and subsequent samples.
[0040]
When applying any of the digital quadrature demodulators of the present invention, no special technique relating to carrier synchronization and timing synchronization is required, and the conventional method can be applied as it is. The digital quadrature demodulator of the present invention is also applicable to quasi-synchronous detection. In this case, an AFC (Auto Frequency Control Circuit) or an APC (Auto Phase Control Circuit) is provided at a subsequent stage. Is arranged.
[0041]
[Second embodiment]
FIG. 3 shows a circuit configuration according to an embodiment of the present invention. In this embodiment, the output of the delay circuit 200 and the output of the interpolation circuit 210 are time-multiplexed by the multiplexing circuit 410 in the embodiment of the invention according to claim 1 shown in FIG. This is a reduction in the number of circuit inputs. In this case, the outputs of the A / D converters 100 and 110 are alternately output from the multiplexing circuit 410 as shown in the time chart of FIG.
[0042]
By the control circuit 450, the selection circuit 420 selects, for example, the output of the delay circuit 200 output from the multiplexing circuit 410 as the in-phase output 50, and then outputs the output of the interpolation circuit 210 output from the multiplexing circuit 410 to the quadrature output 60. And then selects an output obtained by inverting the output of the delay circuit 200 output from the multiplexing circuit 410 to the in-phase output 50 by the sign inverting circuit 320, and then outputs the quadrature output 60 from the multiplexing circuit 410 to the interpolation circuit 210. Is selected by the sign inverting circuit 320, and then the output of the delay circuit 200 output from the multiplexing circuit 410 is selected as the in-phase output 50. This is repeated periodically thereafter.
[0043]
Therefore, the number of circuits is reduced, but the operation speed is doubled, and the sign inverting circuit 320 and the selecting circuit 420 need to be speeded up.
[0044]
[Third Embodiment]
FIG. 4 shows a circuit configuration according to an embodiment of the present invention. This embodiment shows an example of a circuit configuration in which a DC offset compensation circuit is added to the digital quadrature demodulator according to the first aspect. The DC offset compensating circuit is disposed immediately after each of the A / D converters 100 and 110 so as not to affect the compensating circuit for other deterioration factors. The DC offset compensation circuit 610 includes an average value calculation circuit 650 and a subtraction circuit 660. The DC offset compensation circuit 610 has the same configuration. In the present invention, since the received signal is a modulated signal having the IF frequency as the center frequency, it is considered that the output of each of the A / D converters 100 and 110 has a random (equal probability) sign regardless of the transmission data sequence. Can be Therefore, there is no need to multiply the received signal input by a pseudo-random number sequence and randomize it as in Non-Patent Document 3 described above.
[0045]
[Fourth embodiment]
FIG. 5 shows a circuit configuration according to an embodiment of the present invention. This embodiment shows an example of a circuit configuration in which a DC offset compensation circuit and a gain compensation circuit are added to the digital quadrature demodulator according to the first embodiment. Since the gain compensation circuits 700 and 710 are affected by the DC offset, they are arranged after the DC offset compensation circuits 600 and 610. The gain compensating circuit 710 compares the average power calculating circuit 750 for calculating the average power and the output of the average power calculating circuit 750 with a predetermined specified power value, and sets the gain so that the output becomes a predetermined power value. And a multiplication circuit 770 that performs amplification (multiplication) based on the set gain. The gain compensation circuit 700 has the same configuration.
[0046]
[Other embodiments]
In the above description, the interpolation circuit 210 is inserted into only one channel. However, the interpolation circuit 210 is inserted into both channels so that the error from the ideal timing of the quantization timing of each channel is compensated by the control circuit 500. You may comprise. In this case, if the processing delays of the interpolation circuits of both channels are the same, the delay circuit 200 is not required.
[0047]
【The invention's effect】
According to the first to fifth aspects of the present invention, a digital quadrature demodulator applicable to high-speed signal transmission of the order of several hundred Mbit / s using multi-valued QAM can be used at low power consumption and at low cost. This can be realized using a D converter.
[0048]
Also, by digitizing all signal processing of the quadrature demodulator, it is inserted into a VCO (Voltage Controlled Oscillator) for generating and distributing a local oscillation signal required by the analog quadrature demodulator, a hybrid, and an in-phase / quadrature channel. Since an analog low-pass filter or the like to be used becomes unnecessary, the number of analog parts can be significantly reduced. This is a great merit considering that the number of A / D converters and the operation speed are the same as those when the analog quadrature demodulator is used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration of a digital quadrature demodulator according to an embodiment of the present invention.
FIG. 2 is an operation timing chart of the digital quadrature demodulator according to the embodiment of the present invention;
FIG. 3 is a block diagram showing a circuit configuration of a digital quadrature demodulator according to an embodiment of the present invention.
FIG. 4 is a block diagram showing a circuit configuration of a digital quadrature demodulator according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a circuit configuration of a digital quadrature demodulator according to an embodiment of the present invention.
FIG. 6 is an input / output characteristic diagram of a second control circuit of the digital quadrature demodulator according to the first and second embodiments of the present invention;
FIG. 7 is a block diagram showing a circuit configuration when a conventional analog quadrature demodulator is used.
FIG. 8 is a block diagram showing a circuit configuration of a quadrature demodulator using a conventional digital multiplier.
FIG. 9 is a block diagram showing a circuit configuration of a conventional digital quadrature demodulator described in Patent Document 1 and Non-Patent Document 1.
FIG. 10 is an operation timing chart of the conventional digital quadrature demodulator described in Patent Document 1 and Non-Patent Document 1.
FIG. 11 is a block diagram showing a circuit configuration of a conventional A / D converter (Time-Interleaved A / D converter) described in Non-Patent Document 2.
[Explanation of symbols]
10: IF reception signal input
20 to 23: Clock input
30: Carrier input
40: A / D converter input
50: Quadrature demodulator in-phase output
60: Quadrature demodulator quadrature output
70: A / D converter output
100, 110, 830 to 850, 940 to 970: A / D converter
200: delay circuit
210: interpolation circuit
300, 310, 320: sign inversion circuit
400, 420: selection circuit
410: Multiplexing circuit
450: Control circuit (for selection circuit)
500: Control circuit (for interpolation circuit)
600, 610: DC offset compensation circuit
650: Average value calculation circuit
660: Subtraction circuit
700, 710: gain compensation circuit
750: Average power calculation circuit
760: gain setting circuit
770: Multiplication circuit
800: analog quadrature demodulator
810, 820: Low-pass filter
860: π / 2 phase shift circuit
870: Quadrature demodulator using digital multiplier
880: Sine wave table
900 to 930: sample and hold circuit
980: Selection circuit (for Time-Interleaved A / D converter)
990: Control circuit (for Time-Interleaved A / D converter)

Claims (5)

A digital quadrature demodulator that receives a received signal whose frequency has been converted to an intermediate frequency,
A first A / D converter that receives the received signal and performs quantization with a first clock whose sampling frequency is S / T (S is the number of oversamples, T is a symbol period);
A second A / D converter that receives the received signal, performs a quantization with a second clock having a sampling frequency of S / T and a phase different from the first clock by T / 2S,
An interpolation circuit connected to one output side of the first and second A / D converters and compensating for an error of the quantization timing from an ideal time;
A delay circuit connected to the other output side of the first and second A / D converters and delaying a signal by a processing delay time of the interpolation circuit;
A first sign inversion circuit connected to an output side of the interpolation circuit;
A second sign inverting circuit connected to an output side of the delay circuit;
A selection circuit having an output side of the interpolation circuit, an output side of the delay circuit, and an output side of the first and second sign inversion circuits respectively connected to an input side and having first and second outputs;
The selection circuit for periodically distributing an output of the interpolation circuit, an output of the delay circuit, an output of the first sign inversion circuit, and an output of the second sign inversion circuit to the first or second output. A first control circuit for controlling
A second control circuit that receives the first and second outputs of the selection circuit, detects an error in quantization timing, and controls the interpolation circuit;
A digital quadrature demodulator characterized by comprising: A digital quadrature demodulator that receives a received signal whose frequency has been converted to an intermediate frequency,
A first A / D converter that receives the received signal and performs quantization with a first clock whose sampling frequency is S / T (S is the number of oversamples, T is a symbol period);
A second A / D converter that receives the received signal, performs a quantization with a second clock having a sampling frequency of S / T and a phase different from the first clock by T / 2S,
An interpolation circuit connected to one output side of the first and second A / D converters and compensating for an error of the quantization timing from an ideal time;
A delay circuit connected to the other output side of the first and second A / D converters and delaying a signal by a processing delay time of the interpolation circuit;
A multiplexing circuit that time-multiplexes two signals consisting of the output of the interpolation circuit and the output of the delay circuit into one signal;
A sign inversion circuit connected to an output side of the multiplexing circuit;
A selection circuit having an output side of the interpolation circuit and an output side of the sign inversion circuit connected to an input side and having first and second outputs;
A first control circuit that controls the selection circuit so as to periodically distribute the output of the multiplexing circuit and the output of the sign inversion circuit to the first or second output;
A second control circuit that receives the first and second outputs of the selection circuit, detects an error in quantization timing, and controls the interpolation circuit;
A digital quadrature demodulator characterized by comprising: The digital quadrature demodulator according to claim 1 or 2,
A first DC offset compensation circuit comprising an average value calculation circuit for calculating an average value of an input signal and a subtraction circuit for subtracting the output of the average value calculation circuit from the input signal; Inserted between the one of the A / D converters and the interpolation circuit;
A second DC offset compensation circuit having the same configuration as the first DC offset compensation circuit is inserted between the other one of the first and second A / D converters and the delay circuit. Digital quadrature demodulator. The digital quadrature demodulator according to claim 3,
An average power calculation circuit for calculating a mean square value of an input signal; a gain setting circuit for calculating a ratio of an output of the average power calculation circuit to a desired value of the average power; and an output of the gain setting circuit for calculating the average value. Inserting a first gain compensation circuit composed of a multiplication circuit that multiplies the input signal to the power calculation circuit between the first DC offset compensation circuit and the interpolation circuit;
A digital quadrature demodulator characterized in that a second gain compensation circuit having the same configuration as the first gain compensation circuit is inserted between the second DC offset compensation circuit and the delay circuit. The digital quadrature demodulator according to claim 1, 2, 3, or 4,
The delay circuit is replaced with another interpolation circuit for compensating an error from an ideal point in time of quantization timing, and the another interpolation circuit is controlled by the second control circuit. Demodulator.

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