JP2006157652A - Reception apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception apparatus capable of A/D converting an I signal and a Q signal at optimal symbol timings. <P>SOLUTION: A quadrature demodulation unit 1 for analog outputting demodulates a quadrature modulated signal and outputs an I signal of an in-phase component and a Q signal of a quadrature component orthogonal with said in-phase component. An A/D converter 4 and an A/D converter 5 digitally convert the I signal and Q signal outputted via an LPF 2 and an LPF 3, respectively. A phase shifter 7 and a phase shifter 8 independently output A/D converted clocks to the A/D converter 4 and the A/D converter 5, respectively based on phase data from a phase data setting unit 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reception technique for receiving a quadrature modulation signal.

  The receiver of the digital high-speed wireless communication apparatus reproduces the clock timing of analog-to-digital conversion (hereinafter referred to as A / D conversion) for converting the received signal from an analog signal to a digital signal in order to decode the digital data without error. It has a mechanism to adjust. In the reception process, the quadrature-modulated IF signal is demodulated into a baseband signal having an in-phase component (hereinafter referred to as I signal) and a quadrature component (hereinafter referred to as Q signal), and then A / D conversion clock frequency by the LPF. A higher harmonic component higher than the Nyquist frequency or an unnecessary adjacent channel component is removed, A / D conversion is performed, and decoding is performed by digital processing.

  Conventionally, as a means for reproducing A / D conversion clock timing, a symbol point is extracted from an A / D converted I / Q signal so that the square sum of the I / Q signal is maximized, or a zero cross point is extracted. In order to minimize the sum of squares, a configuration is known in which the reference clock timing oscillating at a constant period is adjusted back and forth (see, for example, Patent Document 1).

  According to this clock timing recovery means, an optimum symbol identification point can be captured with an A / D conversion clock that is about 1 or 2 times the symbol rate, so that it can be applied to a high symbol rate, and a multilevel modulation system It is also applicable to.

  As a clock timing adjusting means, a reference clock is delayed by a plurality of delay circuits, and various types of clocks having different phases are prepared in parallel, and one of the clock groups is selected to select an A / D conversion clock. And the like are known (see, for example, Patent Document 2).

According to this clock timing adjustment means, (N−1) delay clock groups are generated in time y steps from time y to time y × (N−1), and one of the delay clock groups is selected. Select and output as a delayed clock.
JP 2000-69100 A (page 6, FIG. 1) JP-A-10-229423 (page 22, FIG. 7)

  However, since the clock timing recovery means or clock timing adjustment means described in Patent Document 1 and Patent Document 2 does not consider the time difference between I / Q, the sampling point of the I signal was optimal. However, the sampling point of the Q signal is shifted by the delay error between IQs, and there is a high possibility that the sampled I / Q signal is out of the desired symbol area and is identified as an erroneous symbol point.

  The present invention has been made in view of the above-described conventional circumstances, and an object of the present invention is to provide a receiving apparatus capable of performing A / D conversion at optimum symbol timing for each of an I signal and a Q signal. And

  The receiving apparatus of the present invention includes an analog output quadrature demodulator that demodulates a quadrature-modulated signal into an in-phase component I signal and a quadrature component Q signal that is orthogonal to the in-phase component, and the quadrature demodulator A first analog-digital converter for digitally converting the output I signal; a second analog-digital converter for digitally converting the Q signal output from the quadrature modulation unit; the first analog-digital converter; A clock output unit that outputs a conversion clock independently to the second analog-digital converter.

  With this configuration, by adjusting the A / D conversion clock for each of the I signal and the Q signal, the time difference between the I signal and the Q signal can be canceled and the A / D conversion can be performed at the optimum symbol timing. .

  In the receiving device of the present invention, the clock output unit includes an oscillator that generates a reference clock, and a delay that outputs the reference clock output from the oscillator to the first analog-digital converter. One phase shifter; a second phase shifter that delays the reference clock output from the oscillator and outputs the delayed reference clock to the second analog-digital converter; the first phase shifter; A phase data setting unit that individually outputs control data to the second phase shifter.

  With this configuration, the phase of the I signal and the Q signal can be adjusted using a phase shifter, and A / D conversion can be performed individually.

  Further, in the receiving device of the present invention, the phase data setting unit, for each of the first phase shifter and the second phase shifter, an offset value storage unit that stores a predetermined offset value; The offset value for the first phase shifter stored in the offset value storage unit and the I and Q signals output from the first analog-digital converter and the second analog-digital converter are decoded. A first adder that adds the common phase data that is the phase data of the received signal and outputs the result to the first phase shifter, and the second phase shifter stored in the offset value storage unit And a second adder that adds the offset value to the common phase data and outputs the sum to the second phase shifter.

  With this configuration, it is possible to adjust the clock timing of A / D conversion for a received signal that is dynamically converted.

  According to the present invention, it is possible to provide a receiving apparatus capable of performing A / D conversion at optimum symbol timing for each of an I signal and a Q signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, a receiver of a high-speed digital radio transmission apparatus will be described as an example of a receiving apparatus according to an embodiment of the present invention. In high-speed digital wireless transmission, when the operation speed or signal bandwidth exceeds a certain level at a high symbol rate, the orthogonal demodulator is an analog circuit due to device performance, cost, power consumption, etc. Generally, it is composed of

  Therefore, after quadrature demodulation, the demodulated in-phase component signal I signal and quadrature component signal Q signal pass through separate analog paths, and slightly between I / Q due to variations in circuit element characteristics. A time difference will occur.

  In particular, the LPF inserted to remove harmonic components before A / D conversion has a coil and a capacitor as the specified constituent elements, so that it originally has a large delay time and perfectly matches individual circuit characteristics. Can be the biggest cause of time difference between I / Q.

  On the other hand, as the symbol rate increases, the symbol period decreases, the ratio of the I / Q time difference to the symbol period increases, and in the case of multilevel modulation, the distance between adjacent symbol points is closer and the identification range is narrower. Therefore, the probability of erroneously identifying the symbol point is further increased.

  Therefore, the receiving apparatus according to the embodiment of the present invention cancels the time difference between the I / Q signals by individually adjusting the A / D conversion clocks for the I signal and the Q signal, respectively. In contrast, A / D conversion is realized at an optimal symbol timing.

  FIG. 1 is a block diagram showing a schematic configuration of a receiving apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, the receiving apparatus of the present embodiment is a quadrature component that is orthogonal to, for example, an I signal that is an in-phase component and an in-phase component of a quadrature-modulated received signal of an intermediate frequency (hereinafter referred to as IF). Quadrature demodulator 1 that demodulates to Q signal and outputs analog signal, low-pass filter (hereinafter referred to as LPF) 2 that removes unnecessary harmonic components from the orthogonally demodulated I signal, and unwanted harmonics from Q signal LPF 3 that removes components, an analog-digital converter (hereinafter referred to as an A / D converter) 4 that converts an I signal after passing through LPF 2 into a digital signal, and an A / A that converts a Q signal after passing through LPF 3 into a digital signal A D converter 5, an oscillator 6 that generates a reference clock for A / D conversion, a phase shifter 7 that changes the timing of the reference clock to create an A / D conversion clock for the I signal, and an A / D for the Q signal A phase shifter 8 for generating a conversion clock; a phase shifter 7; a phase shift data setting unit 9 for setting phase shift data in the phase shifter 8; and a demodulation processing unit 10 for decoding the received IQ signal. Yes.

  Next, the mechanism for canceling the I / Q time difference in this embodiment will be described in detail with reference to FIGS.

  FIG. 2 is a block diagram illustrating an example of a phase shifter in the embodiment of the present invention.

As shown in FIG. 2, the phase shifters 7 and 8 of this embodiment are phase shifters whose delay time can be varied by n-bit control data, and are the first-stage delay elements (delayed by time δ _t0 ). DL0) 21, and [delta] _t1 2-stage delay element for delaying _{(DL1) 22, δ tn-} 1 n -th stage delay element for delaying (DLn-1) 23, the signal does not pass a signal that has passed through the delay element The first stage switcher (SEL0) 24, the second stage switcher (SEL1) 25, and the nth stage switcher (SELn-1) 26 are provided. The expression from the 3rd stage to the (n-1) th stage is omitted to simplify the drawing.

  FIG. 3 is a detailed block diagram showing an example of the phase shift data setting unit in the embodiment of the present invention.

  As shown in FIG. 3, the phase data setting unit 9 of this embodiment includes an offset value register 31 that holds an I-side offset value, an offset value register 32 that holds a Q-side offset value, and a demodulation processing unit 10. And an adder 33 and an adder 34 that steadily add an offset to phase shift data common to I / Q that dynamically changes in accordance with the received signal.

  FIG. 4 is an operation explanatory diagram when there is a time difference between I / Qs in the receiving apparatus according to the embodiment of the present invention.

  FIG. 4 shows the error of the symbol point due to the time difference between I / Q in the transition from the symbol A point to the B point when the modulation method is 64QAM and the moving distance is the longest. When the I signal and the Q signal are sampled at the same timing, and the I signal is an optimal sampling point at this time, if there is no time difference between I / Q, the B point is regarded as a symbol point. At 50 Mbaud, if the Q signal is 10% (= 2 nsec) slower than the symbol rate period (= 20 nsec) with respect to the I signal, a symbol point appears at the position of the point B ′ that is the symbol area adjacent to the symbol area to be originally entered. It shows that it will end. In an LPF that allows a modulation signal having a symbol rate of about 50 Mbaud to pass therethrough, a variation of about a delay time of about nsec is very standard.

  In order to correct the delay of the Q signal, the A / D conversion clock of the Q signal may be delayed from the A / D conversion clock of the I signal, and when delayed by 2 nsec, the Q side offset value register 32 of FIG. A value corresponding to 0 nsec may be set in the offset value register 31 on the I side. Conversely, if the I side is delayed, the Q side offset value register 32 may be set to 0 nsec, and a value corresponding to the delay time may be set in the I side offset value register.

  The adder 33 and the adder 34 add the data of the offset value registers 31 and 32 to the common phase shift data in which the same I / Q value in the data decoded by the demodulation processing unit 10 is set, respectively. Are output to the phase shifter 7 as I-side final phase shift data and to the phase shifter 8 as Q-side final phase shift data. Since the time difference between I / Q is basically static and does not fluctuate, a value may be set in the offset value register in the initial adjustment stage.

  Next, a configuration example of the phase shifter when 2 nsec is set will be described with reference to FIG. In order to simplify the explanation, it is assumed that there is no delay time of the switch.

The set bit width of the phase shift data is n bits, the delay time of the delay element 21 is 10 (= 10 × 2 ⁰ ) psec, the delay time of the delay element 22 is 20 (= 10 × 2 ¹ ) psec, and the delay of the delay element 23 If the time is (10 × 2 ^n-1 ) psec, the 2nsec delay switches the fourth stage (80 psec), the seventh stage (640 psec), and the eighth stage (1280 psec) to select the delay element side, The first stage, the second stage, the third stage, the fifth stage, the sixth stage, the ninth stage to the nth stage can be realized by selecting the side that does not pass the delay element. If a maximum delay time of about 10 nsec is assumed, the phase shifter may be configured with 10 bits (n = 10).

  It should be noted that the time difference between I / Q should eliminate error factors as much as possible in high symbol rate and multilevel modulation transmission, and it is preferable that the phase shifter can be time-adjusted in as fine steps as possible, with a setting resolution of 10 psec. The degree of phase shifter can be easily implemented with a general-purpose device such as PECL (positive emitter coupled logic).

  Next, a method for obtaining the time difference between I / Q in the embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a block diagram showing a schematic configuration when measuring the time difference between I / Q in the embodiment of the present invention.

  FIG. 5 is obtained by adding a signal generator 11 that quadrature-modulates an I / Q signal and outputs it as an IF signal as a measurement signal source to the configuration of FIG. 1, and supplies a sample clock from the signal generator 11 as a reference clock. It is set as the structure which carries out.

  The signal generator 11 mainly includes an IQ data generation unit 11a and an orthogonal modulation unit 11b, and it is assumed that there is no time difference between I / Q. In this configuration, the signal generator 11 orthogonally modulates and outputs the I and Q signals that transition between the points A and B shown in FIG. 4 and outputs the signals from the A / D converter 4 and the A / D converter 5. Observe. As an initial state, the set values of the I-side phase shift offset value register 7 and the Q-side phase shift offset value register 8 are set to the same value, and the offset value is adjusted to the point where the amplitude of either I or Q is maximized. Next, when this adjustment point is an adjustment point at which the amplitude on the I side becomes maximum, the offset value on the Q side is adjusted to maximize the amplitude of Q. If the first adjustment point is the maximum point of the Q amplitude, then the I-side offset value is adjusted to maximize the I amplitude. This is the ideal symbol point of point A or point B, and the difference between the I-side offset value and the Q-side offset value set here represents the I / Q time difference.

  According to the receiving apparatus of the embodiment of the present invention, the time difference between the I / Q signals is canceled by individually adjusting the clock timing of the A / D conversion for each of the I signal and the Q signal. A / D conversion can be performed at optimum symbol timing for each of the Q and Q signals.

  The receiving apparatus of the present invention has an effect capable of performing A / D conversion at optimum symbol timing for each of the I signal and the Q signal, and is useful for a receiver of a high-speed digital radio transmission apparatus.

The block diagram which shows schematic structure of the receiver which concerns on embodiment of this invention The block diagram which shows an example of the phase shifter in embodiment of this invention Detailed block diagram showing an example of a phase shift data setting unit in an embodiment of the present invention Operation explanatory diagram when there is a time difference between I / Q in the receiving apparatus of the embodiment of the present invention The block diagram which shows schematic structure when measuring the time difference between I / Q in embodiment of this invention

Explanation of symbols

1 Orthogonal demodulation unit 2, 3 LPF
4, 5 A / D converter 6 Oscillator 7, 8 Phase shifter 9 Phase shift data setting unit 10 Demodulation processing unit 11 Signal generator 21, 22, 23 Delay element 24, 25, 26 Switcher 31, 32 Offset value register 33, 34 Adder

Claims (3)

An analog output quadrature demodulator that demodulates the quadrature-modulated signal into an in-phase component I signal and a quadrature component quadrature component orthogonal to the in-phase component;
A first analog-digital converter that digitally converts the I signal output from the quadrature demodulator;
A second analog-digital converter for digitally converting the Q signal output from the quadrature modulation unit;
A clock output unit that outputs a conversion clock independently to the first analog-digital converter and the second analog-digital converter;
A receiving device. The receiving device according to claim 1,
The clock output unit
An oscillator that generates a reference clock; and
A first phase shifter that delays the reference clock output from the oscillator and outputs the delayed reference clock to the first analog-digital converter;
A second phase shifter that delays the reference clock output from the oscillator and outputs the delayed reference clock to the second analog-digital converter;
A phase data setting unit that individually outputs control data to the first phase shifter and the second phase shifter;
A receiving apparatus. The receiving device according to claim 2,
The phase data setting unit
An offset value storage unit that stores a predetermined offset value for each of the first phase shifter and the second phase shifter;
The offset value for the first phase shifter stored in the offset value storage unit and the I and Q signals output from the first analog-digital converter and the second analog-digital converter are decoded. A first adder that adds the common phase data that is the phase data of the received signal and outputs the result to the first phase shifter;
A second adder that adds the offset value for the second phase shifter stored in the offset value storage unit and the common phase data and outputs the sum to the second phase shifter;
A receiving apparatus.

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