JP3818528B2 - Orthogonal frequency division multiplex signal receiving apparatus and orthogonal frequency division multiplex signal receiving method - Google Patents

Description

  The present invention relates to OFDM (Orthogonal Frequency Division Multiplexing Division Multiplexing) signal reception, and more particularly to an orthogonal frequency division multiplex signal receiving apparatus and orthogonal frequency division multiplex signal receiving method for receiving an OFDM signal suitable for digital mobile communication. About.

A conventional OFDM signal transmission apparatus will be described with reference to FIG.
First, a digital information data signal is supplied to the serial-parallel conversion circuit 70 via an input terminal, and an error correction code is given as necessary.
The output signal of this circuit 70 is supplied to an IFFT circuit 71, and the output signal is supplied to a D / A converter 73 via a guard interval circuit 72 for reducing multipath distortion.
Here, it is converted into an analog signal, and only the component of the necessary frequency band is passed by the next LPF 74.
The output signal of the analog value real and imaginary part is supplied to the quadrature modulator 75 to output an OFDM signal.

This OFDM signal is frequency-converted by a frequency converter 76 into a frequency band to be transmitted, supplied to the next transmission unit 77, and transmitted through a linear amplifier and a transmission antenna constituting the OFDM signal.
The output signal of the intermediate frequency generation circuit 78 and the signal via the 90 ° shift circuit 78A are supplied to the quadrature modulator 75, respectively.
The output signal of the circuit 78 is supplied to the clock signal generation circuit 79.
The output clock signal of the circuit 79 is supplied to the serial / parallel conversion circuit 70, IFFT circuit 71, guard interval circuit 72, and D / A converter 73, respectively.

Next, a conventional OFDM signal receiving apparatus will be described with reference to FIG.
The receiving unit 80 amplifies the signal from the transmitting unit 77 obtained by the receiving antenna constituting this by a high frequency amplifier, and converts the carrier frequency to an intermediate frequency, through a frequency converter 81 to convert the intermediate frequency amplifying circuit. 82 and further supplied to the quadrature demodulator 83.
The output signal of the circuit 82 is supplied to the intermediate frequency generation circuit 89 via the carrier detection circuit 90.
The output signal of the circuit 89 and the signal via the 90 ° shift circuit 89A are supplied to the quadrature demodulator 83, respectively, and the output signals of the real and imaginary parts are decoded.
The output signal of the quadrature demodulator 83 is supplied to the A / D converter 85 via the LPF 84 and converted into a digital signal, and the output signal of the quadrature demodulator 83 is also supplied to the synchronization signal generation circuit 91. .

The output of the A / D converter 85 is supplied to the FFT / QAM decoding circuit 87 via the next guard interval circuit 86.
The FFT and QAM decoding circuit 87 performs a complex Fourier calculation based on the supplied synchronization signal of the synchronization signal generation circuit 91, and a real part and an imaginary part signal (real part and imaginary part) for each frequency of the input signal. The level of the quantized digital signal transmitted by the carrier for digital information transmission is obtained, and the digital information is decoded.
The output signal of the FFT / QAM decoding circuit 87 is output via a parallel / serial conversion circuit 88.
Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device are completely the same, only the modulation component can be obtained, and there is no problem. However, the intermediate frequency generator circuit, the local oscillator of the frequency converter (not shown) If a signal with a low frequency stability is used, or if there is a phase error between both output signals, the subsequent demodulation operation is affected, and the probability of occurrence of a symbol error increases.

In a receiving apparatus that receives a transmitted OFDM signal, it is very difficult to completely reproduce the phase of all received carriers without having a time-axis fluctuation component, and multipath distortion is further reduced. In order to reduce this, a guard interval circuit is set on the transmission side, so when receiving a transmission signal of such a condition, the phase of the transmission signal is set to the transmission side between the effective symbol period part and the guard interval part. There is a problem that it is more difficult to reproduce in the completely same state.
The present invention has been made paying attention to the above points, and by setting an OFDM specific carrier as a pilot signal carrier, the orthogonal frequency division multiplexing in which the synchronization relationship on the receiving side can be kept constant. It is an object of the present invention to provide a signal receiving apparatus and an orthogonal frequency division multiplex signal receiving method.

The present invention comprises the means described in the following items 1) to 4).
That is,
1) An orthogonal frequency division multiplex signal receiving apparatus for receiving a multilevel QAM modulated digital information signal which is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added thereto,
A real part of the pilot signal obtained by demodulating the pilot signal transmitted as a signal having a high-order frequency and having a constant amplitude, which are present in the same wavelength in adjacent effective symbol sections, and exist in integer wavelengths in the guard interval And a pilot signal demodulating means for obtaining a demodulated output of the imaginary part, an FFT means for converting the multilevel QAM modulated signal into the digital information signal with reference to the pilot signal demodulated output,
An orthogonal frequency division multiplex signal receiving apparatus comprising: An orthogonal frequency division multiplex signal receiving apparatus for receiving a digital information signal that has been subjected to orthogonal frequency division multiplexing with a pilot signal and transmitted with a guard interval added,
A pilot signal demodulating means for phase demodulating the pilot signal which is an integer wavelength in the guard interval and which is a high-order frequency held in phase with each other in adjacent effective symbol sections and transmitted as a constant amplitude signal; Demodulating means for converting the multi-level QAM modulated signal into the digital information signal using phase information of the pilot signal obtained by demodulation by the pilot signal demodulating means;
An orthogonal frequency division multiplex signal receiving apparatus comprising:
2) An orthogonal frequency division multiplex signal receiving apparatus for receiving a digital information signal that is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added,
A pilot signal demodulating means for phase demodulating the pilot signal which is an integer wavelength in the guard interval and which is a high-order frequency held in phase with each other in adjacent effective symbol sections and transmitted as a constant amplitude signal; Demodulating means for converting the multi-level QAM modulated signal into the digital information signal using phase information of the pilot signal obtained by demodulation by the pilot signal demodulating means;
An orthogonal frequency division multiplex signal receiving apparatus comprising:
3) A method of receiving an orthogonal frequency division multiplexed signal for receiving a digital information signal that is orthogonal frequency division multiplexed with a pilot signal and is transmitted with a guard interval added and is subjected to multilevel QAM modulation,
A real part of the pilot signal obtained by demodulating the pilot signal transmitted as a signal having a high-order frequency and having a constant amplitude, which are present in the same wavelength in adjacent effective symbol sections, and exist in integer wavelengths in the guard interval And obtaining a demodulated output of the imaginary part;
Referring to the pilot signal demodulated output obtained in the step, and converting the multi-level QAM modulated signal into the digital information signal;
A method for receiving an orthogonal frequency division multiplex signal.
4) A reception method of an orthogonal frequency division multiplex signal for receiving a multilevel QAM modulated digital information signal which is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added thereto,
The pilot signal that is an integer wavelength in the guard interval, is a higher-order frequency that is held in phase with each other in adjacent effective symbol sections, and is transmitted as a signal having a constant amplitude, is demodulated to obtain phase information of the pilot signal. Obtaining step;
Converting the multi-level QAM modulated signal into the digital information signal using the phase information of the pilot signal obtained in the step;
A method for receiving an orthogonal frequency division multiplex signal.

In the OFDM signal receiving apparatus and OFDM signal receiving method of the present invention, an integer wavelength exists in the guard interval, and a real part obtained by demodulating pilot signals of higher-order frequencies held in phase with each other in adjacent effective symbol sections; By referring to the demodulated output of the imaginary part, it becomes easy to set the same time relationship between the IFFT circuit operating in the transmitting apparatus and the FFT circuit operating in the receiving apparatus, which is close to the signal that has performed the IFFT operation. The FFT operation can be performed in the form, and more accurate information can be received.
In addition, there are integer wavelengths in the guard interval, and phase demodulation of pilot signals of higher-order frequencies that are held in phase with each other in adjacent effective symbol sections is performed to obtain phase information of the pilot signal, and using the obtained phase information In the reception of converting a multi-level QAM modulation signal into a digital information signal, it becomes easy to set the same phase relationship between the IFFT circuit operating in the transmitting apparatus and the FFT circuit operating in the receiving apparatus, and performs the IFFT operation. The FFT operation can be performed in a form close to that of the received signal, and more accurate information can be received.

Embodiments of an OFDM signal transmitting / receiving apparatus adapted to the orthogonal frequency division multiplexing signal receiving apparatus and orthogonal frequency division multiplexing signal receiving method of the present invention will be described below with reference to FIGS.
FIG. 1 shows an embodiment of an OFDM signal transmitting apparatus applied to the present invention, and digital data transmitted here is compressed audio, video signals, and the like.
An OFDM signal transmission apparatus arranges a large number of carriers orthogonally and transmits independent digital information on each carrier. Since the carriers are orthogonally crossed, the spectrum of the adjacent carrier is the frequency position of the carrier. Becomes zero.
IFFT circuit technology is used to make this orthogonal carrier. If inverse DFT (Discrete Fourier Transform) with N complex numbers is performed during a time interval T that is a window interval in IFFT, an OFDM signal can be generated, and each point of the inverse DFT corresponds to a modulated signal output. The N is also called an IFFT or FFT cycle. For details, see pages 74 to 75 of “Signal Processing Engineering” edited by the Television Society of Japan, published by Corona Co., Ltd. (issue date: May 20, 1993). Explained.

The basic specifications of the apparatus according to this embodiment shown in FIGS. 1 and 2 are as shown below.
(a) Center carrier frequency: 100 MHz (b) Number of carriers for transmission: 248 waves
(c) Modulation method: 256QAM OFDM (d) Number of carriers used: 257 waves
(e) Transmission bandwidth: 100 kHz, bandwidth used: 99 kHz
(f) Transfer rate ... 750kbps (g) Guard interval ... 60.6μsec
As shown in FIG. 1, for example, a digital information signal that is an audio or video signal in which an information signal is compressed by an encoding method such as MPEG is supplied to a serial-to-parallel conversion circuit 2 via an input terminal 1 and is necessary. Accordingly, an error correction code is assigned.
In this circuit 2, the input signals are arranged and output as signals for 256QAM modulation.
This 256QAM modulation is a system in which 16 levels in the amplitude direction and 16 levels in the angle direction are defined for each carrier to which information is to be transmitted, and 256 values of 16 × 16 are specified and transmitted.
In this embodiment, information is transmitted using 248 of 257 carriers, and the remaining nine waves are used for calibration and other auxiliary signals.

The serial-parallel conversion circuit 2 is configured to output 248 bytes of digital data during one symbol period, that is, 248 sets of parallel data of 4 bits each during one symbol period.
The output signal of the serial / parallel conversion circuit 2 is supplied to the IFFT / pilot signal generation circuit 3. The circuit 3 operates in accordance with the clock signal output from the clock signal generation circuit 10, performs 256QAM modulation on the 248-wave carrier, and outputs each output signal as a real and imaginary component.
The IFFT / pilot signal generation circuit 3 uses an IFFT circuit having a period of N, and discrete frequency point information corresponding to N discrete frequency points (sample points) in each effective symbol period set by the IFFT circuit. Is output from the IFFT / pilot signal generation circuit 3.
The Nyquist frequency corresponds to ½ of the sample clock frequency in the IFFT having the period N, and the pilot signal is transmitted as information of the Nyquist frequency, that is, Nyquist frequency information. Since this Nyquist frequency is ½ of the sample clock frequency, a sampling position signal (sample clock signal) for operating the FFT circuit can be generated by decoding and multiplying the Nyquist frequency information by the receiving device. .
This Nyquist frequency information is obtained by applying a signal of a constant level to the terminal of the N / 2th frequency in the real part input terminal R (imaginary part input terminal I) of the IFFT of the IFFT / pilot signal generation circuit 3.

The output signals of these IFFT and pilot signal generation circuits 3 are supplied to a guard interval setting circuit 4 having a next RAM (Random Access Memory) 4A. This guard interval setting circuit 4 reduces multipath distortion in the transmission path. The guard interval gi of a predetermined section for making it run is set as shown in FIG.
The guard interval setting circuit 4 operates in accordance with the clock signal output from the clock signal generation circuit 10, and the last part in the window interval (effective symbol period ts) obtained from the IFFT / pilot signal generation circuit 3 is used as the window interval. Place it just before.
In order to set the guard interval, the guard interval setting circuit 4 reads the signal from the IFFT / pilot signal generation circuit 3 fetched into the RAM (4A) included in the guard interval setting circuit 4 (the last period of the effective symbol period ( Set this period equal to gi.
) Is returned to the beginning of the effective symbol period, the data of the effective symbol period ts is read, and the signal of the symbol period ta is transmitted.
The Nyquist frequency information (pilot signal) is transmitted even within the guard interval. However, in order to maintain continuity with the preceding and succeeding IFFT window interval signals, it is assumed that the transmitted pilot signal has an integer wavelength within the guard interval. Let me.

Although the case where the Nyquist frequency is used as the pilot signal has been described, it is not always necessary to use the Nyquist frequency as long as it has a simple integer ratio to the sample clock signal, and the higher one of the transmitted frequencies is used. May be.
When considering an IFFT with a period of M, a pilot signal is arranged at a half of the Nyquist frequency, that is, at an M / 4th frequency, and a carrier transmitted by OFDM is M / 4th from the first in IFFT. And signals output from the 3rd M / 4th to the Mth are used.
Thus, even if an IFFT with a period M = 2N is used, an IFFT output signal equivalent to that when an IFFT with a period N is used can be obtained. Accordingly, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding the pilot signal and multiplying it by four.
If the FFT window section signal information can be separately decoded, the FFT calculation of the OFDM signal can be performed in combination with the sample clock signal obtained by this embodiment, and the OFDM signal can be decoded.

Next, the symbol period set by the guard interval setting circuit 4 will be described with reference to FIG.
First, when the use bandwidth is 99 kHz and the IFFT cycle is N = 256, the effective symbol frequency fs and the effective symbol period ts are as follows.
fs = 99,000 / 256 = 387 Hz
ts = 1 / fs = 2586 μsec
If the guard interval period gi, which is the multipath distortion elimination section, is determined to be three wavelengths for the pilot signal, gi is set as follows.
gi = (1 / 49,500) × 3 = 60.6 μsec
The symbol period ta and the symbol frequency fa at this time are as follows.
ta = ts + gi = 2586 + 60.6 = 2646.6 μsec
fa = 1 / ta = 378 Hz

The output signals of these guard interval setting circuits 4 are supplied to a D / A converter 5 where they are converted into analog signals, and only the necessary frequency band components are passed by the next LPF 6.
The real and imaginary output signals of analog values are supplied to the next quadrature modulator 7, and the modulator 7 outputs a signal via the output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the 90 ° shift circuit 8. Are supplied to output an OFDM signal.
This OFDM signal is frequency-converted by the frequency converter 11 to a frequency band to be transmitted, supplied to the next transmitter 12, and transmitted via a linear amplifier and a transmission antenna constituting the OFDM signal.
The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. In the clock signal generation circuit 10, the clock signal for driving the IFFT / pilot signal generation circuit 3 and the clock signal for driving the guard interval setting circuit 4 are common clock signals supplied from the intermediate frequency generation circuit 9. Generated based on
Since 248 sets of 4 + 4 bit parallel data are transmitted by a carrier of 248 waves, the transmission speed of this apparatus is 248 bytes per symbol period. Therefore, the transmission rate per second is approximately 750 Kbits.

Next, the phase relationship between the guard interval, the symbol period, and the synchronization signal (pilot signal) will be described below with reference to the drawings.
In FIG. 7 according to the embodiment of the present invention, a case where a synchronization signal (pilot signal) having the same phase is generated in each symbol period and a synchronization signal having an integer wavelength is present in the guard interval will be described. (This is a first example in which a continuous synchronization signal is generated without inverting the polarity.)
The IFFT shown in FIG. 7 is synonymous with the effective symbol period and the IFFT period, and one cycle at the end of the IFFT period (right part) is directly used as a signal of the guard interval G immediately before the IFFT period (left part). .
In this example, the synchronization signal (pilot signal) having the same phase is generated every IFFT period, and the synchronization signal (pilot signal) also exists in the guard interval section, so that the pilot signal is transmitted over a plurality of symbol periods. It is generated continuously.
The case of FIG. 3 already described is the same as the case of FIG. 7, and since the synchronization signal (pilot signal) also exists in the guard interval section, the pilot signal is continuously generated over a plurality of symbol periods. Yes.

In FIG. 8 shown as a reference example, a case where synchronization signals (pilot signals) having the same phase are generated in every other symbol period and a synchronization signal having an odd multiple of a half wavelength exists in the guard interval will be described. (This is a second example of generating a continuous synchronization signal without inverting the polarity.)
IFFT is synonymous with an effective symbol period and an IFFT period, and a half cycle at the end (right part) of the IFFT period is used as a guard interval signal immediately before the IFFT period (left part).
In this example, a synchronization signal (pilot signal) having a reverse polarity is generated every IFFT period, and a synchronization signal having an odd multiple of a half wavelength is also present in the guard interval period. Therefore, in a plurality of symbol periods (symbol periods). The pilot signal is continuously generated.

In FIG. 9 shown as a reference example, a case where the synchronization signal exists in the guard interval G at odd multiples of a half wavelength will be described. (This is a first example of generating a synchronization signal with the polarity reversed.)
In this case, the polarity of the pilot signal is inverted at the start point of the guard interval, and the phase of the pilot signal for each symbol period is in phase.
That is, the terminal voltage corresponding to the frequency for generating the IFFT synchronization signal for generating the frequency division multiplexed signal is constant for each symbol, and the synchronization signal having the same phase is always generated.
Therefore, when the guard interval is an odd multiple of a half wavelength, the synchronization signal becomes a continuous signal by inverting the polarity of the synchronization signal every other symbol period on the receiving device side.
In this case, a synchronization signal can be detected using a PLL circuit with a phase synchronization circuit as shown in FIG.

In FIG. 10 shown as a reference example, a case where the synchronization signal (pilot signal) exists in an even multiple of a half wavelength in the guard interval will be described. (This is a second example of generating a synchronization signal with the polarity reversed.)
As shown in FIG. 10, even when the synchronization signal (pilot signal) present in the guard interval is an integer wave (an even multiple of a half wavelength), the synchronization signal is symbol period 1 as in FIG. When output is inverted every other time, a synchronous output whose polarity is inverted for each symbol is obtained.
Also in this case, the synchronization signal can be detected using a PLL circuit as shown in FIG.

FIG. 11 shown as a reference example is a phase synchronization circuit that detects a synchronization signal that is inverted every other symbol period.
This phase synchronization circuit is a signal switching circuit composed of exclusive OR to the VCO output of a PLL circuit composed of a phase comparator PD2 (112), Amp (amplifier 113), LPF (114), and VCO circuit (115). The device 116 is inserted.
The phase comparator PD1 (111) constitutes a synchronous detection circuit that receives the VCO output of the phase synchronization circuit. The frequency division division signal including the synchronization signal applied to the input terminal 110 is input to both the phase synchronization circuit and the synchronization detection circuit PD1 (111). This phase synchronization circuit comprises a PLL composed of a phase comparator PD2 (112), an amplifier (113), an LPF (114), a VCO (115), and a signal switcher (116).
The signal switch (116) inverts the output of the PLL VCO circuit 115 in accordance with the output of the synchronously detected PD1 (111). The phase comparator PD2 (112) detected by the detection circuit and supplied with the polarity-inverted VCO output is supplied to the phase comparator PD2 (112).

FIG. 12 shows the output waveforms of terminals B and A in FIG. Output A is a synchronization signal output waveform, and output B is a symbol synchronization signal transmitted with its polarity inverted every symbol period (symbol period).
FIG. 13 shows another circuit example corresponding to FIG. 11, and the signal switch 136 is inserted between the phase comparator PD2 (132) and the amplifier 133.
At the same time as the synchronization signal is inverted, it is detected and the polarity of the error signal is inverted. The mode of operation is the same as in FIG. In any case, even if the synchronization signal is inverted every other symbol period (symbol period), it is detected and the characteristics of the PLL loop are inverted. Therefore, the VCO continues to operate without being inverted. . Therefore, the synchronization signal can be normally decoded.

Next, an embodiment of an OFDM signal receiving apparatus adapted to the present invention will be described with reference to FIGS.
Each configuration of the receiving device is configured by a circuit that operates in reverse to the transmitting device.
The receiving unit 20 amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting this by a high frequency amplifier and supplies the amplified signal to the frequency converter 21.
This output signal is supplied to the intermediate frequency amplifying circuit 22 and output from the intermediate frequency amplifying circuit 22 as a reception signal of a predetermined level.
The output signal of the intermediate frequency amplifier circuit 22 is supplied to an orthogonal demodulator 23 and a carrier detection (carrier extraction) circuit 29, respectively.
The carrier detection circuit 29 has a PLL circuit including a phase comparator (multiplier) 41, an LPF 42, a VCO circuit 43, and a 1/4 frequency divider circuit 45 illustrated in FIG. 4, and this output signal is supplied. The intermediate frequency oscillation circuit 31 is a circuit that extracts the center carrier with a small phase error.

In this embodiment, carriers for transmitting information are arranged adjacent to each other at a symbol frequency of 378 Hz to constitute an OFDM signal. The information carrier adjacent to the center carrier is also only 378 Hz away, and the center carrier needs to transmit information without being affected by the adjacent information carrier, and a circuit with high selectivity is used.
In this embodiment, a center carrier is extracted using a PLL circuit. A crystal oscillator (VCXO) that oscillates at about ± 200 Hz, which is approximately a half of an adjacent carrier frequency interval, is a voltage controlled oscillator (VCO) 43. To operate the circuit. The LPF used in the PLL circuit also has a cutoff frequency that is sufficiently low with respect to 378 Hz.
The output signal of the intermediate frequency generation circuit 31 and the signal via the 90 ° shift circuit 30 are supplied to the quadrature demodulator 23 having multipliers 40 and 41, respectively, so that the real and imaginary part (real part, imaginary part) The output signal is decoded.
The real part and imaginary part output signals are supplied to the LPF 24 and transmitted as signals of the OFDM signal. The signals in the necessary frequency band are passed through, and the input analog signal is sampled, and the output signal is A / D converted. Is supplied to a sampling device 25 and converted into a digital signal.

In the sample synchronization signal generation circuit 32 applied to the present invention, the sample clock signal before frequency multiplication is generated by a PLL circuit that is phase-synchronized with the pilot signal, and an analog output signal of the quadrature demodulator 23 is supplied to this circuit. Is done. The PLL is phase-synchronized with the pilot signal transmitted as a continuous signal in each symbol period including the guard interval period, and a demodulated pilot signal is obtained.
In the transmitter, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and frequency multiplication is performed in accordance with the frequency ratio to obtain a sample clock signal.
The guard interval processing circuit 26 can obtain an effective symbol period signal of the period ts at an arbitrary timing within the symbol period ta from the transmitted signal, and selects the effective symbol period signal with less influence of multipath distortion from among the effective symbol period signals. Then, an output signal is supplied to the FFT / QAM decoding circuit 27.

A symbol synchronization signal generation circuit 33 for detecting the symbol period detects the symbol period.
The next FFT and QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal, performs a complex Fourier operation, and implements a real part and an imaginary part signal (real part, Imagine the level of Imaginary Part).
The real part and imaginary part signal level for each frequency thus obtained are compared with the demodulated output of the reference carrier for transmitting the reference value of the real part and imaginary part of each carrier to be transmitted, The level of the quantized digital signal transmitted by the carrier for digital information transmission is obtained, and the digital information is decoded.
The output signal of this circuit 27 is output via a parallel / serial conversion circuit 28.

Next, the carrier detection circuit 29 and the sample synchronization (sample clock) signal generation circuit 32 will be described with reference to FIG.
The purpose of this circuit is to extract a pilot signal transmitted at a constant level and generate an accurate sample synchronization (sample clock) signal based on the extracted pilot signal.
First, the VCO circuit 43 constituting the carrier detection circuit 29 is oscillated at a frequency of 42.8 MHz, which is four times the intermediate frequency 10.7 MHz. The output signal of the VCO circuit 43 is supplied to the multipliers 40 and 41 via the 1/4 frequency dividing circuits 44 and 45, respectively.
The output signal from one of the multipliers 41 is supplied to the LPF 42, and components below the symbol frequency are extracted. The output signal controls the VCO circuit 43.
A loop formed by the multiplier 41, the LPF 42, the VCO circuit 43, and the frequency dividing circuit 45 constitutes a PLL circuit.

An intermediate frequency amplified signal is applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit to obtain an output signal of a real part and an imaginary part.
The sample synchronization signal generation circuit 32 is supplied with the real part output signal from the quadrature demodulator 23 and detects a Nyquist frequency component transmitted as a pilot signal.
An output signal of the VCO circuit 43 is supplied to the frequency division ratio variable circuit (VCO circuit) 50, and the frequency division ratio is set from 1/426 to 1/438. The multiplier 52 in the sample synchronization signal generation circuit 32 is supplied with the output signal from the quadrature demodulator 23 and the signal from the VCO circuit via the 1/2 frequency divider circuit 51, and operates as a phase comparator. Do.

The output signal of the multiplier 52 passes only an error signal related to frequency control by the LPF circuit 53. The delay circuit 54 and the adder circuit 55 are circuits for attenuating adjacent carrier components, and have a characteristic of giving a dip to the symbol frequency of 387 Hz.
In the PLL circuit composed of the VCO circuit (frequency division ratio variable circuit) 50, the multiplier 52, and the LPF 53, the VCO output synchronized with the continuous pilot signal included in the real part output signal of the quadrature demodulator 23 of the carrier extraction unit. The signal is oscillated and output as a 99 kHz sample clock output signal.
In the above embodiment, the case where an IFFT having a period of 256 is used to generate a carrier of 257 waves has been described. However, as an embodiment applied to the present invention, an example using an IFFT having a period of 512 will be described below.
In an embodiment using an IFFT with a period of 512, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio to the sample clock signal is used.

That is, when considering an IFFT with a period M, a pilot signal is arranged at a half of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier transmitted by OFDM is M / th higher than the first in the IFFT. The signals output from the 4th to the 4th and from the 3rd M / 4th to the Mth are used.
Thus, even if an IFFT with a period M = 2N is used, an IFFT output signal equivalent to that when an IFFT with a period N is used can be obtained. Accordingly, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding the pilot signal and multiplying it by four.

In the sample synchronization signal generation circuit used at this time, the frequency of the pilot signal is the same as in the embodiment in which the period N is 256, but the sample clock frequency for driving the FFT and QAM decoding circuit 27 shown in FIG. This is twice as long as the period N is 256. Accordingly, a doubled 198 kHz sample clock signal is output.
Therefore, in this sample synchronization signal generating circuit, the dividing ratio of the dividing ratio variable circuit 50 is 1/213 to 1/219, and the dividing ratio of the 1/2 dividing circuit 51 is 1. / 4 is different, and other configurations are the same as those in FIG. 4, and the description thereof is omitted.

It is a block diagram of the Example of the OFDM signal transmitter applied to this invention. It is a block diagram of the Example of the OFDM signal receiver applied to this invention. It is the figure which illustrated the relationship between the symbol period of the OFDM signal which concerns on the Example of this invention, and a guard interval. It is a block diagram of a carrier extraction unit and a sample synchronization signal generation unit of an OFDM signal receiving apparatus according to an embodiment of the present invention. It is a block diagram of the conventional OFDM signal transmitter. It is a block diagram of the conventional OFDM signal receiver. It is the figure which showed the relationship between the synchronizing signal applied to this invention, and a symbol period. It is the figure which showed the relationship between the synchronizing signal shown as a reference example, and a symbol period. It is the figure which showed the relationship between the synchronizing signal shown as a reference example, and a symbol period. It is the figure which showed the relationship between the synchronizing signal shown as a reference example, and a symbol period. It is the figure which showed the example of the phase locked loop shown as a reference example. It is an output waveform diagram of a phase locked loop shown as a reference example. It is the figure which showed another example of the phase locked loop shown as a reference example.

Explanation of symbols

2 Serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 guard interval setting circuit 4A RAM (random access memory)
5 D / A converter 6, 24, 42, 53, 114, 134 LPF
7 Quadrature modulator 8, 30 90 ° shift circuit 9, 31 Intermediate frequency generation circuit 10 Clock signal generation circuit 11, 21 Frequency converter 12 Transmitter 20 Receiver 23 Orthogonal demodulator 25 A / D converter (sampling circuit)
26 guard interval processing circuit 27 FFT, QAM decoding circuit 28 parallel-serial conversion circuit 29 carrier detection circuit 32 sample synchronization signal generation circuit 33 symbol synchronization signal generation circuit 40, 41, 52 multiplier (phase comparator)
43, 50, 115, 135 VCO circuit 44, 45 1/4 frequency divider 51 1/2 frequency divider 111, 112, 131, 132 Phase comparator (PD)
116,136 Signal selector

Claims (4)

An orthogonal frequency division multiplex signal receiving apparatus for receiving a digital information signal that has been subjected to orthogonal frequency division multiplexing with a pilot signal and transmitted with a guard interval added,
A real part of the pilot signal obtained by demodulating the pilot signal transmitted as a signal having a high-order frequency and having a constant amplitude, which are present in the same wavelength in adjacent effective symbol sections, and exist in integer wavelengths in the guard interval And a pilot signal demodulating means for obtaining a demodulated output of the imaginary part, an FFT means for converting the multilevel QAM modulated signal into the digital information signal with reference to the pilot signal demodulated output,
An orthogonal frequency division multiplex signal receiving apparatus comprising: An orthogonal frequency division multiplex signal receiving apparatus for receiving a digital information signal that has been subjected to orthogonal frequency division multiplexing with a pilot signal and transmitted with a guard interval added,
A pilot signal demodulating means for phase demodulating the pilot signal which is an integer wavelength in the guard interval and which is a high-order frequency held in phase with each other in adjacent effective symbol sections and transmitted as a constant amplitude signal; Demodulating means for converting the multi-level QAM modulated signal into the digital information signal using phase information of the pilot signal obtained by demodulation by the pilot signal demodulating means;
An orthogonal frequency division multiplex signal receiving apparatus comprising: An orthogonal frequency division multiplexed signal receiving method for receiving a digital information signal subjected to multi-level QAM modulation which is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added thereto,
A real part of the pilot signal obtained by demodulating the pilot signal transmitted as a signal having a high-order frequency and having a constant amplitude, which are present in the same wavelength in adjacent effective symbol sections, and exist in integer wavelengths in the guard interval And obtaining a demodulated output of the imaginary part;
Referring to the pilot signal demodulated output obtained in the step, and converting the multi-level QAM modulated signal into the digital information signal;
A method for receiving an orthogonal frequency division multiplex signal. An orthogonal frequency division multiplexed signal receiving method for receiving a digital information signal subjected to multi-level QAM modulation which is orthogonal frequency division multiplexed with a pilot signal and transmitted with a guard interval added thereto,
The pilot signal that is an integer wavelength in the guard interval, is a higher-order frequency that is held in phase with each other in adjacent effective symbol sections, and is transmitted as a signal having a constant amplitude, is demodulated to obtain phase information of the pilot signal. Obtaining step;
Converting the multi-level QAM modulated signal into the digital information signal using the phase information of the pilot signal obtained in the step;
A method for receiving an orthogonal frequency division multiplex signal.

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