JP2009239147A - Integrated semiconductor device, and integrated three-dimensional semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated semiconductor device capable of mounting a high-reliability heterogeneous device by eliminating a through-hole defect; and to provide an integrated three-dimensional semiconductor device. <P>SOLUTION: The integrated semiconductor device includes: a plurality of integrated circuit chips arranged side by side in an inner region; a first insulation part filled in the respective circumferences of the plurality of integrated circuit chips to hold the plurality of integrated circuit chips, and containing a quartz filler; a wiring layer arranged on a surface of the inner region, and connected to at least any of the plurality of integrated circuit chip; an input/output part arranged in the inner region for connecting at least any of the plurality of integrated circuit chips to an external circuit; a second insulation part arranged in at least part of an outer region around the inner region, and having a quartz filler content percentage lower than that of the first insulation part; and a penetrating electrode penetrating the second insulation part to connect its front and backsides to each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an integrated semiconductor device and an integrated three-dimensional semiconductor device on which a plurality of integrated circuit chips are mounted.

  2. Description of the Related Art In recent years, high integration technology for semiconductor devices has progressed, and the integration technology for semiconductor elements constituting the semiconductor devices is also required to have high density. In particular, recent high integration technologies for semiconductor devices require technologies for highly integrating electromechanical elements (MEMS) as well as various high-performance semiconductor elements (LSI: Large Scale Integration). ing.

  The MEMS is an electromechanical element having a micro structure and is manufactured using, for example, a silicon microfabrication process. MEMS is expected to be applied in a wide range of electronic component fields such as pressure sensors, acceleration sensors, and RF (Radio Frequency) filters. As a technique for integrating such a MEMS with an LSI, there is a high-density three-dimensional mounting technique in which each LSI and the MEMS are directly stacked. However, this technique requires high process costs because it is necessary to form vertical through holes in LSI and MEMS. For this reason, a technique for highly integrating LSI and MEMS on the same plane is required.

As a method for highly integrating general semiconductor elements on the same plane, there are typically two systems, SOC (System on Chip) and SIP (System in Package).
The SOC is a method of integrating a plurality of devices by directly forming them on one chip. Although this SOC can increase the degree of integration, there are limitations on the types of devices that can be integrated. For example, it is difficult to form a device made of another crystal system such as GaAs on a Si substrate due to process differences. In addition, the SOC has a problem that the design period for producing a new device is long and the development cost is high.

  On the other hand, in SIP, after each LSI chip is individually formed, each is mounted on an integrated substrate. Since this SIP can be formed individually for each device, there is no restriction on the devices to be integrated. Furthermore, when a new system is manufactured, since an existing chip can be used, the design period can be shortened, so that the development cost can be reduced. However, in SIP, there is a problem that it is difficult to increase the density because individual devices are connected by wiring on an integrated substrate.

  On the other hand, for example, there has been proposed an integrated semiconductor device in which an LSI and a MEMS completed by individual manufacturing techniques are made into individual chips by dicing and then rearranged adjacent to each other at a chip level to be reconstructed as a MEMS integrated wafer. (Patent Document 1). This reconfigurable integrated semiconductor device can integrate different types of devices with different manufacturing technologies, and can reduce the manufacturing cost by reintegrating only normal operation products that have been inspected and selected. Further, in a reconfigurable integrated semiconductor device, an integrated substrate is not used unlike SIP, so that the LSI and the MEMS to be mounted are connected by a fine wiring layer. As a result, the reconfigurable integrated semiconductor device has features that can achieve high integration that cannot be achieved by conventional SIP and shortening of design and manufacturing that cannot be achieved by SOI.

In this reconfigurable integrated semiconductor device, when it is not practical to construct an integrated semiconductor device having a large area, a three-dimensional mounting structure in which the stacking direction is a mounting region is used. In order to further improve the integration density, a three-dimensional mounting structure in which the stacking direction is a mounting region is advantageous. Therefore, it is considered that a semiconductor device is three-dimensionally mounted according to the necessity of the electronic equipment system configuration. It has been.
Generally, in a structure in which semiconductor elements are three-dimensionally mounted, it is necessary to form through electrodes for connecting the semiconductor elements in the stacking direction. As a method for forming this through electrode, for example, a method of forming a through hole in a silicon semiconductor device by RIE (Reactive Ion Etching) and then filling the through hole with metal, that is, a TSV (Through Silicon Via) method can be mentioned. However, there is a problem that a through hole forming region such as forming in a region where a device is not formed is limited, and a process for forming the through hole is complicated and manufacturing cost is expensive.
For this reason, in a reconfigurable integrated semiconductor device, it is generally considered advantageous to form a through hole in an insulating material portion disposed between semiconductor elements. This is because when the insulating material used in the reconfigurable integrated semiconductor device is an organic material such as an epoxy resin, the process of forming the through hole is compared with the TSV structure in which the through hole is arranged in silicon. This is because it is easy.

As an organic material used in such a reconfigurable integrated semiconductor device, a material containing a quartz filler having high mechanical properties such as a thermal expansion coefficient and a Young's modulus is used in order to improve stress strain reliability. It is preferable. However, when a quartz filler is contained, if the through hole formed in the insulating material is miniaturized, this quartz filler becomes an obstacle and it is difficult to form a fine through electrode, and a through hole defect may occur. Furthermore, by forming the through electrode in the insulating material, there is a problem that the strength of the insulating material between the integrated circuit chips holding the integrated circuit chip is reduced and the integrated semiconductor device is destroyed.
JP 2007-260866 A

  The present invention is based on the above-described problems, and an object of the present invention is to provide an integrated semiconductor device and an integrated three-dimensional semiconductor device in which a through hole defect is eliminated and a highly reliable heterogeneous device can be mounted. is there.

  According to one aspect of the present invention, there is provided an integrated semiconductor device including a plurality of integrated circuit chips, the plurality of integrated circuit chips juxtaposed in an inner region, and a filling around each of the plurality of integrated circuit chips. A first insulating portion that holds the plurality of integrated circuit chips and contains a quartz filler; a wiring layer that is disposed on a surface of the inner region and connected to at least one of the plurality of integrated circuit chips; An input / output unit disposed in an inner region, for connecting at least one of the plurality of integrated circuit chips and an external circuit; and disposed in at least a part of an outer region around the inner region; and the first insulating unit There is provided an integrated semiconductor device comprising: a second insulating portion having a lower quartz filler content ratio; and a through electrode that penetrates the second insulating portion and connects the front surface and the back surface. It is.

  According to another aspect of the present invention, there is provided the integrated semiconductor device, and a semiconductor device stacked with the integrated semiconductor device and electrically connected to at least one of the plurality of integrated circuit chips. An integrated three-dimensional semiconductor device is provided.

  According to the present invention, there are provided an integrated semiconductor device and an integrated three-dimensional semiconductor device capable of eliminating a through-hole defect and mounting a highly reliable heterogeneous device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic view illustrating the configuration of an integrated semiconductor device according to the first embodiment of the invention.
1A is a schematic plan view of the integrated semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view taken along line AA ′ of FIG. 1A.
As shown in FIGS. 1A and 1B, the integrated semiconductor device 10 according to the first embodiment of the present invention includes a plurality of integrated circuit chips 105. In the case of the integrated semiconductor device 10, five integrated circuit chips 105 arranged in parallel in the plane are arranged. An area where the integrated circuit chip 105 is mounted is an inner area 101.
The upper surfaces (front surfaces) of these integrated circuit chips 105 are placed on the same surface because the integrated circuit chips need to be connected by a fine wiring layer.

  In the inner region 101, first insulating portions 210 that are filled around the integrated circuit chips 105 and hold the integrated circuit chips 105 are disposed. The first insulating portions 210 can be disposed between the integrated circuit chips 105 and on the second main surface 302 side of the integrated circuit chip 105.

  In the inner region 101, input / output units (I / O electrodes) 170 are arranged on the first main surface (front surface) 301 and the second main surface (back surface) 302 of the integrated semiconductor device 10. In the integrated semiconductor device 10, the I / O electrode 170 is disposed on both the first main surface 301 and the second main surface 302 of the integrated semiconductor device 10. It can be disposed on at least one of the second main surfaces 302.

Further, a fine wiring layer (wiring layer) 280 for connecting the integrated circuit chips 105 is disposed on the first main surface 301 side of the inner region 101.
That is, the integrated semiconductor device 10 includes a plurality of integrated circuit chips 105. The integrated circuit chip 105 is disposed in the inner region 101, and is disposed on the first insulating portion 210 that holds the integrated circuit chip 105 and the first main surface 301 of the inner region 101, and is at least one of the integrated circuit chips. And a fine wiring layer 280 connected to each other, and an input / output unit 170 disposed in the inner region 101 for connecting at least one of the integrated circuit chip 105 and an external circuit.

A second insulating part 220 is disposed in at least a part of the outer region 102 around the first insulating part 210. In the specific example shown in FIG. 1, the second insulating portion 220 is disposed in the outer region 102 outside the inner region 101, that is, in the outer peripheral portion of the integrated semiconductor device 10.
In addition, for example, the wiring of the first main surface 301 of the integrated semiconductor device 10 and the wiring of the second main surface 302 that is the back surface of the first main surface 301 are electrically connected to the second insulating portion 220. A through-electrode 200 connected to is disposed. That is, the through electrode 200 penetrating the second insulating portion 220 is arranged in a direction perpendicular to the surface on which the plurality of integrated semiconductor devices 10 are juxtaposed.

  That is, the integrated semiconductor device 10 is disposed in the outer region 102 around the inner region 101, and penetrates at least the outer region 102 through the through electrode 200 that electrically connects the first main surface 301 and the second main surface 302. And a second insulating part 220 disposed around the electrode 200.

  In the above, the second insulating portion 220 does not have to be disposed in all the regions of the outer region 102, and can be disposed at least around the through electrode 200 in the outer region 102 as described later. .

For the first insulating part 210 and the second insulating part 220, for example, an organic insulating material such as an epoxy resin can be used.
Further, the content ratio of the quartz filler in the second insulating portion 220 is set lower than the content ratio of the quartz filler in the first insulating portion 210.
For example, in the case of the integrated semiconductor device 10, an epoxy resin containing 80% quartz filler can be used for the first insulating portion 210, and an epoxy resin containing no quartz filler can be used for the second insulating portion 220. However, the present invention is not limited to this, and the quartz filler content ratio of the second insulating portion 220 may be lower than the quartz filler content ratio of the first insulating portion 210. In addition, in this invention, the case where the content rate of the quartz filler of the 2nd insulation part 220 is zero, ie, the case where the 2nd insulation part 220 does not contain a quartz filler is also included.

  For example, the content ratio of the quartz filler in the first insulating portion 210 can be 50% or more, and the content ratio of the quartz filler in the second insulating portion can be less than 50%. Furthermore, the first insulating portion It is particularly preferable that the content ratio of the quartz filler 210 is 50% or more and 80% or less, and the content ratio of the quartz filler of the second insulating portion 220 is 20% or less.

For the first insulating part 210 and the second insulating part 220, an organic insulating material such as an epoxy resin, a polyimide resin, or benzocyclobutene (BCB) can be used. Further, different organic insulating materials can be used for the first insulating part 210 and the second insulating part 220. For example, the first insulating part 210 and the second insulating part 220 may include at least one selected from the group consisting of an epoxy resin, a polyimide resin, and benzocyclobutene (BCB). It is also possible to change the content ratio of the quartz filler in the organic insulator, and it is also possible to change the content ratio of the quartz filler using an organic insulator of a different material system.
Furthermore, it is possible to change the type, shape, particle size, etc. of the quartz filler contained in the first insulating part 210 and the second insulating part 220. At this time, it is particularly desirable that the quartz filler contained in the second insulating portion 220 has at least one of the average particle size and the maximum particle size smaller than the quartz filler contained in the first insulating portion 210.

  In addition, the integrated semiconductor device 10 is configured such that the integrated semiconductor device 10 is electrically connected to an electric circuit different from the integrated semiconductor device 10 by a bump electrode or the like disposed in contact with the I / O electrode 170. It can be operated.

FIG. 2 is a schematic partial cross-sectional view illustrating a through hole formation state in the integrated semiconductor device according to the first embodiment of the invention.
2 and the subsequent drawings, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description will be omitted as appropriate.
2A and 2B illustrate the states before and after the through-hole forming step in the integrated semiconductor device 10 according to the first embodiment.

As illustrated in FIG. 2A, in the integrated semiconductor device 10, the inner region 101 on which the integrated circuit chip 105 is mounted has a high content of the quartz filler 212 (80% in this example). An insulating part 210 is arranged. In the outer region 102 around the inner region 101, a second insulating portion 220 having a low quartz filler content (0% in this example) is disposed.
Then, as shown in FIG. 2B, a through hole 201 for forming a through electrode 200 (not shown) is provided in the second insulating portion 220 having this structure by, for example, laser processing. At this time, since the content ratio of the quartz filler in the second insulating portion 220 is low (0% in this example), the through hole 201 can be easily formed, and the formation defect of the through hole 201 does not substantially occur.

  As described above, in the integrated semiconductor device 10 according to the present embodiment, the through electrode 200 is disposed in the second insulating part 220 having a low content of the quartz filler, thereby penetrating the quartz filler when forming the through electrode 200. As a result, the formation failure of the through electrode 200 can be reduced.

  Note that the thermal and mechanical strength of the second insulating portion 220 is reduced by arranging the through electrode 200, but the thermal resistance outside the inner region 101 where the integrated circuit chip 105 and the I / O electrode 170 are arranged is reduced. Since the second insulating portion 220 is disposed in the outer region 102 where the generated thermal and mechanical stress due to the difference in expansion coefficient is difficult to concentrate, there is substantially no problem.

  On the other hand, by disposing the integrated circuit chip 105 and the I / O electrode 170 in the inner region 101 having the first insulating portion 210 having a high quartz filler content ratio and a high thermal and mechanical strength, a difference in thermal expansion coefficient is obtained. It is possible to maintain high reliability against the stress strain of the integrated semiconductor device 10 due to the above.

That is, the through electrode 200 is disposed in the peripheral portion (outer region 102) of the integrated semiconductor device 10 and the I / O electrode 170 is disposed in the inner region 101 in which the through electrode 200 is not disposed, whereby the through electrode 200 portion due to stress strain is provided. Destruction failure can be prevented. As a result, the reliability of the integrated semiconductor device 10 with respect to stress strain can be improved.
By disposing the through electrode 200 in the outer region 102, the connection reliability using the bump electrode is improved because it is not affected by stress deformation.
Since the through electrode 200 is not disposed in the central portion of the integrated semiconductor device 10 where stress strain is concentrated, the influence of the bump stress strain caused by the difference in thermal expansion coefficient can be eliminated, thereby further improving the reliability of the integrated semiconductor device. be able to.

  As described above, the integrated semiconductor device 10 according to the present embodiment can eliminate the through-hole defect that has been a problem until now, and can provide an integrated semiconductor device on which a highly reliable heterogeneous device can be mounted.

(First comparative example)
FIG. 3 is a schematic view illustrating the configuration of the integrated semiconductor device of the first comparative example.
FIG. 3A is a schematic plan view of the integrated semiconductor device of the first comparative example, and FIG. 3B is a schematic cross-sectional view taken along line AA ′ of FIG.
As shown in FIGS. 3A and 3B, in the integrated semiconductor device 91 of the first comparative example, the insulating portion 230 containing the quartz filler at a high content ratio is arranged in the entire region. Yes. That is, not only the region where the integrated circuit chip 105 is disposed, but also the outer peripheral portion outside the region is provided with the insulating portion 230 containing the quartz filler in a high content ratio. Except for the insulating unit 230, the integrated semiconductor device 10 according to the first embodiment is the same as the integrated semiconductor device 10, and a description thereof is omitted.

FIG. 4 is a schematic partial cross-sectional view illustrating the formation of through holes in the integrated semiconductor device of the first comparative example.
That is, FIG. 4A illustrates the state before the through hole forming step in the integrated semiconductor device of the first comparative example. Moreover, FIG.4 (b) has illustrated the state after a through-hole formation process.
As shown in FIG. 4A, in the integrated semiconductor device 91 of the first comparative example, the insulating portion 230 having a high content ratio of the quartz filler 212 (80% in this example) is disposed throughout. Yes.
Then, as shown in FIG. 4B, when the through hole for forming the through electrode 200 (not shown) is provided in the insulating part 230 having this structure, for example, by laser processing, the insulating part Since 230 is filled with a quartz filler at a high content ratio, it is difficult to form a through hole. For example, as illustrated in FIG. A hole 202 is formed as a void. Further, as illustrated in FIG. 4B, there is a problem that the diameter of the hole 202 is not uniform. Furthermore, as illustrated in FIG. 4B, the quartz filler 212 remains on the wall surface of the hole 202, and the through-hole formation defect occurs, for example, the shape of the hole 202 becomes non-uniform.

  On the other hand, as already described, in the integrated semiconductor device 10 of the present embodiment, since the content ratio of the quartz filler of the second insulating part 220 forming the through hole 201 is lower than that of the first insulating part 210, the through-hole is penetrated. The formation failure of the hole 201 does not substantially occur.

(Second comparative example)
In contrast to the first comparative example, the integrated semiconductor device of the second comparative example has an insulating portion 240 (not shown) containing a quartz filler in a low content ratio in the entire region. That is, not only the outer peripheral portion on the outer side but also the inner region where the integrated circuit chip 105 is placed is provided with the insulating portion 240 having a low content of quartz filler (10% in this example). Except for the insulating part 240, the integrated semiconductor device 10 according to the first embodiment is the same as the integrated semiconductor device 10, and a description thereof will be omitted.

  In the integrated semiconductor device 92 having such a configuration, the insulating portion 240 in the inner region where the integrated circuit chip 105, the I / O electrode 170, and the like are disposed has a low content of quartz filler. There is a problem that the mechanical properties such as the above are low and the stress strain reliability is not sufficient as an integrated semiconductor device.

  On the other hand, in the integrated semiconductor device 10 according to the present embodiment, the integrated circuit chip 105 and the I / O electrode 170 have a high quartz filler content ratio and high mechanical properties such as a thermal expansion coefficient and a Young's modulus. Since it is arranged in the inner region 101 having the first insulating portion 210 having a high thermal and mechanical strength, the amount of displacement due to the difference in thermal expansion coefficient can be reduced, so that the stress strain of the integrated semiconductor device 10 High reliability can be effectively maintained.

(Third comparative example)
FIG. 5 is a schematic cross-sectional view illustrating the configuration of the main part of the integrated semiconductor device of the third comparative example.
An integrated semiconductor device 93 as a third comparative example has a through-hole 209 formed by forming a through-hole in a silicon substrate and filling the through-hole with metal. FIG. It is an expansion schematic cross section of 209 and its peripheral region.
As shown in FIG. 5, in the integrated semiconductor device 93 of the third comparative example, a through hole (not shown) is disposed in the silicon substrate 109, and the through electrode 209 is formed by filling the through hole with metal. It is formed. In this case, it is necessary to form various barrier metals and a passivation layer 208 between the silicon substrate 109 and the through electrode 209, which causes a problem that the process is complicated and the manufacturing cost is expensive. Further, in this method, a region where the through hole is formed is limited, and there is a limit to integrating different types of devices having different electronic circuit configurations or external dimensions.

  On the other hand, in the integrated semiconductor device 10 according to the present embodiment, the through electrode 200 is disposed in the second insulating portion 220 mainly made of an organic insulator, so that a through hole for forming the through electrode 200 is formed. The formation process is easy and the manufacturing cost can be reduced. Furthermore, the only limitation regarding the region where the through hole is formed is that the region is formed in the outer region 102. Except this, the region where the through hole is formed is arbitrary. Thereby, in the integrated semiconductor device 10 according to the present embodiment, it is possible to integrate different types of devices having different electronic circuit configurations or external shapes.

Since the manufacturing method of the integrated semiconductor device according to this embodiment will be described in detail with reference to examples described later, the outline thereof will be described below.
In the method of manufacturing an integrated semiconductor device according to this embodiment, first, the integrated circuit chip 105 is mounted on a glass mask (integrated transfer substrate).
Next, in the region where the integrated circuit chip 105 is mounted, a first insulating material having a high quartz filler content is formed by, for example, a known printing method to form the first insulating portion 210. Then, a second insulating material having a low (or not containing) quartz filler content is formed in the outer region by, for example, a known printing method to form the second insulating portion 220. In addition, the formation method of the 1st insulating part 210 and the 2nd insulating part 220 is not restricted to a printing method, For example, the inkjet method etc. can be used. Further, the order of forming the first insulating part 210 and the second insulating part 220 is arbitrary, and they can be formed simultaneously.
Next, an electrode portion for electrical connection is exposed at a predetermined portion by exposure through a glass mask and development, and an insulating layer is formed in a predetermined pattern.
Next, a fine wiring layer 280 for electrical connection between the LSI chip 110 and the MEMS chip 120 is formed.
Next, a MEMS sealing material (MEMS cap 290) for protecting the MEMS chip 120 is formed, and the MEMS chip 120 is sealed.
By such a manufacturing method, the integrated semiconductor device 10 of this embodiment illustrated in FIG. 1 can be formed.

FIG. 6 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention.
As shown in FIG. 6, in another integrated semiconductor device 11 according to the first embodiment of the present invention, the first insulating portion 210 is arranged in the inner region 101 where the integrated circuit chip 105 is mounted, and the inner region. The through electrode 200 and the second insulating portion 220 are disposed in the outer regions 102 on the upper and lower sides of the 101. The second insulating part 220 is disposed around the through electrode 200. That is, in the integrated semiconductor device 10 illustrated in FIG. 1, the second insulating portion 220 and the through electrode 200 are arranged over the four sides of the outer peripheral portion of the integrated semiconductor device 10, whereas in FIG. In the illustrated integrated semiconductor device 11, the second insulating part 220 and the through electrode 200 are disposed in the upper and lower two side regions. Since the integrated semiconductor device 11 can be the same as the integrated semiconductor device 10 except for the difference in the planar arrangement, description of other parts is omitted.

  As described above, the second insulating portion 220 and the through electrode 200 do not need to be disposed over the entire periphery of the integrated semiconductor device, and the through electrode 200 is formed from the inner region 101 on which the integrated circuit chip 105 is mounted. If it is the outer side area | region 102 outside, the place to arrange | position is arbitrary, For example, it can arrange | position to any one side of two upper and lower sides, two right and left sides, or the upper and lower sides and right and left. However, in order to average the stress, it is desirable to arrange it in a substantially symmetrical region on the left and right or top and bottom.

  As a result, the integrated semiconductor device 11 can eliminate the through-hole defect and provide an integrated semiconductor device on which a highly reliable heterogeneous device can be mounted.

FIG. 7 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention.
As shown in FIG. 7, in another integrated semiconductor device 12 according to the first embodiment of the present invention, the first insulating portion 210 is disposed in the inner region 101 where the integrated circuit chip 105 is mounted, and the inner region In the outer region 102 outside 101 (illustrated by a broken line in the figure), through electrodes 200 and second insulating portions 220 are arranged at four corners of the integrated semiconductor device 12. In this example, the first insulating portion 210 extends and is disposed in the outer region 102 (four sides other than the four corners) where the through electrode 200 is not disposed. Since it can be the same as that of the integrated semiconductor device 10 except the difference in this planar arrangement, description of other parts is abbreviate | omitted.

  As described above, the through electrode 200 may be arranged in any location as long as it is an outer region around the inner region 101 on which the integrated circuit chip 105 is mounted. Further, the through electrodes 200 are not necessarily arranged in a linear shape, and any location can be arranged as long as they are the outer region 102, and can also be arranged independently as a region.

In the integrated semiconductor device 12 illustrated in FIG. 7, the through electrode 200 is arranged at four corners. However, the upper and lower or left and right corners, the upper left and lower right corners, the upper right and It can be arranged at the lower left corner or at any one of the upper, lower, left and right corners. However, in order to average the stress, for example, it is desirable to arrange in a region that is substantially symmetric in the left-right or up-down direction or substantially point-symmetric. Furthermore, although the example of FIG. 7 is an example in which four through electrodes 200 are arranged at four corners, the number of through electrodes 200 at each corner is arbitrary. Further, the through electrode 200 is not necessarily arranged at the corner, and may be arranged at any one of the four sides, for example, at the central portion.
As a result, the integrated semiconductor device 12 can solve the through-hole defect and provide an integrated semiconductor device on which a highly reliable different device can be mounted.

FIG. 8 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention.
As shown in FIG. 8, in another integrated semiconductor device 13 according to the first embodiment of the present invention, the first insulating portion 210 is disposed in the inner region 101 where the integrated circuit chip 105 is mounted, and the inner region A through electrode 200 is disposed in the outer region 102 outside 101 (illustrated by a broken line in the figure). The second insulating portion 220 is disposed at least around the through electrode 200 in the outer region 102. In this example, the first insulating portion 210 extends and is disposed in the outer region 102 other than the periphery of the through electrode 200. Since it can be the same as that of the integrated semiconductor device 10 except the difference in this planar arrangement, description of other parts is abbreviate | omitted.

As described above, the second insulating portion 220 may be disposed around the through electrode 200, whereby the through hole 201 when forming the through electrode 200 can be easily formed.
As a result, the integrated semiconductor device 12 can solve the through-hole defect and provide a highly reliable integrated semiconductor device on which different types of devices can be mounted.

FIG. 9 is a schematic cross-sectional view illustrating the configuration of the main part of another integrated semiconductor device according to the first embodiment of the invention.
As shown in FIG. 9, another integrated semiconductor device 14 according to the first exemplary embodiment of the present invention further includes a bump electrode 180 arranged in contact with the I / O electrode 170. The bump electrode 180 is intended to operate the integrated semiconductor device 10 by making an electrical connection with an electric circuit different from the integrated semiconductor device 10.
In the figure, the I / O electrode 170 and the bump electrode 180 are arranged on both the first main surface 301 and the second main surface 302 of the integrated semiconductor device 14, but are arranged on either one of them. May be.
A part of the I / O electrode 170 is electrically connected to a fine wiring layer 280 that electrically connects the integrated circuit chips 105.

  The bump electrode 180 is, for example, a material containing at least one selected from the group consisting of Ti, Ni, Al, Cu, Au, Ag, Pb, An, and Pd, and selected from the group. Further, an alloy containing at least two can be used.

  Further, Cu / Ni / Ti can be used for the barrier metal of the bump electrode 180. However, the present invention is not limited to these metals. For example, a material including at least one selected from the group consisting of Cu, Ni, Pa and W, and an alloy including at least two selected from the group may be used. it can.

(First embodiment)
A first example of the integrated semiconductor device according to this embodiment will be described below.
The first example has the same configuration as that of the integrated semiconductor device 10 according to this embodiment illustrated in FIG. This will be described below with reference to FIG.
As shown in FIGS. 1A and 1B, in the integrated semiconductor device 18 according to the first embodiment, as the integrated circuit chip 105, five LSI chips 110 and one MEMS chip 120 are used. Is installed. Further, in this example, the LSI chip 110 includes two CPUs, two drivers, and one memory. Further, the LSI chip 110 and the MEMS chip 120 are interconnected by a fine wiring layer 280.

A first insulating portion 210 is disposed between the LSI chip 110 and the MEMS chip 120 on the back surface thereof (second main surface 302 in this example). That is, the first insulating portion 210 is arranged in the inner region 101 where the LSI chip 110 and the MEMS chip 120 are mounted. A second insulating portion 220 is disposed on the outer peripheral portion of the integrated semiconductor device 18. That is, the second insulating portion 220 is disposed in the outer region 102 around the inner region 101.
Further, a penetrating electrode 200 that electrically connects the first main surface 301 and the second main surface 302 of the integrated semiconductor device 10 is disposed in the portion of the second insulating portion 220 on the outer peripheral portion.

  In this embodiment, an epoxy resin containing 80% quartz filler is used for the first insulating portion 210, and an epoxy resin containing no quartz filler is used for the second insulating portion 220. Further, Al / Ti is used for the fine wiring layer 280.

  Further, the I / O electrode 170 of the integrated semiconductor device 18 is disposed in a region (inner region 101) inside the region (outer region 102) in which the through electrode 200 is disposed. A bump electrode 180 is disposed on the top. In this embodiment, PbSn alloy solder is used as the bump electrode 180, and Cu / Ni / Ti is used as the barrier metal of the bump electrode 180. As already described, the present invention is not limited to these metals, and various materials described above can be used for the bump electrode 180 and the barrier metal.

The external dimension of the integrated semiconductor device 18 of this embodiment is 10 mm × 15 mm.
The integrated semiconductor device 18 of this embodiment is an example in which the LSI chip 110 and the MEMS 120 are mounted as the integrated circuit chip 105, but the number of integrated circuit chips 105 to be mounted is arbitrary.
Furthermore, in the integrated semiconductor device 18, the LSI chip 110 is a CPU, a driver, and a memory, but the present invention is not limited to this.

Hereinafter, a method for manufacturing the integrated semiconductor device 18 of this embodiment will be described.
FIG. 10 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the integrated semiconductor device according to the first example of the invention.
11 is a schematic cross-sectional view in the order of steps following FIG. 10, FIG. 12 is a schematic cross-sectional view in the order of steps following FIG. 11, and FIG. 13 is a schematic cross-sectional view in the order of steps following FIG.
FIG. 10A illustrates the initial state in the manufacturing process. FIG. 10B is a diagram following FIG. 10A, and FIG. 10C is a diagram following FIG. 10B. is there. 11 (a) to 11 (c) are diagrams subsequent to FIG. 10 (c), and FIGS. 12 (a) to 12 (c) are diagrams subsequent to FIG. 11 (c). )-(C) is a figure following FIG.12 (c).

  In the manufacturing method of the integrated semiconductor device 18 of the first embodiment of the present invention, first, as shown in FIG. 10A, five LSI chips 110, one MEMS chip 120, and a predetermined A glass mask (integrated transfer substrate) 250 having a light shielding pattern 253 is manufactured by an individual process. In the glass mask 250, an organic insulating film 252 having an in-plane adhesive strength difference is formed on the main surface of the LSI chip 110. In this embodiment, a polyimide resin is used as the organic insulating film 252 for explanation.

  Next, as illustrated in FIG. 10B, the LSI chip 110 and the MEMS chip 120 are arranged on the glass mask 250 so that the main surfaces of the LSI chip 110 and the MEMS chip 120 are substantially flush with each other. .

  Next, as illustrated in FIG. 10C, the gap between the LSI chip 110 and the MEMS chip 120 and the back surface of the LSI chip 110 and the MEMS chip 120 are used as the first insulating material that becomes the first insulating unit 210. Then, it is coated with an epoxy resin containing 80% quartz filler. For the coating formation of the epoxy resin, it is preferable to use a vacuum printing technique.

Next, as shown in FIG. 11A, by using the same method, an epoxy resin containing no quartz filler is used as the second insulating material to be the second insulating portion 220, and the above-mentioned quartz filler content ratio is 80%. The coating is formed around the epoxy resin.
In addition, when a printing method is used as this coating formation method, the printing mask is not particularly limited, but a metal mesh mask having a large opening diameter is preferably used. In addition, not only a printing method but various methods of applying resin, such as an inkjet method, can also be used.

  Next, as shown in FIG. 11B, after the first insulating material and the second insulating material are cured in a high temperature clean oven in this state to form the first insulating portion 210 and the second insulating portion 220, A through hole 201 is formed at a predetermined location of the second insulating part 220. Laser processing can be used as a method of forming the through hole 201, but the laser used for the laser processing is not particularly limited, and for example, a carbon dioxide laser can be used.

  Next, as illustrated in FIG. 11C, the through electrode 201 is formed by filling the opened through hole 201 with a conductive material. In the case of this example, Cu was filled in the through hole 201 by electroplating. However, the filling method of the conductive material is not limited to this, and various methods such as a metal paste filling method and a molten metal filling method such as solder can be used.

  Next, as shown in FIG. 12A, after forming an insulating layer, a fine wiring layer 150 made of Al / Ti is formed. In the present embodiment, Al / Ni is used for explanation, but it is not limited to these metals. For example, it is made of Ti, Ni, Al, Cu, Au, Pb, Sn, Pd and W. An alloy having at least one selected from a group or at least two selected from the group can be used.

Next, as shown in FIG. 12B, the LSI chip 110 and the MEMS chip 120 are exposed by the exposure light 254 from the main surface of the glass mask 250 in a state where the LSI chip 110 and the MEMS chip 120 are positioned and mounted on the glass mask 250. . The exposure is performed according to the sensitivity of the photosensitive resin that becomes the organic insulating film 252 constituting the multilayer wiring. When polyimide (trade name Photo Nice UR series, manufactured by Toray Industries, Inc.) is used as the photosensitive resin to be the organic insulating film 252, exposure energy of about 100 mJ / cm ² is preferable.

  Next, as shown in FIG. 12C, after removing the glass mask 250, development is performed using a developer (trade name: VD-505 manufactured by Toray Industries, Inc.), and the LSI chip 110 and the MEMS chip 120 The photosensitive resin on the region corresponding to the external connection terminal 171 that connects the two is selectively removed to form the opening 255.

Further, as shown in FIG. 13A, a thin film metal for connecting the external connection terminal 171 is formed on the organic insulating film by a known technique, and the contact via 140 is formed. In this embodiment, Al / Ti is used as the thin film metal, but the thin film metal is not limited to these metals. For example, a group consisting of Ti, Ni, Al, Cu, Au, Pb, Sn, Pd, and W is used. An alloy containing at least one selected from the above or at least two selected from the group can be used.
Note that FIGS. 13A to 13C are drawn upside down with respect to the figure before 12C for the sake of explanation.

  Thereafter, as shown in FIG. 13B, after photosensitive polyimide and Al / Ti are laminated together, the uppermost layer is covered with a polyimide film to form an opening 256 corresponding to the I / O electrode. To do.

  Next, after forming a Cu / Ti film by EB (Electron Beam) vapor deposition on the polyimide film, a thick film plating resist AZ4903 (manufactured by Hoechst Japan Co., Ltd.) is formed with a film thickness of 50 μm by spin coating, and exposure and By development, an opening of 80 μm larger than the I / O electrode having an opening size of 50 μmφ is formed. For the exposure, a sufficient amount of energy was applied to the resist thickness, and for development, an AZ400K developer (manufactured by Hoechst Japan) was used.

Next, it is immersed in the following Pb / Sn plating solution, and plating is performed using Ni / Ti as a cathode and a high-purity eutectic solder plate corresponding to the following electroplating solution, for example, as an anode. At this time, the current density is 1 to 4 (A / dm ² ), the bath temperature is 25 ° C., and the solder composition (Pb / Sn) is approximately equal to the eutectic composition while gently stirring, or Pb A solder alloy having a composition slightly shifted to the Sn or Sn side was deposited on the Ni / Ti layer at a thickness of 50 μm.

Composition of sulfonic acid solder plating solution
Tin ions ^_(Sn 2 +) _12vol%
Lead ions ^_(Pb 2 +) 30vol%
Aliphatic sulfonic acid 41 vol%
Nonionic surfactant 5 vol%
Cationic surfactant 5 vol%
Isopropyl alcohol 7vol%
Next, the electroplating resist is removed with acetone, and further immersed in a solution composed of citric acid / hydrogen peroxide solution to remove Cu by etching, and then ethylenediaminetetraacetic acid / ammonia / hydrogen peroxide solution / pure water. Ti was removed by immersion in a mixed solution composed of
By installing the bump electrode 180 by the above process, the integrated semiconductor device 18 shown in FIG. 13C and FIG. 1 was manufactured.

  With the integrated semiconductor device 18 of the embodiment manufactured by such a process, a through-hole defect can be eliminated, and an integrated semiconductor device on which a highly reliable heterogeneous device can be mounted can be provided.

(Second Embodiment)
FIG. 14 is a schematic cross-sectional view illustrating the configuration of an integrated three-dimensional semiconductor device according to the second embodiment of the invention.
As shown in FIG. 14, the integrated three-dimensional semiconductor device 20 according to the second embodiment of the present invention includes an integrated semiconductor device 18 according to the first embodiment and another semiconductor stacked on the integrated semiconductor device 18. Device 400. Further, the integrated semiconductor device 18 and the semiconductor device 400 are connected by a bump electrode 180.
That is, the integrated three-dimensional semiconductor device 20 according to the present embodiment is an integrated semiconductor device in which the integrated semiconductor device and the integrated semiconductor device are three-dimensionally mounted.

  In this example, the semiconductor device 400 includes two semiconductor substrates, that is, a first LSI circuit wiring board 410 and a second LSI circuit wiring board 420. However, the present invention is not limited to this, and the number of semiconductor devices 400 is arbitrary. It is also possible to stack a plurality of integrated semiconductor devices according to the first embodiment.

  Such an integrated three-dimensional semiconductor device 20 can provide an integrated three-dimensional semiconductor device in which a highly reliable heterogeneous device in which a through hole defect is eliminated can be mounted.

(Second embodiment)
Hereinafter, the integrated three-dimensional semiconductor device according to the second example of the embodiment will be described. The integrated three-dimensional semiconductor device 21 of the second embodiment has the structure illustrated in FIG.
That is, it is a structure of an integrated three-dimensional semiconductor device in which the integrated semiconductor device 18 of the first embodiment, the first LSI circuit wiring board 410, and the second LSI circuit wiring board 420 are stacked. A CPU chip is mounted on the first LSI circuit wiring board 410, and a memory chip is mounted on the second LSI circuit wiring board 420. However, the present invention is not limited to this. For example, a driver chip or the like may be mounted, and the type of LSI chip is not particularly limited.

Hereinafter, a method for manufacturing the integrated three-dimensional semiconductor device 21 of this embodiment will be described.
First, the bump electrode 180 of the integrated semiconductor device 18 and the electrode terminal of the first LSI circuit wiring board 410 are aligned using a flip chip bonder that performs alignment using a known half mirror. The integrated semiconductor device 18 is held by a collet having a heating mechanism and preheated in a nitrogen atmosphere at 350 ° C.

Next, with the bump electrode 180 of the integrated semiconductor device 18 and the electrode terminal of the first LSI circuit wiring board 410 in contact with each other, the collet is moved downward, a pressure of 30 kg / mm ² is applied, and the temperature is increased to 370 in this state. The temperature is raised to ° C. to melt the solder, and the integrated semiconductor device 18 and the electrode terminal of the first LSI circuit wiring board 410 are connected.
The second LSI circuit wiring board 420 is connected to the first LSI circuit wiring board 410 using a similar method.
Through the above steps, the integrated three-dimensional semiconductor device 21 of this embodiment shown in FIG. 14 can be formed.

If necessary, a sealing resin, which is a known technique, can be disposed in the gap between the integrated semiconductor device 18, the first LSI circuit wiring board 410, and the second LSI circuit wiring board 420. As this sealing resin, for example, an epoxy resin in which a spherical quartz filler is added at a weight ratio of 45 wt% to a resin composed of a bisphenol-based epoxy, an imidazole curing catalyst, and an acid anhydride curing agent can be used.
Further, for example, 100 parts by weight of a cresol novolac type epoxy resin (trade name ECON-195XL: manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of a phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, and as a catalyst It is also possible to use an epoxy resin melt obtained by pulverizing, mixing, and melting 0.5 part by weight of benzyldimethylamine, 3 parts by weight of carbon black as an additive, and 3 parts by weight of a silane coupling agent. It is not something.

Next, a connection reliability test result of the integrated three-dimensional semiconductor device 21 of this embodiment will be described.
In this connection reliability test, the number of input / output pins of the integrated three-dimensional semiconductor device 21 is 256 pins, and a case where the connection is open even at one of the 256 pins is defined as defective.

  The number of samples was 1000, and the temperature cycle test conditions were as follows: one temperature cycle was performed at −55 ° C. for 30 minutes to 25 ° C. for 5 minutes to 125 ° C. for 30 minutes to 25 ° C. for 5 minutes.

  Further, as a fourth comparative example, an integrated three-dimensional semiconductor device 94 in which the through electrode 200 is an outer region having a quartz filler content ratio of 80% with respect to the integrated three-dimensional semiconductor device 21 of the second embodiment described above. An integrated three-dimensional semiconductor device using the configuration illustrated in FIG. 3 was manufactured, and a temperature cycle test was performed in the same manner as the integrated three-dimensional semiconductor device 21 of this example.

  As a result, in the integrated three-dimensional semiconductor device 94 of the fourth comparative example, the destruction of the insulating material portion that fixedly holds the LSI chip 110 and the MEMS chip 120 was confirmed at a rate of 100% in 1500 cycles.

On the other hand, in the integrated three-dimensional semiconductor device 21 of this example, no breakdown failure was confirmed even after 3000 cycles.
In the integrated three-dimensional semiconductor device 21 of the present embodiment, the I / O electrode 170 and the bump electrode 180 are disposed in the inner region 101, thereby causing stress breakdown due to deformation of the integrated three-dimensional semiconductor device 21 due to the temperature cycle. It is thought that it was able to be prevented.
Thus, it was confirmed by the temperature cycle test that the connection reliability of the integrated three-dimensional semiconductor device 21 of this example was extremely high.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the integrated semiconductor device and the integrated three-dimensional semiconductor device, those skilled in the art can implement the present invention in the same manner by appropriately selecting from a well-known range and obtain the same effect. Is included in the scope of the present invention as long as possible.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the integrated semiconductor device and the integrated three-dimensional semiconductor device described above as the embodiments of the present invention, all integrated semiconductor devices and modified three-dimensional semiconductor devices that can be implemented by those skilled in the art with appropriate design changes are also included in this book. As long as the gist of the invention is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a schematic view illustrating the configuration of an integrated semiconductor device according to a first embodiment of the invention. FIG. 3 is a schematic partial cross-sectional view illustrating a through hole formation state in the integrated semiconductor device according to the first embodiment of the invention. It is a schematic diagram which illustrates the structure of the integrated semiconductor device of a 1st comparative example. It is a typical fragmentary sectional view which illustrates the formation state of the penetration hole in the integrated semiconductor device of the 1st comparative example. It is a schematic cross section which illustrates the structure of the principal part of the integrated semiconductor device of a 3rd comparative example. FIG. 6 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic plan view illustrating the configuration of another integrated semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional view illustrating the configuration of a main part of another integrated semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the integrated semiconductor device according to the first example of the invention. FIG. 11 is a schematic cross-sectional view in order of the steps, following FIG. 10. FIG. 12 is a schematic cross-sectional view in order of the steps, following FIG. 11. FIG. 13 is a schematic cross-sectional view in order of the steps, following FIG. 12. FIG. 6 is a schematic cross-sectional view illustrating the configuration of an integrated three-dimensional semiconductor device according to a second embodiment of the invention.

Explanation of symbols

10, 11, 12, 13, 14, 18, 91, 93 Integrated semiconductor device 20, 21, 94 Integrated three-dimensional semiconductor device 101 Inner region 102 Outer region 105 Integrated circuit chip 109 Silicon substrate 110 LSI chip 120 MEMS chip 140 Contact via 150 Fine wiring layer 170 I / O electrode (input / output unit)
171 External connection terminal 180 Bump electrode 200, 209 Through electrode 201 Through hole 202 Hole 208 Passivation layer 210 First insulating part 212 Quartz filler 220 Second insulating part 230, 240 Insulating part 250 Glass mask 252 Organic insulating film (insulating layer)
253 Light-shielding pattern 254 Exposure light 255, 256 Opening 280 Fine wiring layer 290 MEMS sealing material (MEMS cap)
301 First Main Surface 302 Second Main Surface 400 Semiconductor Device 410 First LSI Circuit Wiring Board 420 Second LSI Circuit Wiring Board

Claims (8)

An integrated semiconductor device comprising a plurality of integrated circuit chips,
The plurality of integrated circuit chips juxtaposed in the inner region;
A first insulating portion filled around each of the plurality of integrated circuit chips, holding the plurality of integrated circuit chips, and containing a quartz filler;
A wiring layer disposed on a surface of the inner region and connected to at least one of the plurality of integrated circuit chips;
An input / output unit disposed in the inner region and connecting at least one of the plurality of integrated circuit chips and an external circuit;
A second insulating portion disposed in at least a part of the outer region around the inner region and having a lower quartz filler content ratio than the first insulating portion;
A through electrode penetrating the second insulating portion and connecting the front surface and the back surface;
An integrated semiconductor device comprising:   The second insulating portion contains a quartz filler, and the quartz filler contained in the second insulating portion is at least one of an average particle size and a maximum particle size as compared with the quartz filler contained in the first insulating portion. 2. The integrated semiconductor device according to claim 1, wherein:   3. The integrated semiconductor device according to claim 1, wherein the first insulating portion and the second insulating portion include at least one selected from the group consisting of epoxy resin, polyimide resin, and benzocyclobutene. .   The integrated semiconductor device according to claim 1, wherein at least any two of the plurality of integrated circuit chips are different from each other in at least one of an electronic circuit configuration and an external dimension.   5. The integrated semiconductor device according to claim 1, wherein at least one of the plurality of integrated circuit chips is an electromechanical element.   6. The integrated semiconductor device according to claim 1, further comprising a bump electrode electrically connected to the input / output unit.   The bump electrode is at least one selected from the group consisting of Ti, Ni, Al, Cu, Au, Ag, Pb, Sn, Pd, Pd, and W, or Ti, Ni, Al, Cu, Au, Ag. 7. The integrated semiconductor device according to claim 6, comprising an alloy composed of at least two selected from the group consisting of Pb, Sn, Pd, Pd, and W. An integrated semiconductor device according to any one of claims 1 to 7,
A semiconductor device stacked with the integrated semiconductor device and electrically connected to at least one of the plurality of integrated circuit chips;
An integrated three-dimensional semiconductor device comprising:

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