JP2009233356A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the removal of noises carried by signal lines for connection between a detector and each of a plurality of controllers while enabling the individual controllers to simultaneously receive a detection signal output from the detector in a game machine with the detector and the plurality of controllers for receiving the detection signal to be output from the detector. <P>SOLUTION: The plurality of signal lines each includes filter circuits 170 and 214. The filter circuits 170 and 214 are required to make the state of input signals to the filter circuits 170 and 214 as prescribed and signals are output when the state is maintained for a prescribed period of time. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gaming machine including a detection device that detects a state of a gaming machine and a plurality of control devices that receive detection signals output from the detection device. Specifically, the detection signals output from the detection device are The present invention relates to a technique for correctly receiving data by a control device.

  For example, for a highly-equipped gaming machine such as a pachinko machine, a main control device that controls the entire gaming machine, a sub-control device that controls each electrical equipment (for example, symbol display, payout device, etc.), etc. A plurality of control devices are provided as described above. These control devices are individually connected to a detection device (for example, a power failure detection device) provided in the gaming machine by a signal line, and each control device is configured to directly receive a detection signal via this signal line. There is a case.

In the case as described above, the detection signal output from the detection device may be received by the control device at different timings depending on the configuration of each signal line connecting the detection device and each control device. Therefore, when it is desired to perform processing synchronized with each control device based on this detection signal, it is desirable that the detection signal is received simultaneously by each control device.
On the other hand, a lot of electrical equipment is installed in a game store where gaming machines are installed, and noise is likely to be generated, and it is often installed in an environment in which noise is likely to be applied to the signal line connecting the detection device and the control device. . When noise is applied to the signal line, the control device determines that the detection signal is output from the detection device even though the detection device does not output the detection signal. It becomes. Therefore, it is necessary to remove noise on the signal line. As a method for that purpose, a filter circuit constituted by an element such as a capacitor is generally provided on the signal line (FIG. 18A). reference).
However, when such a filter circuit is provided in the signal line and a detection signal is output from the detection device, charging or discharging of the capacitor of the filter circuit is caused by this detection signal. Therefore, the signal output from the filter circuit gradually changes with time as shown in FIG. 18B, but the temporal change rate of this output signal (the straight line shown in FIG. 18B). The slope of () varies greatly depending on the capacitor element and is not constant. Also, it is not easy to select a plurality of elements having the same characteristics. For this reason, even if the threshold value of the receiving element of each control device that receives the output signal is the same, the timing at which the detection signal is received by each control device is shifted.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to remove noise on a signal line connecting the detection device and each control device, and to detect each detection signal output from the detection device. Provided is a gaming machine that can be simultaneously received by a control device.

In order to solve the above-described problem, a gaming machine according to claim 1 includes a detection device, a plurality of control devices that receive detection signals output from the detection device, and each of the detection device and the plurality of control devices. In the gaming machine having a plurality of signal lines connecting the two, a filter circuit is provided for each of the plurality of signal lines.
The filter circuit is configured to output a signal when the state of the input signal to the filter circuit becomes a predetermined state and the state is maintained for a predetermined period.

According to the above gaming machine, in the filter circuit provided in each signal line connecting the detection device and each control device, the state of the input signal to the filter circuit becomes a predetermined state, and the state is maintained for a predetermined period. Sometimes configured to output a signal. Therefore, when an instantaneous signal such as noise is applied to the signal line, the state of the input signal to the filter circuit instantaneously becomes a predetermined state (signal ON state), but the state is predetermined. The period is not maintained. For this reason, no signal is output from the filter circuit, and the signal is not received by the control device. In addition, when the detection signal output from the detection device is input to the filter circuit, the state of the input signal to the filter circuit is a predetermined state (the signal is in an ON state), and the state is maintained for a predetermined period. Therefore, a signal is output from the filter circuit, and this signal is received by the control device.
The filter circuit is configured to output a signal when a predetermined period has elapsed after the state of the input signal changes (becomes a predetermined state), and the output signal is in an OFF state. Switches from ON to ON state instantaneously. For this reason, there are no problems such as variations in the temporal change rate (rise time, followability, etc.) of the output signal generated in the filter circuit using an analog element such as a capacitor, and each control device simultaneously outputs signals output from the filter circuit. Can be received.
The term “simultaneous” here does not mean completely simultaneous, but even when the timing of receiving the detection signal in each control device is deviated, such deviation can be ignored ( In the case where each control device can be synchronized), it is included in “simultaneous” here.

Here, the “detection device” may be any detection device provided in a gaming machine. For example, a detection device that detects a game medium (typically a prize ball in a pachinko machine). And a detection device (typically, a frame open sensor, a power failure detection device, etc. in a pachinko machine).
Here, as one preferable aspect of the gaming machine according to claim 1, the “detecting device” is a gaming machine that is a power failure detecting device that detects that power to the gaming machine is cut off.
That is, each control device must perform predetermined processing within a short period of time after receiving the detection signal (while power is supplied from the information storage circuit), and separately transmit and receive signals between the control devices. This is because it is difficult to adopt the method of synchronizing by the above.

In addition, the “control device” may be any control device provided in the gaming machine, for example, a main control device that controls the entire gaming machine, and electrical equipment attached to the gaming machine. There are sub-control devices (typically, a symbol control device that controls a symbol display in a pachinko machine, a prize ball control device that controls a payout device, etc.).
Here, as one preferable aspect of the gaming machine according to claim 1, the “plurality of control devices” controls a main control device that controls the entire gaming machine and electrical equipment attached to the gaming machine. At least one of the sub-control devices is included, and the sub-control device is a gaming machine configured to control the electrical device based on a command transmitted from the main control device.
In such a configuration, the sub-control device may independently control the electrical equipment based on the detection signal output from the detection device (control the electrical equipment without being based on the command transmitted from the main control device). In such a case, it is necessary to cause both control devices to simultaneously receive detection signals. That is, the main control device assumes that the sub control device is also receiving the detection signal at the same time, and performs subsequent control (command transmission, etc.).

The “filter circuit” may be any circuit that is configured to output a signal when a state of an input signal to the filter circuit is in a predetermined state and the state is maintained for a predetermined period. You may comprise.
As such a filter circuit, for example, a noise removal circuit (for example, constituted by a shift register or the like) that removes an input signal for less than a predetermined period and a clock circuit that defines a determination cycle of the noise removal circuit are mainly configured. be able to.
In such a configuration, by shortening the cycle of the clock circuit, it is possible to reduce the deviation of the reception timing of the detection signal in each control device and improve the accuracy. In other words, in the filter circuit having the above-described configuration, when the predetermined period (predetermined number of clocks) is counted after the state of the input signal is changed, the clock signal in each filter circuit is shifted, thereby counting in each filter circuit. It is inevitable that the start timing is shifted and the signal output timing is shifted by one period (one clock). Therefore, by shortening the cycle of the clock circuit that defines the determination cycle of the noise removal circuit, such an inevitable timing shift can be reduced and the accuracy can be improved.
More preferably, when the filter circuit is configured as described above, the clock circuit of the filter circuit provided in each signal line is shared, that is, a clock signal is supplied from one clock circuit to a plurality of noise removal circuits. It is to be configured. According to such a configuration, the clock signal of the filter circuit provided in each signal line is shared, and the above-described problem of “shift in the count start timing for each filter circuit” can be eliminated. Therefore, each control apparatus can receive a detection signal simultaneously.
Note that the use of a heat-resistant crystal resonator, VCO, or the like as the clock circuit is particularly effective in a highly electronic gaming machine. This is because in highly-equipped gaming machines, heat is generated from various electrical equipment equipped in the gaming machine, and the clock circuit is also heated.

In the gaming machine according to claim 1, it is preferable that the control device and a filter circuit provided in a signal line to the control device are mounted on a single substrate.
According to such a configuration, it is possible to reduce the possibility of noise on the signal line between the filter circuit and the control device, and the filter circuit and the control device are mounted on one substrate. Wiring work between the detection device and the control device, attaching work of these devices to the gaming machine main body, and the like can be facilitated.

The signal transmission technology according to the present invention includes at least one part for controlling an electrical equipment disposed in a gaming machine (hereinafter simply referred to as a control unit) and a part for detecting the state of the gaming machine (hereinafter simply referred to as a detection unit). ) May be provided on the same substrate (device).
In such a case, the gaming machine according to a preferred aspect of the present invention includes a power failure detection unit that detects that power supply from an external power source is cut off, and a power failure signal output from the power failure detection unit. When it is received, the required information is stored, and when the power supply from the external power supply is restored, the gaming machine includes a plurality of control units that resume control based on the stored information, and is output from the power failure detection unit. The detected signal is input to the control unit via a digital filter circuit.
According to such a configuration, since each control unit can receive a power failure signal in synchronization, the operation of each control unit is performed without deviation when the power supply from the external power supply is restored.

The rear view which shows the back set board 11 deployed on the back surface side of the pachinko machine which concerns on this Embodiment, and its attachment The block diagram which shows the structure of the control part of the pachinko machine shown in FIG. The figure for demonstrating the structure of the power supply part 120. Circuit diagram of clock circuit constituting filter circuit Circuit diagram of the noise elimination circuit that composes the filter circuit A timing chart for explaining the operation of the noise removal circuit; Timing chart for explaining the operation of the noise removal circuit Flowchart explaining processing of main control unit in normal time Flowchart explaining processing of main control unit in normal time Flowchart explaining processing of main control unit in normal time Flow chart of processing in the prize ball control unit at normal time Flow chart of processing in the prize ball control unit at normal time Flow chart of processing in the prize ball control unit at normal time Flow chart of processing in the prize ball control unit at normal time Flowchart explaining processing of main control unit at power-off Flow chart of processing of prize ball control unit at power-off Flow chart of processing in main control unit and prize ball control unit when power is restored The figure which shows the example of the filter circuit which uses the capacitor element

An embodiment in which the present invention is applied to a pachinko machine (specifically, from a power failure detection unit to a main control unit and a prize ball control unit that controls a payout device (a device for paying a prize ball to a player)) A case where a power failure signal is transmitted) will be described with reference to FIGS. Here, FIG. 1 is a rear view showing the back set plate 11 and its accessories (dispensing device 30 and the like) provided on the back side of the pachinko machine according to the present embodiment, and FIG. 2 shows the present embodiment. FIG. 3 is a block diagram illustrating a configuration of a control unit of the pachinko machine, FIG. 3 is a diagram for explaining a configuration of the power supply unit 120, and FIG. 4 is a clock configuring a part of the filter circuit according to the present embodiment. FIG. 5 shows a circuit diagram of a noise removal circuit that constitutes a part of the filter circuit according to the present embodiment, and FIGS. 6 and 7 explain the operation of the noise removal circuit shown in FIG. 8 to 10 are flowcharts of processing in the main control unit, FIGS. 11 to 14 are flowcharts of processing in the prize ball control unit, and FIG. 15 is processing in the main control unit when power is shut off. In the flowchart Ri, Figure 16 is a flowchart of processing at power shutdown in prize balls controller, FIG. 17 is a flowchart of processing in the main control unit and Shodama controller when energized recovery.

First, the dispensing device 30 provided in the pachinko machine 10 will be described.
As shown in FIG. 1, the payout device 30 is disposed on a back set plate 11 attached to the back side of the pachinko machine 10. In addition to the payout device 30, the back set plate 11 includes a ball storage tank 13 for storing a large number of pachinko balls, and a guide rail 14 for guiding the pachinko balls stored in the ball storage tank 13 to the payout device 30. Is provided. The guide rail 14 has two spherical passages formed in parallel inside and outside, although not shown.

As shown in FIG. 1, the payout device 30 includes an upper sphere guide path 31a communicating with the guide rail 14, a rotating sphere receiver 34 provided near the downstream opening of the upper sphere guide path 31a, and the rotation It has two lower sphere guide paths 31b arranged below the ball receiver 34. The upper sphere guide path 31a, the rotating sphere receiving body 34, and the lower sphere guide path 31b are also provided adjacent to each other in pairs in and out, according to the fact that the guide rails 14 are formed in two rows. .
The rotating ball receiver 34 is formed with a number of concave portions (ball receiving portions) 34a (six locations in the figure) that can temporarily receive one pachinko ball, and the upper ball guiding path 31a passes through the ball receiving portion 34a. Pachinko balls that have been received are accepted one by one. The rotating ball receiver 34 is rotationally driven by a motor 25 (not shown: shown in FIG. 2). For this reason, when the motor 25 rotates, the pachinko balls received by the ball receiving portion 34a can be regularly dropped into the lower ball guide path 31b one by one. Since the rotating ball receivers 34 are formed in two rows (inside and outside) as already described, the pachinko balls are discharged from the inner and outer rotating ball receivers 34 to the lower guide path 31b. The timing at which pachinko balls are discharged from the two inner and outer rotating ball receivers 34 is adjusted so that the pachinko balls are not discharged from both rotating ball receivers 34 at the same time. That is, it is configured such that the discharge timing of the pachinko balls is shifted by providing the rotating ball receivers 34 provided inside and outside with a predetermined angle shifted from each other.
The upstream side portion of the lower ball guiding path 31b into which the pachinko balls discharged from the rotating ball receiving body 34 fall is divided into two, a winning ball guiding path 32a and a lending ball guiding path 32b. Whether the pachinko ball discharged / dropped from the ball receiving portion 34a according to the rotation direction of the rotating ball receiving body 34 falls into the winning ball guiding path 32a or into the lending ball guiding path 32b. Is determined.

  As a result of this configuration, pachinko balls stored in the ball storage tank 13 reach the rotating ball receiver 34 from the bottom of the ball storage tank 13 through the guide rail 14 and the upper ball guide path 31a. When the motor 25 is driven to rotate, the rotating ball receiver 34 rotates. As a result, the pachinko balls are one ball at a time in the lower ball guiding path 31b (the winning ball guiding path 32a or the lending ball guiding path 32b). ). That is, when paying out a prize ball to the player, the rotating ball receiver 34 rotates counterclockwise, so that the pachinko balls discharged from the rotating ball receiver 34 fall into the award ball guiding path 32a. . On the other hand, when the pachinko balls are paid out as rental balls, the rotating ball receiver 34 rotates clockwise, so that the pachinko balls discharged from the rotating ball receiver 34 fall into the rental ball guiding path 32b. The pachinko balls that have fallen into the award ball guiding path 32a and the lending ball guiding path 32b flow into the payout ball guiding path 35 and are discharged to an upper plate (not shown) provided on the front surface of the pachinko machine 10. .

  Further, the dispensing device 30 is provided with a rotation detection sensor 29 including a photo detector (photo coupler) adjacent to the above-described rotating ball receiver 34, thereby detecting the rotation of the rotating ball receiver 34. . That is, the rotating ball receiver 34 is provided with a disk-shaped position detection plate (not shown) that rotates integrally with the rotating ball receiver 34, and the plurality of ball receivers are provided at the periphery of the position detection plate. A plurality of slits corresponding to each of the portions 34a are provided at a constant interval (angle). The rotation detection sensor 29 is disposed at a predetermined position where the passage of the slit of the position detection plate can be detected when the position detection plate rotates. Therefore, every time one of the slits of the position detection plate passes the detection position of the rotation detection sensor 29, the rotation detection sensor 29 is turned on, and a rotation detection signal is output to the prize ball control unit 200 described later. That is, once for each rotation of the rotation angle at which one pachinko ball can be discharged from the ball receiving portion 34a (that is, 60 degrees in the rotating ball receiving body 34 according to the present embodiment having the six ball receiving portions 34a). The rotation detection signal is output to the winning ball control unit 200. The mechanism of the photo detector itself may be the same as that provided in a conventional pachinko machine (see, for example, Japanese Patent Laid-Open No. 9-1555035), and does not characterize the present invention. Description is omitted.

Further, the payout device 30 is provided with a prize ball detection sensor 27 (typically a proximity switch) for detecting a pachinko ball passing through the guidance path on the prize ball guiding path 32a. The prize ball detection sensor 27 is provided in each of the ball guidance paths 32a for prize balls provided in two rows inside and outside. When a pachinko ball passes through the prize ball guiding path 32a, a prize ball detection signal is output to the main control unit 100 and the prize ball control unit 200 described later.
Similarly, a lending ball detection sensor 28 (typically a proximity switch) that detects a pachinko ball passing through the lancing path is also provided in the lending ball guiding path 32b. This lending ball detection sensor 28 is also provided in each of lending ball ball guiding paths 32b provided in two rows inside and outside. When a pachinko ball passes through the lending ball guiding path 32b, a lending ball detection signal is output to the main control unit 100 and the prize ball control unit 200 described later.

Next, the configuration of a control system that controls the dispensing device 30 configured as described above will be described with reference to FIGS.
As shown in FIG. 2, the control system that controls the payout device 30 includes a main control unit 100 that controls the entire pachinko machine 10 and a prize ball control unit 200 that is electrically connected to the main control unit 100. . The main control unit 100 and the prize ball control unit 200 are electrically connected to the power source unit 120, and are configured to supply power from the power source unit 120 to the main control unit 100 and the prize ball control unit 200.

The power supply unit 120 includes a voltage transformer 140 that rectifies and smoothes the AC 24V power supplied from an external power source into a DC supply power of a voltage corresponding to each electrical component equipped in the pachinko machine 10, power failure, and the like. A power failure detection unit 130 is provided that outputs a power failure signal toward each control unit (main control unit 100, prize ball control unit 200, etc.) of the pachinko machine 10 when energization from an external power source is interrupted for a reason.
As shown in FIG. 3, the voltage transformer 140 includes rectifier circuits 142a and 142b that rectify the waveform of the AC 24V power supply, and smoothing circuits (diodes D1, D2, and D2) that smooth the pulsating waveform rectified by the rectifier circuits 142a and 142b. D3 and D4 and capacitors C1, C2, C3, and C4), and constant voltage circuits IC1, IC2, and IC3 that make the waveform smoothed by the smoothing circuit constant.
In such a voltage transformer 140, a signal of + 5V generated by the constant voltage circuit IC1 is supplied to the main controller 100 and the prize ball controller 200 at normal times. In addition, when the energization is cut off, such as a power failure, the power stored during energization of the capacitor C1 is supplied to the main control unit 100 and the prize ball control unit 200. It is possible to perform the process.
Further, the + 5V signal output from the constant voltage circuit IC1 is separated in parallel and connected to the information storage output terminal VBB via the diode D5 and the capacitor C5. The power stored in the capacitor C5 is supplied to the RAMs of the main control unit 100 and the prize ball control unit 200 when the energization is interrupted, such as a power failure, and the information stored in the RAM is held.
The power failure detection unit 130 shapes the waveform of the AC power supply AC (rectification, clipping, etc.), divides the voltage of the shaped waveform, detects the divided waveform (pulse wave), and generates a pulse. A power failure signal is output when a predetermined number of waves are missing.

The main control unit 100 is a control device that controls the operation of each device (electrical component) of the pachinko machine 10, and in addition to the prize ball control unit 200, a symbol display (not shown) arranged in the center of the game board. ) The symbol display control unit that performs symbol variation processing, the sound control unit that performs processing for generating sound effects and BGM from the speaker, the lamp control unit that performs lighting driving processing of the lamps mounted inside and outside the game board, etc. Electrically connected. The mechanism of each control unit is the same as that in a conventional pachinko machine, and the description thereof is omitted here.
As shown in FIG. 2, the main control unit 100 includes a CPU 102, a ROM 104, a RAM 106, an input processing circuit 108, a communication control circuit 112, and a filter circuit 170 connected to the CPU 102 via a bus 114 (referred to in the claims). Filter circuit).
The CPU 102 controls the pachinko machine 10 by executing a game control program stored in the ROM 104. This game control program includes a control program for creating various commands to be transmitted to each control unit such as the prize ball control unit 200 and transmitting commands to each control unit.
The RAM 106 stores various data and input / output signals. In the RAM 106, as will be described later, a winning number counter for counting the number of pachinko balls won in various winning openings provided on the front side of the game board, and a winning ball created based on the winning number counter A command to be transmitted to the control unit 200 and a transmission ball number counter for accumulating the number of pachinko balls ordered to be paid out to the prize ball control unit 200 based on the command are stored.
Further, the input processing circuit 108 receives signals output from sensors (typically proximity switches) such as a general winning port sensor 54 and a specific winning port sensor 56 that detect pachinko balls that have been won in various winning ports. The main control unit 100 has a function of converting to a data format that can be processed. The input processing circuit 108 also receives detection signals output from the prize ball detection sensor 27 and the lending ball detection sensor 28 provided in the payout device 30. The communication control circuit 112 is a circuit (consisting of a general-purpose logic IC, PIO, transistor array, etc.) for transmitting a command or the like set to the output port to each control unit such as the prize ball control unit 200.
In the main control unit 100, the CPU 102, the ROM 104, the RAM 106, the input processing circuit 108, and the communication control circuit 112 described above are configured by electronic elements (hereinafter simply referred to as CPU elements) integrated on one chip.

Next, the filter circuit 170 provided in the main control unit 100 will be described. The filter circuit 170 is a so-called digital filter, and includes a noise removal circuit 160 and a clock circuit 150 that defines a processing cycle of the noise removal circuit 160 as shown in FIG.
As shown in FIG. 4, the clock circuit 150 is mainly configured by a high-frequency oscillator 151 and two counter circuits 155 and 157 that further divide the signal output from the high-frequency oscillator 151.
That is, the high-frequency oscillator 151 (SG-531 manufactured by Seiko Epson Corporation) is an integrated crystal oscillator and CMOSIC in one electronic element, and outputs a 12 MHz signal. The signal output from the high frequency oscillator 151 is input to the CK terminal of the 4-bit binary counter 155.
The 4-bit binary counter 155 (Toshiba 74HC161) divides the signal (12 MHz) output from the high-frequency oscillator 151 into 4 MHz. That is, the signal output from the CO terminal of the 4-bit binary counter 155 is divided into 4 MHz, and this signal is input to the CK terminal of the 12-stage ripple counter 157 via the inverter 156.
The 12-stage ripple counter 157 (Toshiba 74HC4040) divides the signal (4 MHz) output from the 4-bit binary counter 155 into a 500 kHz signal. That is, the signal output from the third-stage output terminal Q 3 of the 12-stage ripple counter 157 is frequency-divided to 500 kHz, and this signal is output to the noise removal circuit 160.
The clock circuit 150 further includes a reset IC 152 (M51951 manufactured by Mitsubishi Corporation). The reset IC 152 outputs a reset signal when the voltage of the signal supplied from the voltage transformer 140 described above to the main controller 100 decreases and falls below a predetermined level. This reset signal is received by the aforementioned 4-bit binary counter 155, 12-stage ripple counter 157, etc., and functions to stop the functions of these elements.

Next, the configuration of the noise removal circuit 160 to which the signal (500 kHz) output from the 12-stage ripple counter 157 of the clock circuit 150 described above is input will be described with reference to FIG.
As shown in FIG. 5, the noise removal circuit 160 is configured around an 8-bit shift register 162. In this shift register 162 (Toshiba 74HC164), a power failure signal output from the power failure detection unit 130 is input to its A terminal, its B terminal is connected to a + 5V power line, and its clock circuit is connected to its CK terminal. A signal (500 kHz) output from 150 (12-stage ripple counter 157) is input. The first output terminal Qa of the shift register 162 is connected to the first terminal of the logic circuit 165 via the inverter 163, and the second output terminal Qb is connected to the second terminal of the logic circuit 165. Further, the fifth output terminal Qe is connected to the third terminal of the logic circuit 165 via the inverter 164. Further, the sixth output terminal Qf of the shift register 162 is connected to the NMI terminal of the CPU element of the main control unit 100 via the inverter 167.
The output terminal of the logic circuit 165 is connected to the third terminal of the logic circuit 161 through the inverter 166. The first terminal of the logic circuit 161 is connected to the + 5V power supply line, and the reset signal output from the reset IC 152 of the clock circuit 150 is input to the second terminal.

Since it is configured as described above, when the state of the signal input to the A terminal of the shift register 162 becomes a predetermined state (ON state) and the state is maintained for a predetermined period, the sixth terminal of the shift register A signal is output from Qf. Conversely, when the signal input to the A terminal of the shift register 162 is in an ON state and the state is not maintained for a predetermined period, a signal is output from the logic circuit 161 and the shift register 162 is reset, so that the sixth No signal is output from the output terminal Qf.
The operation of the noise removal circuit 160 as described above is performed when a power failure signal is input to the A terminal of the shift register 162 (in the case of FIG. 6) and when noise is input to the A terminal of the shift register 162 (shown in FIG. 7). Case) will be specifically described as an example. 6 and 7, in order from the top, a clock signal, a signal input to the A terminal of the shift register 162, a signal output from the Qa terminal of the shift register 162 and input to the logic circuit 165, and a Qb terminal of the shift register 162 Is output from the logic circuit 165, input from the Qe terminal of the shift register 162 to the logic circuit 165, output from the logic circuit 165, + 5V power line, and output from the reset IC. , A signal output from the logic circuit 161 and input to the CLR terminal of the shift register 162, and a signal output from the Qf terminal of the shift register 162 and input to the NMI terminal of the CPU element.

First, an operation when a signal (noise) having a length of two clock signals is input to the A terminal of the shift register 162 will be described (in the case of FIG. 7). When a signal is input to the A terminal, a signal having the same waveform as that of the signal input to the A terminal is output from the Qa terminal simultaneously with the rise of the next clock signal, and a signal having the same waveform is also output from the Qb terminal after one cycle. . In the next period when the signal is output from the Qb terminal, the signals input to the logic circuit 165 are 0 → 1 (high level), 1 → 1 (high level), and 0 → 0 (low level). The state of the signal output from the logic circuit 165 changes from 0 to 1. Accordingly, signals input to the logic circuit 161 are 1 → 1 (high level), 1 → 1 (high level), 1 → 0 (low level). For this reason, the state of the signal output from the logic circuit 161 changes from 1 (high level) to 0 (low level), and the shift register 162 is cleared. Therefore, the state of the Qf terminal of the shift register 162 does not change and no signal is input to the NMI terminal of the CPU element.
Next, an operation when a power failure signal (a signal having a length of six or more clock signals) is input to the A terminal of the shift register 162 will be described (in the case of FIG. 6). When a signal is input to the A terminal, a signal having the same waveform as the signal input to the A terminal is output from the Qa terminal simultaneously with the rise of the next clock signal, and a signal having the same waveform is output from the Qb terminal after one cycle. A signal having the same waveform is output from the terminal. Since the power failure signal is a signal having a predetermined length, the level of the signal output from the Qa terminal, the Qb terminal, and the Qf terminal does not change until the signal is output from the Qf terminal, and is therefore output from the logic circuit 165. The state of the signal is not changed. Therefore, since the level of the signal output from the logic circuit 161 does not change, the shift register 162 is not reset and a signal is output from the Qf terminal of the shift register 162. This output signal is received by the NMI terminal of the CPU element.

As is clear from the above description, when a signal having a predetermined period is input to the shift register 162, no signal is output from the filter circuit 170 (shift register 162), and a signal having a predetermined period or more is input to the shift register 162. A signal is output from the filter circuit 170 (shift register 162) only in such a case. Therefore, an instantaneous signal (noise or the like) is removed by the filter circuit 170. That is, when the state of the input signal to the filter circuit 170 changes and before returning to the original state before counting a predetermined number of clock signals, no signal is output from the filter circuit 170, and the predetermined number of clock signals are output. If the state is maintained after the signal is counted, the signal is output from the filter circuit 170.
Further, after a signal is input to the A terminal, the signal is output after a predetermined period (1 → 0), and the signal instantaneously changes from 1 → 0 (the change of the signal here passes through the inverter 167). Later changes in signal). Therefore, unlike an analog filter using a capacitor or the like, it does not take time for the signal to rise.
Note that the output signal may be shifted by one cycle of the clock signal depending on the timing at which the signal is input to the A terminal (the possibility of being output at (1) or (2) in FIG. 6). Since the oscillation frequency of 150 is sufficiently high, there is almost no problem with a shift of one clock.

Next, the winning ball control unit 200 will be described. The prize ball control unit 200 is a control device that controls the operation of the payout device 30 based on the command transmitted from the main control unit 100 described above, and is basically the same as the main control unit 100 as shown in FIG. , CPU 202, ROM 204, RAM 206, input processing circuit 210, communication control circuit 208, output processing circuit 212, filter circuit 214, and the like connected to CPU 202 via bus 216.
The CPU 202 performs prize ball control and the like of the payout device 30 according to a control program stored in the ROM 204. Various data and input / output signals are stored in the RAM 206. As will be described later, the RAM 206 converts the command transmitted from the main control unit 100 into the number of prize balls and accumulates the prize ball, and the prize is transmitted from the main control unit 100 in the same manner as the prize ball accumulation counter. The received command is converted into the number of prize balls, integrated, and when a detection signal output from the rotation detection sensor 29 is received, a prize ball addition / subtraction counter that subtracts 1 and a detection signal output from the prize ball detection sensor 27 are received. A payout accumulation counter for accumulating the number of received detection signals is stored.
The input processing circuit 210 can receive the detection signals output from the rotation detection sensor 29, the lending ball detection sensor 28, and the prize ball detection sensor 27 provided in the payout device 30 and process them in the prize ball control unit 200. Has a function to convert to a data format.
The output processing circuit 212 is a circuit that outputs a drive signal for driving the motor 25, and the communication control circuit 208 is a circuit for receiving a command transmitted from the main control unit 100. It should be noted that a command buffer for storing a command received at the time of energization (corresponding to the energized reception command storage unit in the claims) and an NMI command buffer for storing a command received at the time of power failure signal reception (reception at energization in the claims) (Corresponding to a command storage unit) is provided in the RAM 206.
In the prize ball control unit 200, as with the main control unit 100, electronic elements (hereinafter referred to as the CPU 202, ROM 204, RAM 206, input processing circuit 210, output processing circuit 212, and communication control circuit 208 are integrated on one chip. Simply referred to as a CPU element).
In addition, the filter circuit 214 provided in the prize ball control unit 200 is the same circuit as the filter circuit 170 provided in the main control unit 100 described above, receives the power failure signal output from the power failure detection unit 130, The prize ball control unit 200 has a function of outputting a signal to the NMI terminal of the CPU element.

  Next, the operation of the pachinko machine configured as described above will be described focusing on the processing of the main control unit 100 and the prize ball control unit 200. First, the processing of each control unit when power is supplied to the pachinko machine 10 will be described.

(1) Power-on processing (main control unit)
When the power is turned on, energization is started from the power supply unit 120 to the control units 100 and 200, and when the voltage applied to the control units 100 and 200 reaches a predetermined voltage, processing described below is started. First, the processing of the main control unit 100 will be described with reference to FIGS.
Note that the main control unit 100 receives a prize detection process for detecting a pachinko ball that has won a prize opening, and a prize for transmitting a prize ball command created based on a prize detected by the prize detection process to the prize ball control unit 200. Input / output processing of commands and signals such as ball command transmission processing and prize ball detection processing for detecting a pachinko ball paid out from the payout device 30 is separate from normal processing in the main control unit 100. This is performed by interrupt processing at predetermined intervals (4 ms in this embodiment) by a CTC counter provided in the control unit 100. Therefore, first, normal processing of the main control unit 100 will be described first with reference to FIG. 8, and then interrupt processing by the CTC counter (hereinafter simply referred to as CTC interrupt processing) will be described with reference to FIG. 9 and FIG. .

As shown in FIG. 8, the main control unit 100 first performs initialization processing (S01), and then determines whether the RAM erase switch is turned on (output) (S02). Here, the RAM erase switch is a switch operated to erase stored information when the power is shut off. That is, it is a switch that is operated when it is not necessary to resume the game using the stored information (for example, when the business is turned off the next day after the power is turned off due to the end of business), and is operated when the power to the pachinko machine 10 is turned on. Then, a signal is output to the main control unit 100 and the prize ball control unit 200. Accordingly, in step S02, the main control unit 100 determines whether or not a signal output by operating the RAM erase switch has been received.
If the RAM erase switch has been operated (YES in step S02), the process proceeds to step S04. If the RAM erase switch has not been operated (NO in step S02), then there is an abnormality in the RAM 106. Is determined (S04). In other words, if the information stored in the RAM 106 is destroyed for some reason, the process cannot be resumed using that information, so it is first determined whether the information in the RAM 106 can be used. As a specific method, the determination is made based on whether or not the checksum value (added value obtained by adding the values of the registers in the RAM 106) matches the normal value. If there is an abnormality in the RAM 106 (YES in step S03), the process proceeds to step S04. If there is no abnormality in the RAM 106 (NO in step S03), the process is resumed based on the stored information. The process proceeds to electric processing (S09). The contents of the power recovery process will be described later.
In step S04, the main control unit 100 clears the information stored in the RAM 106. Thereby, the main control unit 100 shifts to a main process described below.

In the main processing, first, output data creation processing is performed (S05). In this output data creation processing, not shown, provided on the front surface of the game board based on detection signals output from various sensors (general winning sensor 54, specific winning sensor 56, starting port sensor, etc.) equipped in the pachinko machine. Output data (driving data) for operating the electric winning component such as a big prize opening is created. The created output data is output to each electrical device by the CTC interrupt process described above.
When the output data creation process is completed, a command creation process is performed (S06). In the command creation process, based on detection signals output from various sensors (general winning sensor 54, specific winning sensor 56, start opening sensor, etc.) equipped in the pachinko machine, the winning ball control unit 200, the symbol control unit, the sound A command to be transmitted to a sub control unit such as a control unit or a lamp control unit is created. For example, a prize ball command for instructing the prize ball to be paid out is created in the prize ball control unit 200, a symbol variation command for instructing a variation in a special symbol is created in the symbol control unit, and a sound effect is transmitted to the sound control unit. A sound effect command for commanding sound generation is created, and a lamp lighting command for commanding lamp decoration is created in the lamp control unit. The command created in step S06 is transmitted to each control unit by CTC interrupt processing. Note that the command transmission process to each control unit will be described later by taking the command transmission to the prize ball control unit 200 as an example.
When the command creation processing is completed, external information creation processing is then performed (S07). In this external information creation process, information on the information to be output to a notification device (symbol display device, lamp, speaker, external computer, etc.) in order to notify the player, hall clerk, etc. of a ball hit notification, etc. during a big hit count or probability change. Create. The created information is also output from the main control unit 100 by the CTC interrupt process.
Next, in step S08, random number update processing is performed. In this random number update process, initial value random numbers are created / updated and lost symbols are created / updated. When the process of step S08 ends, the process returns to step S05 and the processes from step S05 to step S08 are repeated.

Next, the CTC interrupt process will be described with reference to FIG. In the following description, only processes (winning detection process, prize ball command transmission process, prize ball detection process) performed when controlling the payout device 30 will be described.
In the winning detection process shown in FIG. 9A, the main control unit 100 first determines whether or not a winning is detected (S11). Specifically, it is determined whether or not the signal output from the general winning opening sensor 54 or the specific winning opening sensor 56 is received in the input processing circuit 108 of the main control unit 100. If the detection signals output from these sensors 54 and 56 have not been received (NO in step S11), the winning detection process is terminated, and if the detection signal has been received (YES in step S11). If), the winning number is stored in the winning number counter (S32), and the winning detection process is terminated.

In the winning ball command transmission process shown in FIG. 9B, the main control unit 100 first determines whether or not the winning number counter has a stored value (S13). When there is no stored value in the winning number counter [when step S13 is NO], the winning ball command transmission process is terminated, and when there is a stored value in the winning number counter (when step S13 is YES), the winning ball control is performed. A prize ball command transmission process is performed to pay out a prize ball to the unit 200 (S14). The command transmission process in step S14 will be described in detail with reference to FIG.
As shown in FIG. 10, in the command transmission process, the main control unit 100 first sets a command to be transmitted to the output port of the CPU 102 (S21). Next, the main control unit 100 turns on a write signal for causing the prize ball control unit 200 to start command reception processing, and at the same time, the prize ball control unit 200 can read a command set in the output port of the main control unit 100. The select signal is turned on (S22). Then, after waiting in that state for a while (S23), the write signal is turned off (S24), and the read pointer is updated (S25). This read pointer is information for managing which command is the currently transmitted command when there are a plurality of commands to be transmitted. After these processes, the select signal is turned OFF (S26), and the command transmission process is terminated.
As described above, in the command transmission process, the command is first set to the output port, then the command transmission is started (the write signal / select signal is turned ON), and the command transmission is ended (the select signal is transmitted). OFF). In this embodiment, a certain amount of time is required from the start of command transmission to the end of transmission (the time during which the select signal is ON) because the write signal for starting the command reception process is the prize ball control unit. This is for inputting to 200 INT terminals. That is, a certain amount of time is required until the command reception process is started in the prize ball control unit 200. After the above-described prize ball command transmission process is completed, the number of transmitted balls is then set in the transmission ball integration counter. Accumulated (S15), and further subtracted from the winning number counter (S16), and the winning ball command transmission process is terminated. Therefore, when there is a stored value in the winning number counter, a winning ball command is transmitted to the winning ball control unit 200 until the stored value becomes 0, and at the same time, the number of payouts commanded to the winning ball control unit 200 by the transmission. Is added to the transmission ball integrating counter.

In the prize ball detection process shown in FIG. 9C, the main control unit 100 first determines whether or not a pachinko ball is detected by the prize ball detection sensor 27 provided in the payout device 30 (S17). Specifically, the determination is made based on whether or not the detection signal output from the winning ball detection sensor 27 has been received.
If no winning ball is detected by the winning ball detection sensor 27 (NO in step S17), the winning ball detection process is terminated, and if the winning ball is detected by the winning ball detection sensor 27 (in step S17). In the case of YES], the number of pachinko balls detected from the transmitted ball number integrating counter is subtracted (S18). Then, it is determined whether or not the value of the transmitted ball integration counter is 0 or more (S19). When the value of the transmitted ball number counter is 0 or more [when step S19 is YES], the prize ball detection process is terminated. On the other hand, when the value of the transmitted ball number counter is not equal to or greater than 0 (when step S19 is NO), it is an abnormal situation in which extra pachinko balls are being paid out from the payout device 30, and therefore the abnormal lamp is turned on. To inform the hall clerk etc. of the abnormality (S20).

As is apparent from the above description, the main control unit 100 detects a winning by CTC interrupt processing, and creates a winning ball command to be transmitted to the winning ball control unit 200 in the normal main processing based on the winning detection. Is done. The created prize ball command is transmitted to the prize ball control unit 200 in the CTC interruption process.
In addition, the main control unit 100 accumulates the number of transmitted balls in the transmitted ball number counter every time a prize ball command is transmitted to the prize ball control unit 200, and is output from the prize ball detection sensor 27 provided in the payout device 30. Every time a detection signal is received, the number of payout balls is subtracted from the transmitted ball count counter. Then, based on the value of the transmission integration counter, an abnormal case (for example, a failure of the payout device 30) is determined in which a payout ball number that is larger than the transmitted ball number is paid out.

(2) Processing at power-on (prize ball control unit)
Next, the operation of the prize ball control unit 200 will be described with reference to FIGS. In the prize ball control unit 200, a command reception process for receiving a command transmitted from the main control unit 100 by an interrupt process using a write signal (INT terminal input) output from the main control unit 100 is performed. Signal input / output processing, such as processing for outputting a drive signal for driving the drive motor 25, processing for receiving a detection signal output from a sensor such as the rotation detection sensor 29, the prize ball detection sensor 27, etc. This is performed by interruption processing at predetermined intervals (4 ms in the present embodiment) by a CTC counter provided in the prize ball control unit 200. Therefore, first, normal processing in the prize ball control unit 200 will be described first with reference to FIGS. 11 and 12, and next, command reception processing and interrupt processing by a CTC counter (hereinafter simply referred to as CTC interrupt processing) will be described with reference to FIG. This will be described with reference to FIG.

As shown in FIG. 11, in the prize ball control unit 200 as well as the main control unit 100, first, initialization processing is performed (S27), and then it is determined whether or not the RAM erase switch is turned on (output) (S28). ). If the RAM erase switch is turned on (YES in step S28), the process proceeds to step S30. If the RAM erase switch is not turned on (NO in step S28), there is next an abnormality in the RAM 206. Is determined (S29).
If there is an abnormality in the RAM 206 (YES in step S29), the process proceeds to step S30. If there is no abnormality in the RAM 206 (NO in step S29), the process is resumed based on the stored information. The process proceeds to the power recovery process (S36). The power recovery process in the winning ball control unit 200 will also be described in detail later.
In step S30, the prize ball control unit 200 clears the information stored in the RAM 206, and shifts to a main process described below.

When shifting to the main process, first, an analysis process of the command transmitted from the main control unit 100 is performed (S31). That is, the command transmitted from the main control unit 100 is any type of command (for example, a winning ball permission command for allowing the starting of a winning ball, a winning ball disabling command for prohibiting a winning ball due to a cause such as a broken ball, a predetermined ball Whether the command is a prize ball command or the like commanding the number to be paid out. This command analysis processing will be described with reference to FIG.
As shown in FIG. 12, in the command analysis process, it is first determined whether or not the select signal is ON (S36). That is, it is determined whether or not the main control unit 100 is performing command transmission processing.
If the select signal is ON (YES in step S36), the command analysis process is terminated. If the select signal is not ON (NO in step S36), then the NMI command buffer It is determined whether or not the value of 0 is 0 (S37). In other words, in the present embodiment, a command buffer that stores commands received during energization and an NMI command buffer that stores commands received at the input port of CPU 202 when a power failure signal is received are provided in RAM 206. . Therefore, the same command is stored in these two command buffers depending on the timing at which a power failure occurs (for example, when commands are taken into the command buffer before the power failure). Therefore, in this embodiment, in order to prevent the same command from being read twice, the command in the NMI command buffer is given priority (the data in the command buffer is invalidated). Therefore, after confirming the state of the select signal, it is first determined in step S37 whether the NMI command buffer is 0 or not.

If the value of the NMI command buffer is 0 [YES in step S37], it is next determined whether or not the values of the command read pointer and the command write pointer match (S38). That is, in the present embodiment, when the command transmitted from the main control unit 100 in the command reception process described later is stored in the command buffer, the value of the command write pointer is updated by 1, and the command analysis process When the written command is analyzed, the value of the command read pointer is updated by one. Therefore, if the command stored in the command buffer has already been analyzed, the values of the command write pointer and the command read pointer match, and conversely if the command stored in the command buffer has not been analyzed, The pointer values do not match. Therefore, in step S38, it is first determined whether or not the value of the command read pointer matches the value of the command write pointer so that the same command is not analyzed twice.
If the value of the command read pointer matches the value of the command write pointer (YES in step S38), command analysis has already been completed, so the command analysis processing is terminated as it is. Conversely, if the value of the command read pointer does not match the value of the command write pointer (NO in step S38), the value of the command buffer is analyzed (S39), and the value of the command read pointer is updated by one. The value of the command buffer is cleared to 0 (S40), and the command analysis process is terminated.

On the other hand, if the value of the NMI command buffer is not 0 (NO in step S37), the command of the NMI command buffer is analyzed (S41). Then, the value of the command write pointer is matched with the value of the command read pointer, that is, the values of both pointers (S42). As a result, in the next command analysis process, the determination in step S38 is YES, so that it is prevented from proceeding to the process in step S39 (process for analyzing the value of the command buffer). Therefore, for example, when the command received before the power failure is stored in the command buffer and the same command is stored again in the NMI command buffer after the power failure occurs, the same command (command stored in the command buffer) It will not be analyzed.
When step S42 ends, the value of the NMI command buffer is finally cleared to 0 and the command analysis process ends.

  As a result of the command analysis process, if the received command is a prize ball command, the number of pachinko balls to be paid out to the player by the command is added to the prize ball accumulation counter (S32), and similarly, The number of pachinko balls to be paid out to the player is added to the prize ball adjustment counter (S33). Next, drive data for driving the motor 25 is created based on the number of pachinko balls to be paid out stored in the above-mentioned prize ball adjustment counter (S34). Next, when there is some abnormality (for example, when award balls are paid out too much from the payout device 30), an error process is performed to notify the hall clerk about the abnormality (S35). When this error process is performed, the winning ball control unit 200 returns to step S31 and repeats the process from S31.

Next, command reception processing in the prize ball control unit 200 will be described with reference to FIG. 13, and input / output processing in the prize ball control unit 200 will be described with reference to FIG.
In the command reception process shown in FIG. 13, first, the CPU 202 of the prize ball control unit 200 saves the contents of a predetermined register to another place in order to secure an area necessary for the command reception process (S44). Next, an input port command is input to the area secured in step S44 (S45), and it is determined whether the select signal is ON (S46).
If the select signal is not ON [NO in step S46], the main control unit 100 is not in the transmission state, and the process proceeds to step S49. Conversely, if the select signal is ON [YES in step S46], the command input in step S45 is stored in the command buffer (S47). Next, the value of the write pointer is updated (S48), and the process proceeds to step S49. In step S49, the register saved in the process of step S44 is restored to the original (S49). This completes the command reception process.

In the input / output process shown in FIG. 14, the drive data created by the drive data creation process in step S34 shown in FIG. 11 is first output to the motor 25 of the payout device 30 (S50). Specifically, a drive signal is output to the motor 25 via the output processing circuit 212.
When the drive signal is output, it is next determined whether or not the pachinko ball has been paid out from the payout device 30 (S51). Specifically, it is determined whether or not a detection signal output by detecting a pachinko ball with the prize ball detection sensor 27 is received by the prize ball control unit 200. If a detection signal has not been received (NO in step S51), the process proceeds to step S53. If a detection signal has been received (YES in step S51), the pachinko ball detected by the payout integration counter is detected. The number is added (S52).
Next, the winning ball control unit 200 determines whether or not the rotating ball receiver 34 of the payout device 30 has rotated a predetermined angle (S53). Specifically, it is determined by whether or not the prize ball control unit 200 has received a detection signal output from the rotation detection sensor 29 provided in the payout device 30.
When the detection signal output from the rotation detection sensor 29 is received by the prize ball control unit 200 (in the case of YES at step S53), 1 is subtracted from the prize ball addition / subtraction counter (S54), and then the prize ball addition / subtraction counter is 0. It is determined whether or not this is the case (S55). If the prize ball addition / subtraction counter is larger than 0 (YES in step S55), the prize ball to be paid out has not been paid out, so the process returns to step S50 and the processing from step S50 is repeated. Conversely, if the prize ball addition / decrement counter is 0 or less (NO in step S55), the process proceeds to step S56.
On the other hand, when the winning ball control unit 200 has not received the detection signal output from the rotation detection sensor 29 (NO in step S53), a predetermined time has elapsed since the drive signal in step S50 was output. Is determined (S60). If the predetermined time has not elapsed [NO in step S60], the process returns to step S50, and the processing up to step S53 is repeated until the predetermined time elapses. On the contrary, if the predetermined time has elapsed (YES in step S60), a ball biting process is performed (S61). That is, if the detection signal output from the rotation detection sensor 29 cannot be received even after a predetermined time has elapsed since the drive signal was output in step S50, the pachinko ball is bitten for some reason and the rotating ball receiver 34 rotates. It is thought that it is in an incapable state. For this reason, the ball smear state is eliminated by performing a process of rotating the motor 25 alternately (a ball smear process). When the ball smearing process is completed, the process returns to step S50 again to repeat the above-described process.

In the process of step S56, it is determined whether or not the value of the winning ball addition / subtraction counter is 0 (S56). When the value of the winning ball addition / subtraction counter is not 0, that is, when the value of the winning ball addition / subtraction counter is smaller than 0 (NO in step S56), a state where an excessive amount of winning balls is paid out from the payout device 30 (abnormal state). Therefore, the input / output process is terminated. This abnormal state is notified to a store clerk or the like by the error process in step S35 shown in FIG.
If the value of the prize ball addition / subtraction counter is 0 [YES in step S56], the motor 25 is stopped (S57), and it is determined whether or not the value of the prize ball accumulation counter matches the value of the payout accumulation counter. (S58). When the value of the winning ball integration counter matches the value of the payout integration counter (in the case of YES in step S58), the input / output processing is terminated, and when the value of the winning ball integration counter and the value of the payout integration counter do not match [ In the case of NO in step S58], since the prize ball to be paid out is not actually paid out, the process of paying out the prize ball until the value of the prize ball integration counter matches the value of the payout integration counter (retry) Process) (S59).

As is apparent from the above description, the prize ball control unit 200 performs the command reception process shown in FIG. 13 by the interrupt process using the write signal output from the main control unit 100, and the received command is shown in FIG. Analysis is performed in the normal processing shown in FIG. 12, and drive data is created. Then, this drive data is output to the motor 25 by the input / output process by the CTC interruption process shown in FIG. 14, and a predetermined number of pachinko balls are paid out from the payout device 30.
The winning ball control unit 200 that receives this command updates the write pointer when the command is stored (written) in the command buffer, and updates the read pointer when the written command is analyzed. Then, the command analysis processing is performed so that the write pointer matches the read pointer, thereby preventing the data stored in the command buffer from being analyzed twice.
Also, the prize ball control unit 200 adds the number of payout balls specified by the command transmitted from the main control unit 100 to the prize ball addition / subtraction counter. Each time the detection signal output from the rotation detection sensor 29 is received, the value of the prize ball addition / subtraction counter is subtracted, and the motor 25 of the payout device 30 is driven until the value of the prize ball addition / subtraction counter becomes zero. As a result, the motor 25 of the payout device 30 is rotated so that the number of pachinko balls paid out is the number of prize balls specified by the command transmitted from the main control unit 100.
Further, the prize ball control unit 200 adds the number of payout balls specified by the command transmitted from the main control unit 100 to the prize ball accumulation counter, while the pachinko ball paid out from the payout device 30 is used as a prize ball detection sensor. 27, and the detection signal is integrated into the payout integration counter. Then, control is performed so that the pachinko balls are paid out from the payout device 30 until the values of the prize ball integration counter and the payout integration counter match (retry processing in step S59 in FIG. 14). Therefore, it can be prevented that the pachinko ball is not paid out because the pachinko ball is not paid out even though the rotating ball receiver 34 is rotated for some reason.

(3) Processing at power-off (main control unit, prize ball control unit)
Next, the operation of the pachinko machine 10 when the power supply to the pachinko machine 10 is interrupted due to a power failure or unexpected power OFF will be described.
When power supply from the external power source to the pachinko machine 10 is interrupted, a power failure signal is output from the power failure detection unit 130 provided in the power source unit 120 toward the main control unit 100 and the prize ball control unit 200. The power failure signal output from the power failure detection unit 130 is input to the filter circuits 170 and 214 provided in the main control unit 100 and the prize ball control unit 200, respectively. Since the filter circuits 170 and 214 are configured as described above, a predetermined timing (sixth (or seventh) of the clock signal of the filter circuits 170 and 214) is input after the power failure signal is input to the filter circuits 170 and 214. The signal is output from the filter circuits 170 and 214 at the timing when the clock signal rises. Therefore, the signals output from the filter circuits 170 and 214 are input to the NMI terminals (non-massable interrupt terminals) of the main control unit 100 and the prize ball control unit 200 almost simultaneously, and these control units perform the power failure described below. Processing is performed.
Note that the power supplied to the main control unit 100 and the prize ball control unit 200 during a predetermined time after the power failure signal is output (the time required to perform the power failure process described below) is as described above. In addition, the capacitor C1 of the power supply unit 120 is covered by electric power stored during energization.

First, the process performed in the main control part 100 which received the power failure signal is demonstrated based on FIG.
As shown in FIG. 15, the main control unit 100 stores the register and stack pointer of the RAM 106 in a predetermined area of the RAM 106 (S60). Next, for processing when the power failure is restored, the command set in the output port of the CPU 102 when the power failure signal is received is stored in a predetermined address of the RAM 106 (S61).
Then, a count value that defines the time during which the detection signal output from the prize ball detection sensor 27 must be monitored after the power failure signal is output is set in a predetermined register of the RAM 106 (S62), and the countdown is performed by the set count value. Start. The time defined by the count value set in step S62 is from the mechanical characteristics of the payout device 30, that is, from the time when the driving signal is output to the motor 25 until the winning ball detection sensor 27 detects the pachinko ball. It is determined in consideration of the time required for.
When the countdown is started, it is next determined whether or not the winning ball control unit 200 has received the detection signal output from the winning ball sensor 27 provided in the inner winning ball guiding path 32a (S63). When the detection signal is received (in the case of YES in step S63), the value of the transmitted ball count counter is decremented by 1 (S64), and when the detection signal is not received (in the case of NO in step S63). Advances to step S65.
In step S65, it is determined whether or not the winning ball control unit 200 has received the detection signal output from the winning ball sensor 27 provided on the outer winning ball guiding path 32a (S65). When the detection signal is received (in the case of YES in step S65), the value of the transmitted ball count counter is decremented by 1 (S66), and when the detection signal is not received (in the case of NO in step S65). Advances to step S67.
In step S67, it is determined whether or not a predetermined time has elapsed since the power failure signal was received (S67). Specifically, the determination is made based on whether or not the count value that started counting in step S62 has reached a predetermined value (in this embodiment, the count value is 0). If the predetermined time has not elapsed [NO in step S67], the process returns to step S63 and the processes from step S63 are repeated.
On the other hand, if the predetermined time has elapsed (YES in step S67), the process proceeds to the next process and a checksum value is calculated (S68). That is, the checksum value is obtained by adding the values of the registers in the RAM 106. When the checksum value is calculated, the checksum value is stored at a predetermined address in the RAM 106 (S69), and access to the RAM 106 is prohibited (S70). Thereby, the processing of the main control unit 100 at the time of power-off is completed.
Note that, when the energization is cut off, power is supplied to the RAM 106 from an information storage power supply (configured by a capacitor C5) provided separately in the power supply unit 120, and the information stored in the RAM 106 is held for a predetermined time.

Next, processing in the prize ball control unit 200 when a power failure signal is received will be described with reference to FIG. As is clear from FIG. 16, the process in the prize ball control unit 200 is basically the same as the process in the main control unit 100 shown in FIG. That is, the detection signal output from the winning ball detection sensor 27 is monitored by operating a timer for a preset time, and when the monitoring time has elapsed, a checksum is calculated and stored, and access to the RAM 206 is prohibited. The point is the same.
However, the main control unit 100 stores the command set in the output port of the CPU 102 and stores it until the energization is restored, whereas the prize ball control unit 200 receives the input of the CPU 202 when the power failure signal is received. If there is a command received at the port, the command is stored in the NMI command buffer in the RAM 206 and stored until the power is restored.
That is, as shown in FIG. 16, in the process when the power of the prize ball control unit 200 is turned off, it is first determined whether or not the select signal is ON after the monitoring time is set in step S72 (S73). ). If the select signal is not ON (NO in step S73), the process proceeds to step S75 because the main control unit 100 is not in a state of transmitting a command. Conversely, if the select signal is ON (YES in step S73), the command received at the input port is stored (written) in the NMI command buffer (S74). After that, predetermined processing such as prize ball detection is performed in the same procedure as the main control unit 100, and the process at the time of power interruption in the prize ball control unit 200 is ended.

As is clear from the above, the main control unit 100 and the prize ball control part 200 operate the timer for a preset time when receiving the power failure signal, and the prize ball detection sensor while the timer is operating. The detection signal output from 27 is monitored. Therefore, even when a driving signal is output from the prize ball control unit 200 to the motor 25 immediately before the power failure signal is output from the power failure detection unit 130, the main control unit 100 and the prize ball control unit 200 can reliably count.
In addition, the main control unit 100 stores and holds the command set in the output port of the CPU 102 at the time of power failure signal reception until energization is restored, and the prize ball control unit 200 performs main control at the time of power failure signal reception. The unit 100 determines whether or not transmission processing is being performed. If transmission processing is being performed, the command received at the input port of the CPU 202 is stored and held in the NMI command buffer in the RAM 206. These commands that are held during a power failure are used for the process at the time of energization recovery described below.
Further, the main control unit 100 and the prize ball control unit 200 receive the power failure signal at the NMI terminal substantially simultaneously, and start the above-described process when the power is turned off almost simultaneously. Accordingly, since the information stored in the process when the power is turned off (step S60 in FIG. 15 and step S71 in FIG. 16) is also stored almost simultaneously, there is a discrepancy between the processes restarted by both control units when power is restored. Can be prevented.

(4) Processing when power is restored (main control unit, prize ball control unit)
Next, the processing of the main control unit 100 and the prize ball control unit 200 when the processing is resumed using the information stored in the RAM 106, 206 or the like by the processing at the time of power-off described above will be described with reference to FIG. To do.
When the game is resumed from the power-off state using the information stored in the pachinko machine 10 according to the present embodiment, the power to the pachinko machine 10 is turned on without operating the RAM erase switch.

First, processing in the main control unit 100 will be described. As shown in FIG. 8, when the power supply is started, the main control unit 100 first performs an initialization process (S01), and then determines whether or not the RAM erase switch is turned on (S02). It is determined whether or not it has occurred (S03). Thereafter, power recovery processing for starting the game is started from the state when the power is shut off (S10). The power recovery process in the main control unit 100 will be described with reference to FIG.
As shown in FIG. 17A, the main control unit 100 first restores the stack pointer (S84). Specifically, the stack pointer stored in a predetermined area of the RAM 106 is restored to the original area by the process at the time of power-off (the process of step S60 shown in FIG. 15). Next, the command set to the output port of the CPU 102 when the power failure signal is received is reset to the output port (S85). Specifically, the command stored by the process at the time of power shutdown (the process of step S61 shown in FIG. 15) is reset to the output port. Then, the contents of all the registers stored by the power-off process (the process of step S60 shown in FIG. 15) are restored (S13). Therefore, since the state of the stack pointer, the register, and the output port is restored to the state at the time of power-off, the main control unit 100 resumes the process from the time of power-off (when a power failure signal is received). For this reason, for example, if a power failure occurs after the command is set and before the write signal / select signal is turned ON, the write signal / select signal is turned ON when the power is restored, and the command set in step S85 receives the prize ball control. It will be retransmitted to the unit 200.

As in the main control unit 100, the processing in the prize ball control unit 200 is also performed as shown in FIG. 11 (S27), and then whether or not the RAM erase switch is turned on (S28). It is determined whether there is an abnormality (S29). Thereafter, the winning ball control unit 200 starts power recovery processing (S36).
In the power recovery process, as shown in FIG. 17B, the stack pointer stored in the process at the time of power shutdown (the process of step S71 in FIG. 16) is restored (S90), and then the process at the time of power shutdown (FIG. 16). All the registers stored in step S71) are restored (S91). Accordingly, since the contents of the stack pointer and the register are restored to the state at the time of power-off, the prize ball control unit 200 resumes the processing from the time of power-off.
Here, if the main control unit 100 is transmitting a command (select signal ON state) when a power failure occurs (when a power failure signal is received), the prize ball control unit 200 receives the command received at the input port in the process when the power is shut off. Are stored in the NMI command buffer. Therefore, in the first command analysis process (see FIG. 12) when power is restored, the command held in the NMI command buffer is processed. Therefore, even if a power failure or the like occurs during command transmission, the command being transmitted is reliably processed by the prize ball control unit 200. If the command is stored (written) in the command buffer of the winning ball control unit 200 before the occurrence of a power failure, the command stored in the NMI command buffer is prioritized to prevent the command from being read twice.

As is clear from the above description, in the pachinko machine 10 according to the present embodiment, the main control unit 100 and the prize ball control unit 200 receive a power failure signal almost simultaneously and process when the power is turned off (FIGS. 15 and 16). Is started. Accordingly, the register / stack pointer information saved by these processes is also stored at the same timing, and the operations of the main controller 100 and the prize ball controller 200 are synchronized in the subsequent power recovery process (FIG. 17). be able to.
Further, in the pachinko machine 10 according to the present embodiment, noise is removed by the filter circuits 170 and 214 provided in both the main control unit 100 and the prize ball control unit 200, so that the main control unit 100 and the prize ball control unit It is possible to prevent 200 from inadvertently starting the process when the power is cut off due to noise or the like.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment, and the present invention is in a form in which various modifications and improvements are made based on the knowledge of those skilled in the art. Can be implemented.

For example, the above-described embodiment is an example in which the present invention is applied when a power failure signal is output from the power failure detection unit 130 toward the main control unit 100 and the prize ball control unit 200. The filter circuit of the invention sends a power failure signal from the power failure detection unit 130 to another control unit (a symbol control unit that controls the symbol display, a sound control unit that controls a speaker, a lamp control unit that controls lamps, etc.). This can also be applied to output.
Also, as a matter of course, the detection device that outputs a detection signal to each control unit is not limited to the power failure detection device shown in the above-described embodiment. For example, the detection device is a frame opening sensor, and this frame opening sensor This can also be used when each control unit (main control unit 100, prize ball control unit 200, etc.) is urgently stopped based on the output detection signal.

  In addition, the period of the clock signal provided in the filter circuits 170 and 214 may be variable so that the magnitude of noise to be removed can be finely adjusted in accordance with the environment of the game store where the gaming machine is installed. In other words, depending on the amusement store where the gaming machine is installed, there is a case where a lot of noise is generated (when the noise signal itself is long in time). It is good to make more.

  The embodiment described above is an example in which the present invention is applied to a pachinko machine. However, the present invention is not limited to this, for example, an arrangement hall machine (a predetermined number of steel balls are injected onto a game board to It can also be applied to various gaming machines such as slot machines, sparrow ball machines, and pachislot machines.

10. Pachinko machine 27. Prize ball detection sensor 29. Rotation detection sensor 30. Dispensing device 34. Rotating ball receiver 100. Main control part 200. Prize ball control part.

Claims (2)

A gaming machine comprising a detection device, a plurality of control devices that receive detection signals output from the detection device, and a plurality of signal lines that connect the detection device and each of the plurality of control devices,
Each of the plurality of signal lines is provided with a filter circuit,
A gaming machine, wherein the filter circuit is configured to output a signal when a state of an input signal to the filter circuit becomes a predetermined state and the state is maintained for a predetermined period. When a power failure detection unit that detects that the power supply from the external power source is cut off, and when a power failure signal output from the power failure detection unit is received, the required information is saved, and when the power supply from the external power source is restored, A gaming machine comprising a plurality of control units that resume control based on the stored information,
A gaming machine, wherein the detection signal output from the power failure detection unit is input to the control unit via a digital filter circuit.

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