JP2009200165A5 - - Google Patents
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- Publication number
- JP2009200165A5 JP2009200165A5 JP2008039049A JP2008039049A JP2009200165A5 JP 2009200165 A5 JP2009200165 A5 JP 2009200165A5 JP 2008039049 A JP2008039049 A JP 2008039049A JP 2008039049 A JP2008039049 A JP 2008039049A JP 2009200165 A5 JP2009200165 A5 JP 2009200165A5
- Authority
- JP
- Japan
- Prior art keywords
- region
- regions
- semiconductor device
- conductive well
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 claims 8
- 239000000758 substrate Substances 0.000 claims 6
- 238000009792 diffusion process Methods 0.000 claims 5
- 238000002955 isolation Methods 0.000 claims 3
- 230000004913 activation Effects 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008039049A JP2009200165A (ja) | 2008-02-20 | 2008-02-20 | 半導体装置 |
| US12/379,288 US20090206451A1 (en) | 2008-02-20 | 2009-02-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008039049A JP2009200165A (ja) | 2008-02-20 | 2008-02-20 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009200165A JP2009200165A (ja) | 2009-09-03 |
| JP2009200165A5 true JP2009200165A5 (enExample) | 2011-01-20 |
Family
ID=40954328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008039049A Abandoned JP2009200165A (ja) | 2008-02-20 | 2008-02-20 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20090206451A1 (enExample) |
| JP (1) | JP2009200165A (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5667893B2 (ja) * | 2011-01-20 | 2015-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| KR102403735B1 (ko) | 2017-09-07 | 2022-05-30 | 삼성전자주식회사 | 비대칭적인 엔딩 셀들을 포함하는 집적 회로 및 시스템 온 칩 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0179898B1 (ko) * | 1996-02-28 | 1999-04-15 | 문정환 | 반도체소자의 바디-콘택 구조 |
| US5946564A (en) * | 1997-08-04 | 1999-08-31 | Micron Technology, Inc. | Methods of forming integrated circuitry and integrated circuitry |
| JP2002158278A (ja) * | 2000-11-20 | 2002-05-31 | Hitachi Ltd | 半導体装置およびその製造方法ならびに設計方法 |
-
2008
- 2008-02-20 JP JP2008039049A patent/JP2009200165A/ja not_active Abandoned
-
2009
- 2009-02-18 US US12/379,288 patent/US20090206451A1/en not_active Abandoned
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