JP2009177297A - Digitally controlled oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digitally controlled oscillator in which all elements are constituted of digital circuit elements and which is suitable for practical design as well. <P>SOLUTION: The digitally controlled oscillator includes: first and second first-stage delay elements of different delay times connected to each other in parallel; a first second-stage delay element whose input terminal is connected to the output terminal of the first and second first-stage delay elements; a second second-stage delay element of the delay time longer than that of the first second-stage delay element, whose input terminal is connected to the output terminal of the first and second first-stage delay elements and output terminal is connected to the output terminal of the first second-stage delay element; and a decoder for generating first decoding output for enabling one of the first and second first-stage delay elements on the basis of digital input signals and second decoding output for enabling one of the first and second second-stage delay elements. The output signals of the first and second second-stage delay elements are inverted and transmitted to the input of the first and second first-stage delay elements. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a digitally controlled oscillator using a digital signal as a control input of an oscillation frequency, and more particularly to a digitally controlled oscillator suitable for constituting all elements with digital circuit elements.

  In general, in integrated circuit design, it is advantageous in terms of cost, shortening the design period, and the like to use a digital circuit by eliminating analog circuit design elements as much as possible. A digital circuit has a limited element library, and if a design tool is included, circuit design is easier than an analog circuit.

  Among various commonly used circuits, a typical one that requires an analog design is a PLL (phase locked loop) circuit, and in particular, one of the elements, a VCO (voltage controlled oscillator), is a digital circuit. difficult. As a part of a VCO that is converted into a digital circuit, there is an oscillator (digital controlled oscillator: DCO) configured such that an oscillation frequency is controlled by an input digital signal, that is, a digital code. Is still an analog circuit.

  Some VCOs use ring oscillators in which digital circuit elements such as inverters are used as constituent elements and are connected in an odd number of rings. Usually, however, analog circuit elements are also required. For example, in a ring oscillator using a CMOS inverter as an inverter, a configuration in which a current control transistor for adjusting a current passing through the CMOS inverter from the power supply side to the ground side is provided as a configuration for controlling the oscillation frequency. Such a transistor is not only an analog circuit element, but if it is provided, it becomes unsuitable for lowering the power supply voltage as a digital circuit which has been demanded recently.

  Also, in a VCO using a ring oscillator, a configuration in which the number of inverter stages is changed by a digital code is also conceivable. This can eliminate analog circuit elements, but the number of stages is unusually high when smooth changes (fine adjustment) of the oscillation frequency are difficult, or when trying to overcome this point and when a low oscillation frequency is required. It is not suitable for practical design.

Note that examples of general techniques of VCOs including digital circuit elements are disclosed in the following documents.
JP 2007-150820 A Japanese Patent No. 3127517 JP 11-205094 A

  The present invention has been made in consideration of the above-described circumstances, and in a digitally controlled oscillator that uses a digital signal as a control input of an oscillation frequency, all the elements are constituted by digital circuit elements and are suitable for practical design. An object is to provide an oscillator.

  In order to solve the above problems, a digitally controlled oscillator according to an aspect of the present invention includes a first first-stage delay element having an input terminal, an output terminal, and an enable terminal, an input terminal, an output terminal, and an enable terminal. And the input terminal is connected to the input terminal of the first stage delay element, and the output terminal is connected to the output terminal of the first stage delay element. A first delay element having a delay time greater than the delay time of the first delay element, an input terminal, an output terminal, and an enable terminal, the input terminal being the first and second one stages A first second-stage delay element connected to both of the output terminals of the second delay element, an input terminal, an output terminal, and an enable terminal, the input terminal being the first and second first-stage delay elements; Connected to both the output terminals of the delay element, A second second-stage delay element having a delay time greater than the delay time of the first second-stage delay element, the terminal of which is connected to the output terminal of the first second-stage delay element; First decode output supplied to both enable terminals of the second first-stage delay element and enabling at least one of the first and second first-stage delay elements based on a digital input signal And at least one of the first and second second-stage delay elements is enabled based on the digital input signal and supplied to both the enable terminals of the first and second second-stage delay elements. And a decoder for generating a second decoded output, wherein the signals at both of the output terminals of the first and second stage delay elements have the inverted polarity of the first and second signals. Before the first stage delay element of 2 Characterized in that it is transmitted to the input terminal therebetween.

  In other words, this digitally controlled oscillator is based on a ring oscillator configuration, but two (or more) delay elements in each stage are connected in parallel, and one of them is usually enabled by a digital input signal. Configured to be selected. There is a difference in delay time between the delay elements connected in parallel in each stage, so that the sum of the delay times of one round of the ring can be set by a digital input signal. Since the delay time of one round of the ring corresponds to the oscillation frequency, this oscillator is a digitally controlled oscillator using a digital input signal as a control input of the oscillation frequency.

  According to such a configuration, it is possible to design a circuit with only digital circuit elements by utilizing an element library in which delay elements having different delay times are prepared as digital circuit elements, and to reduce the delay time difference between parallel-connected elements. By setting it as small as necessary, smooth control of the oscillation frequency is possible and practical.

  According to the present invention, in a digitally controlled oscillator using a digital signal as a control input of an oscillation frequency, it is possible to provide a digitally controlled oscillator in which all elements are constituted by digital circuit elements and suitable for practical design.

  As an embodiment in the above aspect, each of the first and second first-stage delay elements and the first and second second-stage delay elements may be a non-inverting three-state buffer. . In the case of a three-state buffer, a terminal for enabling selection is prepared by itself and is suitable as a delay element used here. The “inverted” type may be used instead of the “non-inverted” type, but the non-inverted type is suitable in that it can support a minimum element library.

  Here, the first state maintaining circuit connected to both the output terminals of the first and second stage delay elements and the output terminals of the first and second stage delay elements And a second state maintaining circuit connected thereto. The high / low state of a node to which the outputs of a plurality of three-state buffers are connected is considered to be kept constant and stable regardless of the disabled state of all the buffers.

  As an embodiment, the delay time of the first first-stage delay element is the same as the delay time of the first second-stage delay element, and the second first-stage delay element has the delay time. The delay time may be the same as the delay time of the second second-stage delay element. If the delay times are aligned in this way, the necessary element library can be simplified accordingly.

  Further, as an embodiment, the first and second first-stage delay elements and the first and second second-stage delay elements are respectively connected to an inverter and an output side of the inverter. A non-transmission changeover switch, the input terminal on the input side of the inverter, the output terminal on the output side of the transmission / non-transmission changeover switch, and the switching control input side of the transmission / non-transmission changeover switch The enable terminal. Since the inverter is one of the most basic digital elements, it is used in this mode. In this case, the enable selection function is obtained by a transmission / non-transmission changeover switch connected to the output side of the inverter.

  Again, the first state maintaining circuit connected to both the output terminals of the first and second first stage delay elements and both the output terminals of the first and second second stage delay elements And a second state maintaining circuit connected thereto. The high / low state of the node to which the outputs of the plurality of delay elements are connected is considered to be kept constant and stable regardless of the disabled state of all of the delay elements.

  Further, as an embodiment, the device has an input terminal, an output terminal, and an enable terminal, the input terminal is connected to both the input terminals of the first and second stage delay elements, and the output terminal is the first terminal. A third first-stage delay element having a delay time greater than the delay time of the second first-stage delay element connected to both of the output terminals of the first and second first-stage delay elements; An output terminal and an enable terminal, the input terminal being connected to the three output terminals of the first, second, and third stage delay elements, and the output terminal being the first, second, and second And a third second-stage delay element having a delay time longer than the delay time of the second second-stage delay element, connected to both of the output terminals of the second-stage delay element, 1 decode output of the first, second and third first stage delay elements. At least one of the first, second, and third stage delay elements is enabled based on the digital input signal supplied to the three enable terminals, and the second decode output of the decoder At least one of the first, second, and third stage delay elements is enabled based on the digital input signal supplied to the enable terminals of the first, second, and third stage delay elements. And can be.

  This is a configuration in which three first-stage delay elements are provided and three second-stage delay elements are provided. Since the range of selection of the delay element is expanded at each stage, it is possible to widen the upper and lower limits of the frequency control and smoother frequency control. Similarly, if the number is four or more, the effect becomes higher as the number increases.

  As an embodiment, a first three-stage circuit having an input terminal, an output terminal, and an enable terminal, the input terminal being connected to both the output terminals of the first and second second-stage delay elements. An input terminal, an output terminal, and an enable terminal, and the input terminal is connected to both the output terminals of the first and second second-stage delay elements, and the output terminal is the first terminal. A second third-stage delay element having a delay time longer than a delay time of the first third-stage delay element, connected to the output terminal of the third-stage delay element, and the first and second 3 A third decoding output is generated which is supplied to both of the enable terminals of the stage delay element and enables at least one of the first and second stage delay elements based on the digital input signal. And 2 decoders. Door can be.

  This is a configuration in which a third-stage delay element is provided. In this case, since the delay time of one round of the loop can be changed by the element selection at the third stage, it is possible to widen the upper and lower limits of the frequency control and smoother frequency control. Similarly, if the number of stages is four or more, the effect increases as the number of stages increases.

  Also, as an embodiment, the first and second first-stage delay elements and the first and second second-stage delay elements are respectively composed of a resistor, a stray capacitance associated with the resistor, A non-inverting three-state buffer having one end connected to the input side, the input terminal on the other end side of the resistor, the output terminal on the output side of the non-inverting three-state buffer, the non-inverting three-state buffer It can be said that the enable terminal is on the enable input side of the buffer. In this case, the difference in delay time between the delay elements in the same stage can be realized by a resistor and its associated stray capacitance, and the three-state buffer itself does not require a plurality of types having different delay times. Therefore, it is possible to deal with a simpler element library.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a digitally controlled oscillator according to an embodiment of the present invention. In particular, the simplest configuration is used for explaining the principle. As shown in FIG. 1, this digitally controlled oscillator includes three-state buffers 11, 12, 13, 14, a NOR gate 15, and decoders 16, 17.

  The three-state buffers 11, 12, 13, and 14 each have an input terminal, an output terminal, and an enable terminal, and are input to the input terminal only when a logic signal to be enabled is input to the enable terminal. Is output to the output terminal with the same logic (non-inverted output). When a logic signal to be enabled is not input to the enable terminal, the output terminal is in a high impedance state.

  The delay time from the input terminal to the output terminal of the buffers 11 and 12 is td1, the delay time from the input terminal to the output terminal of the buffers 13 and 14 is td2, respectively, and the magnitude relationship between them is td1 <td2. In order to set such a magnitude relationship of the delay times in the buffer, for example, the gate width of the transistors (not shown, for example, CMOS transistors) constituting each of the buffers 11 to 14 may be changed. As the state transitions, the current increases and the delay time decreases.

  Buffers 11 and 13 are connected in parallel, and buffers 12 and 14 are also connected in parallel. Further, these are cascaded to the buffers 11 and 13 (first-stage delay elements), and the buffers 12 and 14 (second-stage delay elements) are connected. Both the output sides of the buffers 12 and 14 are led as one input to the NOR gate 15, and the output side of the NOR gate 15 is an oscillation output and led as an input to the buffers 11 and 13. When the other input DN of the NOR gate 15 is set to the high state, the oscillation output is inevitably fixed to low by the function of the NOR gate 15. That is, the input DN is used when oscillation is stopped as necessary.

  The decoder 16 outputs a logic signal that enables at least one of the buffers 11 and 13 as a decoding result based on the input 2-bit digital signal. The decoder 17 outputs a logic signal that enables at least one of the buffers 12 and 14 as a decoding result based on the same input 2-bit digital signal. The decoding specifications of the decoders 16 and 17 are as shown in the table shown in FIG. In this table, “2” means that only the buffers with the delay time td2 (buffers 13 and 14) are enabled, and “1” enables only the buffers with the delay time td1 (buffers 11 and 12). Means that “-” Means that none is enabled.

  Due to the functions of the decoders 16 and 17 described above, as long as the input 2-bit digital signal is not 00, one of the buffers 11 and 13 is enabled as the first-stage delay element, and the buffer 12 and the second-stage delay element are 14 is enabled. Thus, when the other input DN of the NOR gate 15 is set to low, a so-called ring oscillator including the NOR gate 15 is configured. This is because, although the logic level of one input of the NOR gate 15 and the output of the NOR gate 15 are inverted, the output passes through one of the buffers 11 and 13 and further passes through one of the buffers 12 and 14. This is because it returns as one of the gates 15. That is, the delay time is a half period of the oscillation waveform around the ring.

  When the 2-bit digital signal is 01, the decoders 16 and 17 both output “2”, so that the delay time for one round of the ring is 2 × td2 + td0 (where td0 is the delay time of the NOR gate 15). Similarly, when it is 10, the decoder 16 outputs “2” and the decoder 17 outputs “1”, so that the delay time of one round of the ring is td1 + td2 + td0. Further, at 11, since both the decoders 16 and 17 output “1”, the delay time for one round of the ring is 2 × td1 + td0.

  Since these magnitude relationships are 2 × td2 + td0> td1 + td2 + td0> 2 × td1 + td0, the oscillation frequency is proportional to the reciprocal of the delay time of one round of the ring, and the input 2-bit digital signal is 01 (1 in decimal notation). ) Is the lowest, 10 (2 in decimal display) is the middle, and 11 (3 in decimal display) is the highest. Accordingly, the digitally controlled oscillator shown in FIG. 1 is an oscillator in which the oscillation frequency is controlled according to the magnitude relationship of the input 2-bit digital signal.

  In such a variable frequency oscillator, all the elements necessary for the configuration are digital circuit elements, and analog circuit elements are eliminated. Therefore, it is easy to use a process in which only digital circuit elements are provided as an element library. Can be made. Although it is a variable frequency oscillator, it does not require design as an analog circuit, which is advantageous in terms of cost and shortening the design period. In addition, even when the power supply voltage is lowered as a digital circuit, no problem occurs in correspondence. Furthermore, it is relatively easy to expand to integrated circuits having different process specifications.

  As a modification of the embodiment shown in FIG. 1, the delay times of the buffers 11 and 13 as the first-stage delay elements and the buffers 12 and 14 as the second-stage delay elements are not the same. You may make it let. For example, the magnitude relationship of the respective delay times can be set like the buffer 11, the buffer 12, the buffer 13, and the buffer 14 in ascending order. In this case, since four types of delay times can be generally realized as a ring, the decoding specifications of the decoders 16 and 17 are set so that oscillation occurs even when the input 2-bit digital signal is 00. In the case of this modification, an element library provided with more types of delay times is used as a buffer.

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing a digitally controlled oscillator according to another embodiment of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. The description of that part is omitted. This embodiment also has the simplest configuration for explaining the principle.

  In this embodiment, instead of the three-state buffers 11, 12, 13, and 14, a transmission / non-transmission switch 25 is connected to the output side of the inverter 21, and transmission / non-transmission switching is performed on the output side of the inverter 22. A switch 26 is connected, a transmission / non-transmission changeover switch 27 is connected to the output side of the inverter 23, and a transmission / non-transmission changeover switch 28 is connected to the output side of the inverter 24. As the transmission / non-transmission changeover switches 25, 26, 27, and 28, so-called analog switches can be used.

  The decoders 16 and 17 are basically similar in function to those described in FIG. 1, but the decoding outputs of the decoders 16 and 17 are the switching control inputs of the transmission / non-transmission change-over switches 25, 26, 27, and 28. As led. That is, according to the outputs of the decoders 16 and 17, any one of the switches 25 and 27 is in a transmission state, and further, either one of the switches 26 and 28 is in a transmission state.

  The magnitude relationship of the delay times of the inverters 21, 22, 23, 24 (more precisely, the delay time including the transmission / non-transmission changeover switch connected to the output side thereof) is the same as that of the embodiment shown in FIG. Set to. In order to set such a magnitude relationship of the delay times in the inverter, for example, the gate width of a transistor (not shown, for example, a CMOS transistor) constituting each of the inverters 21 to 24 may be changed. As the state transitions, the current increases and the delay time decreases.

  With the configuration as described above, the digitally controlled oscillator of this embodiment can perform the same operation as the oscillator shown in FIG. That is, when the input 2-bit digital signal is 01 (1 in decimal notation), the ring becomes a path that returns to the inverter 23 via the inverter 23, the switch 27, the inverter 28, the switch 24, and the NOR gate 15. When the input 2-bit digital signal is 10 (2 in decimal notation), the ring becomes a path returning to the inverter 23 via the inverter 23, the switch 27, the inverter 22, the switch 26, and the NOR gate 15. When the input 2-bit digital signal is 11 (3 in decimal notation), the ring becomes a path returning to the inverter 21 via the inverter 21, the switch 25, the inverter 22, the switch 26, and the NOR gate 15. The point that the logic of one round is inverted in these rings is the same as the embodiment shown in FIG.

  This embodiment can be configured only when a transmission / non-transmission changeover switch is prepared as an element library, but conversely, it can be configured even when a three-state buffer is not included in the element library. It can be easily understood that the modification of the embodiment shown in FIG. 1 can be applied.

  Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing a digitally controlled oscillator according to still another embodiment of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. The description of that part is omitted. This embodiment also has the simplest configuration for explaining the principle.

  In this embodiment, the resistors 18a, 19a, 18b, and 18b of the resistance due to the wiring and the accompanying stray capacitance are used, and instead of the three-state buffers 11, 12, 13, and 14, respectively, three elements are provided on the output side of the element 18a. A state buffer 11a connected, a three-state buffer 12a connected to the output side of the element 19a, a three-state buffer 11b connected to the output side of the element 18b, and a three-state buffer 12b connected to the output side of the element 19b I use what I did.

  The elements 18a, 19a, 18b, and 19b are obtained by adjusting the length and / or width of the metal wiring in the integrated circuit to set the resistance value and the stray capacitance associated with the distributed constant to a predetermined value. In general, the longer the wiring, the higher the resistance value and the stray capacitance. As the width of the wiring is increased, the resistance value decreases and the stray capacitance increases. Since the characteristics from the input to the output of the elements 18a, 19a, 18b, and 19b are delay characteristics, the delay time is added to the element 18a and the three-state buffer 11a by the delay time td1, and the element 19a and the three-state buffer 12a. The delay time is td1, the delay time is td2 between the element 18b and the three-state buffer 11b, and the delay time is also td2 between the element 19a and the three-state buffer 12b.

  Therefore, in this embodiment, the three-state buffers 11a and 11b having the same delay time and the three-state buffers 12a and 12b having the same delay time can be used. That is, it is not necessary to prepare a plurality of types having different delay times as three-state buffers, and it is possible to cope with a simpler element library. Although the elements 18a, 19a, 18b, and 19b operate in an analog manner, they can be handled in a normal digital LSI design flow including layout, and do not correspond to the analog circuit elements that are usually said.

  Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a digitally controlled oscillator according to still another embodiment of the present invention. In this embodiment, a more practical and specific design than the oscillator shown in FIGS. 1 to 3 is shown.

  As shown in FIG. 4, the digitally controlled oscillator includes three-state buffers 31 to 65 (5 stages and 7 columns), a NOR gate 71, decoders 72 to 77, a buffer 78, and inverters 81 to 90.

  Each of the three-state buffers 31 to 65 has an input terminal, an output terminal, and an enable terminal, as in the case of the three-state buffers 11 to 14 shown in FIG. Only when the signal is input, the logic signal input to the input terminal is output to the output terminal with the same logic (non-inverted output). When a logic signal to be enabled is not input to the enable terminal, the output terminal is in a high impedance state.

  The buffers 31 to 65 have a five-stage configuration as described above, and seven buffers are connected in parallel at each stage. As shown in the figure, the delay times of these seven buffers are 75.5 ps, 81 ps, 99 ps, 134 ps, 201 ps, 278 ps, and 380 ps, respectively. Note that the delay time of the NOR gate 71 which is one configuration of the ring is set to 75.5 ps, which is the same as that of the fastest buffer.

  Among the buffers 31 to 65, the output side of the final stage (fifth stage) 35, 40, 45, 50, 55, 60, 65 is led as one input to the NOR gate 71, and the output side of the NOR gate 71 Becomes an oscillation output through the buffer 78. Further, the output side of the NOR gate 71 is led as an input to the first stage 31, 36, 41, 46, 51, 56, 61 of the buffers 31 to 65. When the other input DN of the NOR gate 71 is set to the high state, the oscillation output is inevitably fixed to low by the function of the NOR gate 71. That is, the input DN is used when oscillation is stopped as necessary.

  Based on the input 9-bit digital signal, the decoders 72 to 77 output a logic signal that enables at least one of the buffers in each stage as a decoding result. Therefore, the input 9-bit digital signal is first decoded into a 3-bit digital signal for each stage (0 to 7 in decimal notation) by the decoder 72, and the digital signals for each stage are further decoded. Decoding is performed by the decoders 73 to 77, and a logic signal that enables at least one of the buffers in each stage is output as a decoding result.

  Here, when the inputs to the decoders 73 to 77 are 1 in decimal display, the buffers 31 to 35 (first column) are selected to be enabled. The decoders 73 to 77 and the buffers are connected so that the buffers that are enabled are increased as shown in FIG. If the inputs to the decoders 73 to 77 are 0 in decimal display, none of the buffers on the output side is enabled. Decoding specifications of the decoders 73 to 77 including the decoder 72 will be further described later (FIG. 5).

  The inverters 81 and 82 are inverters that are connected in a cyclic manner, and one of the nodes in the cyclic manner is commonly connected to the outputs of the first-stage buffers 31, 36, 41, 46, 51, 56, and 61. The This is because the high / low state of the node to which the outputs of the three-state buffers 31, 36, 41, 46, 51, 56, 61 are connected is maintained at a constant logic regardless of the disabled state of all the buffers. It is a state maintaining circuit that operates so as to be stable. If one of the buffers 31, 36, 41, 46, 51, 56, 61 is enabled, the inverters 81, 82 operate according to their output logic. The set of inverters 83 and 84, the set of inverters 85 and 86, the set of inverters 87 and 88, and the set of inverters 89 and 90 are similar in function to the set of inverters 81 and 82 except that the connected stages are different. It is.

  FIG. 5 is a table showing conversion specifications of the decoders 73 to 77 in the digitally controlled oscillator shown in FIG. More specifically, the decoding values to be output by the decoders 73 to 77 are shown as correspondences with the input digital values, and the decoding specifications of the decoder 72 are also shown from these relationships. Furthermore, since the ring related to oscillation is specified by the selection of the buffers 31 to 65 by the decoder 72 and the decoders 73 to 77, the oscillation frequency calculated from the delay time of one round is also shown.

  From FIG. 5, for example, if the 9-bit input digital value is 129 in decimal notation, the decoder 73 outputs “enables” the buffer 61 in the seventh column because “7” is indicated. Similarly, the decoder 74 performs output for enabling the buffer 62 in the seventh column because “7” is indicated, and the decoder 75 indicates that the third column is indicated because “3”. Since the output of the buffer 43 is enabled, the decoder 76 similarly outputs “3”, so that the output of the buffer 44 in the third column is enabled, and the decoder 77 is indicated by “1”. Therefore, an output for enabling the buffer 35 is performed. The delay time of one round is 380 + 380 + 99 + 99 + 75.5 + 75.5 [ps] due to the ring constituted by these enabled buffers, and the oscillation frequency is 451 MHz as a reciprocal of this double time.

  The way of viewing FIG. 5 is the same for other input digital values. In FIG. 5, a part of the middle is omitted due to the paper width, but when an oscillation frequency that is a specification is given to the input digital value, the creation of FIG. 5 can be performed as follows. In other words, the delay time for one round of the ring is obtained from the oscillation frequency, and the buffers at each stage may be selected so as to be closest to this delay time. The column position from the top of the selected buffer is a numerical value in FIG.

  FIG. 6 is a graph showing the oscillation frequency control characteristics of the digitally controlled oscillator shown in FIG. FIG. 6 shows that the digitally controlled oscillator shown in FIG. 4 controls the level of oscillation frequency (about 253 MHz to about 1104 MHz) according to the magnitude relationship of the input 9-bit digital signal (1 to 428 in decimal notation). This indicates that this is an oscillator.

  The embodiment shown in FIG. 4 described above also shows that in the digitally controlled oscillator, smooth oscillation frequency control according to the change of the input signal can be realized without enlarging the circuit scale. That is, in this embodiment, it is sufficient to prepare 35 elements in 5 stages and 7 rows as the main delay elements constituting the ring. The small circuit scale is obtained by simply changing the number of inverter stages using a digital code. Compared with the case of obtaining.

  That is, in the present embodiment, the input digital value can correspond to a change of 1 to 428 in decimal display. Therefore, it is easy to see how many 428 × 2 inverters are required if we try to obtain a similar response by changing the number of stages of the ring. It takes the number of inverters. In particular, when a low frequency is required, the number of stages is further increased to increase the ring delay time.

  In addition, as described in the embodiment shown in FIGS. 1 to 3, the digital control oscillator shown in FIG. 4 naturally has all the elements necessary for its configuration as digital circuit elements and eliminates analog circuit elements. Therefore, even if a process in which only a digital circuit element is provided as an element library can be easily made. Although it is a variable frequency oscillator, it does not require design as an analog circuit, which is advantageous in terms of cost and shortening the design period. In addition, even when the power supply voltage is lowered as a digital circuit, no problem occurs in correspondence. In addition, it has many advantages such as relatively easy deployment to integrated circuits with different process specifications.

  A more practical and specific embodiment shown in FIG. 4 is based on the inverter and the transmission / non-transmission changeover switch shown in FIG. 2 as each delay element, or the wiring resistance and stray capacitance shown in FIG. The same configuration can be achieved by using a three-state buffer.

1 is a configuration diagram showing a digitally controlled oscillator according to an embodiment of the present invention. The block diagram which shows the digitally controlled oscillator concerning another embodiment of this invention. The block diagram which shows the digitally controlled oscillator which concerns on another embodiment of this invention. The block diagram which shows the digitally controlled oscillator which concerns on another embodiment of this invention. The table | surface which shows the decoding specification of each decoder 73-77 in the digital control oscillator shown in FIG. The graph which shows the oscillation frequency control characteristic of the digital control oscillator shown in FIG.

Explanation of symbols

  11, 11a, 11b, 12, 12a, 12b, 13, 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ... three-state buffer, 15, 71 ... NOR gate, 16, 17 , 72, 73, 74, 75, 76, 77 ... decoder, 18a, 18b, 19a, 19b ... wiring resistance (including distributed constant stray capacitance), 21, 22, 23, 24 ... inverter, 25, 26, 27, 28 ... Transmission / non-transmission changeover switch, 78 ... Buffer, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90 ... Inverter.

Claims (9)

A first first-stage delay element having an input terminal, an output terminal, and an enable terminal;
An input terminal; an output terminal; and an enable terminal; the input terminal is connected to the input terminal of the first first-stage delay element; and the output terminal is the output of the first first-stage delay element. A second first-stage delay element having a delay time greater than a delay time of the first first-stage delay element, connected to a terminal;
A first second-stage delay element having an input terminal, an output terminal, and an enable terminal, the input terminal being connected to both of the output terminals of the first and second first-stage delay elements;
An input terminal, an output terminal, and an enable terminal, wherein the input terminal is connected to both the output terminals of the first and second first-stage delay elements, and the output terminal is the first second-stage delay; A second second-stage delay element having a delay time greater than the delay time of the first second-stage delay element, connected to the output terminal of the element;
A first signal which is supplied to both of the enable terminals of the first and second first-stage delay elements and enables at least one of the first and second first-stage delay elements based on a digital input signal. And at least one of the first and second second-stage delay elements based on the digital input signal and supplied to both the decode terminal and the enable terminals of the first and second second-stage delay elements. And a decoder for generating a second decode output for enabling
The signals at both the output terminals of the first and second stage delay elements are transmitted to both the input terminals of the first and second stage delay elements with the inverted polarity of the signals. A digitally controlled oscillator characterized by   2. The digitally controlled oscillator according to claim 1, wherein each of the first and second first-stage delay elements and the first and second second-stage delay elements is a non-inverting three-state buffer. A first state maintaining circuit connected to both of the output terminals of the first and second first-stage delay elements;
3. The digitally controlled oscillator according to claim 2, further comprising: a second state maintaining circuit connected to both of the output terminals of the first and second stage delay elements. The delay time of the first first-stage delay element is the same as the delay time of the first second-stage delay element;
The digitally controlled oscillator according to claim 1, wherein the delay time of the second first-stage delay element is the same as the delay time of the second second-stage delay element.   The first and second first-stage delay elements and the first and second second-stage delay elements each include an inverter and a transmission / non-transmission changeover switch connected to the output side of the inverter. And having the input terminal on the input side of the inverter, the output terminal on the output side of the transmission / non-transmission switch, and the enable terminal on the switching control input side of the transmission / non-transmission switch The digitally controlled oscillator according to claim 1. A first state maintaining circuit connected to both of the output terminals of the first and second first-stage delay elements;
6. The digitally controlled oscillator according to claim 5, further comprising: a second state maintaining circuit connected to both of the output terminals of the first and second stage delay elements. The input terminal has an input terminal, an output terminal, and an enable terminal. The input terminal is connected to both the input terminals of the first and second stage delay elements, and the output terminal is the first and second ones. A third first-stage delay element having a delay time greater than the delay time of the second first-stage delay element connected to both of the output terminals of the second-stage delay element;
An input terminal, an output terminal, and an enable terminal, wherein the input terminal is connected to the three output terminal of the first, second, and third stage delay elements, and the output terminal is the first, A second second-stage delay element having a delay time longer than a delay time of the second second-stage delay element, connected to both of the output terminals of the second second-stage delay element;
The first decode output of the decoder is supplied to the three enable terminals of the first, second, and third first-stage delay elements and based on the digital input signal, the first, second, second Enable at least one of the first three delay elements
The second decode output of the decoder is supplied to the enable terminals of the first, second, and third second-stage delay elements and based on the digital input signal, the first, second, second 3. The digitally controlled oscillator according to claim 1, wherein at least one of the second stage delay elements is enabled. A first third-stage delay element having an input terminal, an output terminal, and an enable terminal, the input terminal being connected to both of the output terminals of the first and second second-stage delay elements;
An input terminal, an output terminal, and an enable terminal; the input terminal is connected to both of the output terminals of the first and second stage delay elements; and the output terminal is the first third stage delay. A second third-stage delay element having a delay time greater than a delay time of the first third-stage delay element connected to the output terminal of the element;
The first and second third stage delay elements are supplied to both the enable terminals of the first and second third stage delay elements, and at least one of the first and second third stage delay elements is enabled based on the digital input signal. The digitally controlled oscillator according to claim 1, further comprising: a second decoder that generates three decoded outputs.   The first and second first-stage delay elements and the first and second second-stage delay elements each have a resistance, a stray capacitance associated with the resistance, and an input side connected to one end of the resistance. A non-inverting three-state buffer, the input terminal is on the other end side of the resistor, the output terminal is on the output side of the non-inverting three-state buffer, and the enable input side of the non-inverting three-state buffer is 2. The digitally controlled oscillator according to claim 1, wherein the enable terminal is provided.

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