JP2001016099A - Digital pll circuit and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital PLL circuit which operates stably with respect to variations in noise and source voltage. SOLUTION: This digital PLL circuit comprises a phase comparator 1, which compares the phase of a feedback clock 51 with the phase of a reference signal 50, an up/down counter 2 which counts up or down according to the comparison result of the phase comparator 1, a decoder 3 which decodes the count value of the up/down counter 2, and a numerical control oscillator 4, which has its oscillation frequency controlled according to the decoding result of the decoder 3 and outputs the feedback clock 51, and the numerical control oscillator 4 is constituted by using a ring oscillator composed of an odd number of inverters, which are each provided with a varying means for varying the delay times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital PLL.
The present invention relates to a circuit and a control method thereof, and particularly to a digital PLL circuit suitable for reducing clock skew between LSIs and a control method thereof.

[0002]

2. Description of the Related Art In recent years, high-speed system clocks, LS
Due to the miniaturization of I, when an LSI is mounted on a board,
It has become difficult to design the timing of data transfer between SIs, and it has become necessary to use clocks having different phases between LSIs in order to increase the timing margin.

In order to meet this demand, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 7-28847, a voltage controlled oscillator is composed of multi-stage delay elements, and a signal is extracted from the output of each delay element. A circuit has been proposed in which a logical sum of these signals is generated to generate a signal having a timing proportional to the external clock cycle. The method disclosed in this prior art document, as shown in FIG.
Since the circuit configuration controls all delay elements uniformly, the gain against power supply fluctuations increases when the voltage of the LSI system is reduced, making high-precision voltage control more difficult. There is a disadvantage that the characteristics are easily affected by power supply noise and environmental fluctuation.

Further, in the above-mentioned circuit, a logical sum between two predetermined elements is obtained, and if a problem occurs after manufacturing or after mounting on a board, it is necessary to change the outlet of the logical sum. It is not easy, so circuit changes,
There is also a drawback that the production is unavoidable and the cost increases.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to provide a novel digital PLL which operates stably with respect to noise and power supply voltage fluctuations.
A circuit and a control method thereof are provided.

[0006]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, a first aspect of the digital PLL circuit according to the present invention is a phase comparator for comparing a phase of a reference signal with a phase of a feedback clock, and an up-count or down-count based on a comparison result of the phase comparator. A digital PLL circuit comprising an up / down counter, a decoder for decoding a count value of the up / down counter, and a numerically controlled oscillator for controlling an oscillation frequency based on a decoding result of the decoder and outputting the feedback clock. The numerically controlled oscillator is constituted by a ring oscillator composed of an odd number of inverters, and each of the inverters is provided with delay time varying means for varying the delay time,
Also, a second aspect is characterized in that the delay time varying means is a three-state buffer connected in parallel to an inverter, and a third aspect is that the delay time varying means is , A plurality of 3 connected in parallel to the inverter
Characterized by being a state buffer,
In a fourth aspect, the three-state buffer is configured so that conduction and non-conduction thereof are controlled by an output signal of the decoder. The delay time varying means is a series circuit of an inverter and a switching element, which is connected in parallel to the inverter, and a sixth mode is as follows.
A plurality of series circuits of the inverter and the switching element are provided.
According to an aspect, the switching element is configured so that conduction and non-conduction thereof are controlled by an output signal of the decoder, and an eighth aspect configures the ring oscillator. The delay time varying means provided in each of the odd number of inverters has the same configuration, and in a ninth aspect, an output clock of each of the inverters is guided to a multiplexer. ,
An arbitrary clock among the output clocks is selected by the multiplexer.

The digital PLL circuit control method according to the present invention comprises a phase comparator for comparing a phase of a reference signal with a phase of a feedback clock, and counting up or down based on a comparison result of the phase comparator. A digital PL comprising an up / down counter for counting, a decoder for decoding the count value of the up / down counter, and a numerically controlled oscillator for controlling the oscillation frequency based on the decoding result of the decoder and outputting the feedback clock
A method of controlling an L circuit, comprising controlling, based on a decoding result of the decoder, a delay time of each of an odd number of inverters of a ring oscillator constituting the numerically controlled oscillator, whereby an oscillation frequency of the numerically controlled oscillator is controlled. Is controlled.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Digital PLL according to the present invention
A phase comparator that compares a phase of a reference signal with a phase of a feedback clock; an up / down counter that counts up or down based on a comparison result of the phase comparator; and a count value of the up / down counter. And a numerically controlled oscillator for controlling the oscillation frequency based on the decoding result of the decoder and outputting the feedback clock, wherein the numerically controlled oscillator is constituted by a ring oscillator including an odd number of inverters. In addition, each of the inverters is provided with delay time varying means for varying the delay time.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a digital PLL circuit according to the present invention.

FIG. 1 shows a digital PLL according to the present invention.
FIG. 4 is a block diagram showing a configuration of a numerically controlled oscillator, and FIG. 5 is a circuit diagram showing an example of a delay fine adjustment circuit of the numerically controlled oscillator. A phase comparator 1 that compares the phase of the feedback clock 51 with the phase of the feedback clock 51, an up / down counter 2 that counts up or down based on the comparison result of the phase comparator 1, and a count value of the up / down counter 2 is decoded. The oscillation frequency is controlled based on the decoding result of the decoder 3 and the feedback clock 5
Digital P consisting of a numerically controlled oscillator 4 that outputs 1
In the LL circuit, the numerically controlled oscillator 4 is constituted by a ring oscillator composed of an odd number of inverters 6.1 to 6.5, and each of the inverters 6.1 to 6.5 has:
A digital PLL circuit is provided, wherein a delay time varying means 10 for varying a delay time is provided. The delay time varying means 10 includes a plurality of delay time variable means 10 connected in parallel to an inverter 9. 3-state buffer 1
0.1, 10.2
LL circuit is shown, and the three-state buffer 10.
Numerals 1 and 10.2 denote output signals of the decoder 3, the conduction and non-conduction of which are controlled. The digital PLL circuit is characterized by an odd number of output signals constituting the ring oscillator. The digital PLL circuit is characterized in that the delay time varying means 10 provided in each of the inverters has the same configuration, and the output clocks 55.1 to 55.5 of each of the inverters are A digital PLL circuit is shown, wherein the digital PLL circuit is guided to a multiplexer 8 and an arbitrary clock is selected from the output clocks 55.1 to 55.5.

The configuration of a digital PLL circuit according to the present invention will be described below with reference to FIGS.

Referring to FIG. 1, the digital P of the present invention is shown.
The LL circuit detects a direction in which the phase of the reference clock 50 and the phase of the feedback clock 51 shift, and outputs a UP / DOWN command signal 52 to the phase comparator 1 and an UP / DOWN command which is a phase comparison result of the phase comparator 1. An UP / DOWN counter 2 for generating a decoder input signal 53 based on a signal 52;
A decoder 3 that decodes a decoder input signal 53 output from the P / DOWN counter 2 and generates a control signal 54 (54.1 to 54.10) of the numerically controlled oscillation circuit 4
And a numerically controlled oscillation circuit 4 that oscillates at a frequency determined by the control signal 54.

Further, the numerical control type oscillation circuit 4 is configured so that an arbitrary phase proportional to the oscillation frequency can be extracted from the output 60 by the selection signal 56.

FIG. 2 shows a circuit diagram as an example of the phase comparator.

In the phase comparator 1, a feedback clock signal 51 is input to the data side of the DF / F, and a reference clock signal 50 is input to the clock side, and the feedback clock 51 is sampled by the reference clock 50. Thus, the phase lead / lag is configured to be output as the UP / DOWN command signal 52.

The UP / DOWN counter 2 is well known to those skilled in the art, and is not directly related to the present invention.

FIG. 3 shows a truth table of a decoded value with respect to a counter value (decoder input signal 53) as an example of the decoder 3. Here, the counter value is configured to change from 0 to 10, and 10 control signals 54.
1 to 54.10 correspond to the change of the counter value in order.
The configuration is such that the control signal changes from “0” to “1” in this order.
The frequency control command is given to the numerically controlled oscillation circuit 4 at the next stage.

FIG. 4 is a block diagram showing an example of a numerically controlled oscillation circuit.

An odd number of delay fine adjustment circuits 6.1 to 6.5 constituting the numerically controlled oscillation circuit 4 are controlled by control signals 54.1 to 54.1.
54.10 becomes “LOW” level or “HIGH”
The delay value changes depending on the level.

The delay fine adjustment circuits 6.1 to 6.5
The outputs of the delay fine adjustment circuits 6.1 to 6.5 are taken out by buffers 7.1 to 7.5, and the outputs 55.1 to 55.5 are output to the multiplexer 8.
, And an arbitrary one of 55.1 to 55.5 is extracted as an output signal 60 by a selection signal 56.

FIG. 5 is a block diagram showing an example of the delay fine adjustment circuit.

In the example shown in FIG. 5A, each of the fine delay adjusting circuits comprises a basic delay inverting element 9 composed of an inverter and a fine delay adjusting inverting element 10 composed of a three-state inverter.
(10.1, 10.2). In this example,
Two delay fine adjustment inversion elements 10 are provided and connected in parallel to the inverter 9.
0 may be constituted by one or a plurality of 0s may be provided.

The control signal 62.
1 is a control terminal CT of the delay fine-tuning inversion element 10.1
The control signal 62.2 from the decoder 3 is connected to the control terminal CT of the delay fine adjustment inversion element 10.2. These delay fine-tuning inverting elements 10.
1 and 10.2 are control signals 62.1 and 62.2 respectively.
At the LOW "level, the conductive state is established, and the delay time from the input terminal 61 to the output terminal 61 'is reduced.
1 and 62.2 are each in the non-conductive state at the “HIGH” level, and the delay time from the input terminal 61 to the output terminal 61 ′ becomes longer. Control signals 62.1 and 62.2 are both "LO"
10. When the signal is at the “W” level, the delay fine-tuning inverting element
1 and 10.2 are both conductive, and at this time, the delay time from the input terminal 61 to the output terminal 61 'is the shortest.
Becomes

Next, when the control signal 62.1 becomes "HIGH"
When the control signal 62.2 is at the “LOW” level, the delay fine adjustment inversion element 10.1 is in the non-conductive state,
0.2 is a conductive state, and the delay time from the input terminal 61 to the output terminal 61 'at this time is delayed by the non-conduction of the delay fine adjustment inverting element 10.1, and T
+ ΔT.

When both the control signals 62 are at "HIGH" level, the delay fine-adjustment inverting elements 10.1, 1
0.2 are both non-conducting, and the input terminal 6
The delay time from 1 to the output terminal 61 'is the largest
+ 2δT.

FIG. 5B shows another example of the delay fine-adjustment circuit. In this circuit, the delay time varying means is connected in parallel to the inverter 9 by the inverter 10.1A and the switching element 20. 1 in this case, and in this case, a series circuit 3 of an inverter and a switching element.
You may comprise so that 0 may be provided with two or more.

Then, the switching element 20.1,
Reference numeral 20.2 denotes an output signal of the decoder 3, as in FIG. 5A, so that conduction and non-conduction are controlled. As the switching elements 20.1 and 20.2,
What is necessary is just to comprise a transmission gate etc.

Next, the operation of this embodiment will be described.

First, the operation of the entire circuit will be described with reference to the flowchart of FIG.

Referring to FIG. 6, the reference clock 50 and the feedback clock 51 are input to the phase comparator 1 (steps S100 and S101), and the phase comparator 1 determines the phase of the reference clock 50 and the feedback clock 51. Comparison is performed (step S102). When the phase comparison result is determined (step S103), the UP / DO is received based on the result.
The WN counter 2 operates (step S104), and the counter value of the UP / DOWN counter 2 is finally determined (step S105). The decoder 3 is UP / DOWN
While receiving the counter value of the counter 2, the counter value is decoded in order to control the numerically controlled oscillation circuit 4 (step S106). And a numerically controlled oscillation circuit 4
, A decode value is input, the oscillation cycle of the numerical control type oscillation circuit 4 is controlled, and the oscillation cycle is determined (step S1).
07). An output clock 51 synchronized with the reference clock is output from the numerical control type oscillation circuit 4, and the output is input to the phase comparator 1 as a feedback clock 51 (step S108), and steps S100 to S108 are performed.
By repeating the series of operations up to 50, the reference clock 50
And the feedback clock 51 is kept in synchronization. Further, from the numerically controlled oscillation circuit 4, a clock having an arbitrary phase determined by the selection signal 56 in FIG.
It is output as LK1 (step S109, step S110).

Next, the operation of the phase comparator 1 of FIG. 1 will be described with reference to FIG.

First, when the phase of the feedback clock 51 is advanced, the "HIGH" level of the feedback clock 51 is sampled by the reference clock 50 as shown in the waveform of FIG. DOWN command signal 52
Output a "HIGH" level. When the phase of the feedback clock 51 is delayed,
As shown in the waveform of FIG.
The "W" level is sampled by the reference clock 50, and the "LOW" signal is output from the UP / DOWN command signal 52.
The level will be output.

Next, the operation of the UP / DOWN counter 2 in FIG. 1 will be described with reference to FIGS.

The UP / DOWN counter 2 determines, based on the UP / DOWN command signal 52 from the phase comparator 1, whether to perform the UP count or the DOWN count.

Now, the UP / DOWN instruction signal 52 in FIG.
Is at the “HIGH” level, the phase of the feedback clock 51 is advanced, so the phase of the feedback clock 51 needs to be delayed. That is, control is given to the numerical control type oscillation circuit 4 which is the output source of the feedback clock 51,
1 must be delayed. Therefore, in order to delay the phase from the table of FIG. 3, an UP instruction is given to the UP / DOWN counter 2 of FIG. 1, and the counter value is increased (the decoder input signal is increased). As a result, the delay fine adjustment circuit 10 is controlled so as to increase the delay time.

On the other hand, the UP / DOWN instruction signal 52 shown in FIG.
Is at the “LOW” level, the phase of the feedback clock 51 is delayed, so the phase of the feedback clock 51 needs to be advanced. That is, control is given to the numerically controlled oscillation circuit 4 which is the output source of the feedback clock 51,
Must be advanced. Therefore, in order to advance the phase from the table of FIG. 3, the UP / DOWN counter 2 of FIG.
Is given a DOWN instruction, and the counter value becomes DOWN (decreases the decoder input signal). Thereby, the delay fine adjustment circuit 10 is controlled in a direction to decrease the delay time.

Next, the decoder 3 and the numerically controlled oscillation circuit 4
3 will be described in detail with reference to FIGS.

As shown in FIG. 3, when the decoder input signal 53 is input to the decoder 3, the value of the control signal is determined.

That is, in the example of FIG.
Each time 3 is incremented by 1, the control signal 54 is also incremented by one.
Will increase. For example, assuming that the decoder input signal is now in the state of 3, control signals 54.1 to 54.3 are provided.
Up to "1" and from 54.4 to 54.10 "
0 ".

In the state of such a control signal, the decoder control signal 5 is supplied to the delay fine adjustment circuits 6.1 to 6.5 in FIG.
The internal operation of the delay fine adjustment circuits 6.1 to 6.5 when 4.4 to 54.10 are input will be described with reference to FIG.

When "0" is inputted to the input terminal 61 of FIG. 5, the signal passes through the basic delay inversion element 9 and "1" is outputted from the output terminal 61 '.

Here, the delay fine-tuning inverting elements 10.1, 1
T is the delay value when 0.2 is both conductive, and δT is the increase in the delay value when one of the fine delay adjustment inverting elements 10.1 or 10.2 changes from the conductive state to the non-conductive state. Then, since “1” is input to the control signal 62.1 and “0” is input to 62.2, the delay fine adjustment inversion element 10.1 is in a non-conductive state, and the delay fine adjustment inversion element 10.2 is input. Because of the conduction state, the delay time from the input terminal 61 to the output terminal 61 ′ is shorter than that of the delay fine adjustment inversion elements 10.1 and 10.2 both in the conduction state. 10.1 is delayed by the non-conduction state. Therefore, when "0" is input to the delay fine adjustment circuit 6.1, "1" is output from 61.1 after T + δT time. .

Further, the output 6 from the delay fine adjustment circuit 6.1
1.1 is input to the next fine delay adjustment circuit 6.2. As described above, the control signals 54.2 and 54.7 are respectively "
1 "and" 0 ", the output 61.2 outputs" 0 "with a delay of T + δT, which is the same delay time as the delay fine adjustment circuit 6.1. The output 61.2 from 2 is input to the next delay fine adjustment circuit 6.3.In this case, since the control signals 54.3 and 54.8 are "1" and "0" respectively, the output From 61.3, “1” is output with a delay of T + δT of the same delay time as the delay fine adjustment circuit 6.2.

Output 6 from delay fine adjustment circuit 6.3
1.3 is input to the next delay fine adjustment circuit 6.4. In this case, since both the control signals 54.4 and 54.9 are "0", the output 61.4 is delayed by T time. "0" is output.

The output 6 from the fine delay adjustment circuit 6.4
1.4 is input to the next delay fine adjustment circuit 6.5. In this case, the control signals 54.5 and 54.10 are both "0". Circuit 6.3
"1" is output with a delay of T times the same delay time as.

As described above, the output of 61.5, which was initially "0", passed through each delay fine-adjustment circuit in an odd number of stages to become "1". By repeating such control, the numerical control type was obtained. The oscillating circuit 4 performs an oscillating operation, and the delay time of each delay fine adjustment circuit becomes equal, and the locked signal is output as CLK0 via the buffer 7.0.

Here, focusing on the phases of the output signals 55.1 to 55.5, the result is as shown in FIG. That is, the output signal 5
Considering 5.5 as a reference, the output signal 55.2 has a phase that is delayed by 1/5 cycle with respect to the output signal 55.5,
The output signal 55.4 has a phase that is delayed by ／ cycle with respect to the output signal 55.5, and the output signal 55.1 is obtained.
Obtains a phase delayed by 3/5 cycle from the output signal 55.5, and similarly, the output signal 55.3 becomes the output signal 55.5.
A phase delayed by 4/5 cycle from 5 is obtained. These outputs are input to the multiplexer 8 of FIG. 2, a signal of an arbitrary phase is selected by the selection signal 56, and output from the output 60 as CLK 1.

In the specific example described above, the numerical control type oscillation circuit 4 has a configuration in which five stages of delay fine adjustment circuits are connected in a cascade manner. However, it is possible to employ a (2N + 1) stage configuration (N Is an integer of 1 or more). Thus, a phase shifted by (1 / (2N + 1)) from the reference clock is obtained.
Also, as the number of N increases, (1 / (2N +
The number of 1)) is also reduced, and a finer phase can be selected.

In the delay fine adjustment circuit shown in FIG. 5, the control is performed by two control signals.
By setting the number (K is an integer of 1 or more), the total amount of control of the entire numerically controlled oscillation circuit 4 can be adjusted, so that the number of control lines can be set according to the frequency band to be used.

Further, when a large gain is required, the required number of control lines may be controlled collectively instead of controlling the control lines one by one.

With this configuration, the output clock whose phase is shifted by "1 / delay fine adjustment circuit number" in proportion to the reference clock cycle can be stabilized without being affected by manufacturing variations and environmental fluctuations. Can be obtained.

Also, since the fine adjustment elements can be finely adjusted one step at a time, the gain of the entire oscillator can be suppressed, and the influence of voltage fluctuations at low voltage operation is less likely. Therefore, the influence on power supply noise and environmental fluctuation can be suppressed low.

Further, since the delay value by the delay fine adjustment circuit can be slightly increased or decreased, the output cycle and output phase can be synchronized with the reference clock with high accuracy.

FIG. 8 shows the relationship between the decode value and the oscillation period. The decode value is increased or decreased by “1”, that is, 54.1.
From 54.10 to “0” one by one ”
By increasing the number of control lines that take the value of “1”, the oscillation cycle increases stepwise. Also, from the state where all of 54.1 to 54.10 are “1”, one by one “0” The oscillation period decreases stepwise by increasing the value.

On the other hand, when the control is uniformly applied to all the control elements as in the related art, that is, 54.1 to 54.1.
From the state where all of 54.10 are “0”, 54.1 to 54.
When the values up to 5 are changed to “1” at a stretch, the amount of change is five times that when switching one stage at a time, and the jitter characteristic of the PLL results in five times the jitter. The advantage is clear.

[0057]

The digital PLL circuit and its control method according to the present invention have a configuration in which fine control is performed as described above.
Stable operation becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital PLL circuit according to the present invention.

2A is a circuit diagram of a phase comparator, FIG.
(C) is a diagram illustrating the comparison operation.

FIG. 3 is a chart showing an example of an input signal of a decoder and a control signal which is a decode output.

FIG. 4 is a block diagram of a numerically controlled oscillator of the digital PLL circuit of the present invention.

FIG. 5 is a circuit diagram of a fine delay adjustment circuit constituting the numerically controlled oscillator.

FIG. 6 is a flowchart illustrating the operation of the digital PLL circuit of the present invention.

FIG. 7 is a waveform diagram output from the delay fine adjustment circuit.

FIG. 8 is a graph showing a relationship between a decode signal and a delay time.

FIG. 9 is a diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 UP / DOWN counter 3 Decoder 4 Numerically controlled oscillator 6.1-6.5 Fine-delay circuit 7.0-7.5 Buffer 8 Multiplexer 10 Inverting element for fine-delay adjustment 10.1.10.2 3-state buffer 50 reference clock 51 feedback clock 52 UP / DOWN command signal 53 decoder input signal 54, 54.1 to 54.10 control signal 55.1 to 55.5 output signal clock 56 selection signal 60 multiplexer output 61 input terminal 61 'output terminal 61.1 to 61.5 output signal of delay fine adjustment circuit 62.1, 62.2 control signal of decoder CT control terminal of 3-state buffer

Continued on the front page F-term (reference) 5J043 AA02 AA06 AA07 AA11 AA25 BB02 DD00 DD05 DD07 DD08 DD10 DD14 LL01 5J106 AA05 CC03 CC21 CC59 DD19 DD46 GG01 HH01 JJ01 KK14 KK24

Claims (10)

[Claims] 1. A phase comparator for comparing a phase of a reference signal with a phase of a feedback clock, an up / down counter for counting up or down based on a comparison result of the phase comparator, and a count value of the up / down counter. And a numerically controlled oscillator that controls the oscillation frequency based on the decoding result of the decoder and outputs the feedback clock, wherein the numerically controlled oscillator is a ring oscillator including an odd number of inverters. A digital PLL circuit, wherein each of the inverters is provided with delay time varying means for varying a delay time. 2. The digital PLL circuit according to claim 1, wherein said delay time varying means is a three-state buffer connected in parallel to an inverter. 3. The digital PLL circuit according to claim 1, wherein said delay time varying means is a plurality of three-state buffers connected in parallel to an inverter. 4. The digital PLL circuit according to claim 2, wherein the conduction and non-conduction of the three-state buffer is controlled by an output signal of the decoder. 5. The digital PLL circuit according to claim 1, wherein said delay time varying means is a series circuit of an inverter and a switching element connected in parallel to the inverter. 6. The digital PLL circuit according to claim 5, wherein a plurality of series circuits of the inverter and the switching element are provided. 7. The digital PLL circuit according to claim 5, wherein the switching element is configured so that conduction and non-conduction thereof are controlled by an output signal of the decoder. 8. The delay time varying means provided in each of the odd number of inverters constituting the ring oscillator has the same configuration.
The digital PLL circuit according to any one of the above. 9. The clock according to claim 1, wherein an output clock of each of the inverters is guided to a multiplexer, and the multiplexer selects an arbitrary clock among the output clocks. Digital P
LL circuit. 10. A phase comparator for comparing a phase of a reference signal with a phase of a feedback clock, an up / down counter for counting up or down based on a comparison result of the phase comparator, and a count value of the up / down counter. And a numerically controlled oscillator that controls the oscillation frequency based on the decoding result of the decoder and outputs the feedback clock. A method for controlling a digital PLL circuit, comprising: A method for controlling a digital PLL circuit, comprising: controlling a delay time of each of an odd number of inverters of a ring oscillator constituting a numerically controlled oscillator, thereby controlling an oscillation frequency of the numerically controlled oscillator.