JP2007003337A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which makes it hard for the AC timing characteristics of an input circuit and/or output circuit to undergo scattering of electric characteristic during manufacturing and variation of operation conditions such as power source voltage/temperature in use and can contribute in realizing a high-speed interface. <P>SOLUTION: The semiconductor integrated circuit has a measurement control circuit 12 generating measured data for measuring the operation speed of a specific circuit, a measured data output FF circuit 13, a plurality of steps of measured data delay circuit 14 delaying the measured data generated by the measured data output FF circuit, an operation speed detection circuit 15 delayed by the measured data delay circuit and detecting the operation speed of the circuit by latching each measured data of a plurality of bits output from the output nodes in the final step and a middle step synchronizing with a synchronization clock signal. The semiconductor integrated circuit also has an AC timing control circuit provided with a delay quantity switching circuit 20 for switching the delay quantity of a specific data so as to fulfill the AC timing of the specific data output or input from the semiconductor integrated circuit based on the results detected with the operation speed detection circuit 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to an AC timing adjustment circuit used for AC timing adjustment of an input circuit and / or an output circuit, for example, a semiconductor integrated circuit that requires a high-speed interface. is there.

  As an AC timing characteristic of an output circuit of a semiconductor integrated circuit, an output data hold time tHO and a setup time tSU are defined with reference to the rising edge of the output clock signal. In an AC timing adjustment circuit used to adjust the AC timing characteristics of an output circuit so as to satisfy this rule, an output data delay circuit is usually inserted to delay output data. In this case, the number of stages of the output data delay circuit is adjusted and inserted so that the delay amount satisfies tHO under the best conditions. However, the delay amount under the worst condition is about 3.5 to 4 times the delay amount under the best condition. If the output data is too late due to the delay amount under the worst condition, the result is that tSU is compressed. The delay of output data under such worst conditions has a problem that the high-speed interface cannot satisfy the tSU specification.

  On the other hand, in order to adjust the AC timing characteristics of the input circuit (for example, flip-flop circuit), the input circuit of the semiconductor integrated circuit also satisfies the tHO and tSU specifications of the input data with reference to the rising edge of the input clock signal. A timing adjustment circuit is used. In this AC timing adjustment circuit, an input data delay circuit is usually inserted to delay input data. In this case, the number of delay stages of the input data delay circuit is adjusted and inserted so as to meet the delay amount satisfying tHO under the best conditions so as to match the delay by the input buffer with respect to the input clock signal and the delay by the input clock tree synthesis (CTS). .

  However, if the input data is too late due to the amount of delay under worst conditions, it will result in pressure on tSU. The delay of input data under such worst conditions has a problem that it is difficult to match the AC specifications, such as an interface with a high-speed input clock signal cannot satisfy the tSU specification.

In Patent Document 1, the output of the D-type flip-flop circuit is compared with an expected value in order to adjust the output timing of the D-type flip-flop circuit so as to reduce the influence of variations in electrical characteristics during manufacturing. The point that feedback control is performed so as to select a delay cell based on the comparison result is disclosed.
Japanese Patent Laid-Open No. 10-22789

  The present invention has been made to solve the above-described conventional problems, and the AC timing characteristics of the input circuit and / or the output circuit are operations such as variations in electrical characteristics during manufacture, power supply voltage / temperature during use, etc. An object of the present invention is to provide a semiconductor integrated circuit that is less susceptible to changes in conditions and can contribute to the realization of a high-speed interface with the outside even when the clock frequency is significantly switched from a low frequency to a high frequency. .

  A semiconductor integrated circuit according to the present invention includes a measurement control circuit that generates and controls measurement data for measuring the operating speed of a predetermined circuit, a measurement data output flip-flop circuit that outputs measurement data, and the measurement data output flip-flop. A plurality of measurement data delay circuits for delaying measurement data output from the circuit, and a plurality of bits of measurement data delayed by the measurement data delay circuit and output from the output nodes of the last and intermediate stages, An operation speed detection circuit that latches in synchronization with the signal and detects the operation speed of the circuit, and satisfies the AC timing characteristics of predetermined data output or input from the semiconductor integrated circuit based on the result detected by the operation speed detection circuit AC timing adjustment circuit having a delay amount switching circuit for switching the delay amount of the predetermined data Is built in.

  According to the semiconductor integrated circuit of the present invention, the AC timing characteristics of the input circuit and / or the output circuit are not easily affected by variations in electrical characteristics during manufacture and changes in operating conditions such as power supply voltage and temperature during use. Thus, even when the clock frequency is significantly switched from a low frequency to a high frequency, it is possible to realize a high-speed interface with the outside.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing an output data AC timing adjustment circuit in the output circuit of the semiconductor integrated circuit according to the first embodiment of the present invention.

  The circuit of FIG. 1 is a circuit that adjusts the AC timing of the output data DATA with reference to the rising edge of the output clock signal CLOCK, for example, and is roughly divided into an operation speed measuring circuit 10 and an internal clock output from the internal clock signal line 1. A clock buffer 5a that receives the signal and outputs it as an output clock signal CLOCK, an output data latch circuit 2 that latches internal data in synchronization with the internal clock signal, and a delay switching circuit inserted on the output side of the output data latch circuit 2 20 and a data buffer 5b that receives the output of the delay switching circuit 20 and outputs the output data DATA.

  The operation speed measurement circuit 10 includes a measurement control circuit 12 that generates and controls measurement data for measuring the operation speed of a predetermined circuit, a measurement data output flip-flop (FF) circuit 13 that outputs measurement data, and a multi-stage measurement. The data delay circuit 14 is composed of a plurality of stages of speed detection FF circuits 15 and a plurality of stages of synchronization FF circuits 16. The delay switching circuit 20 includes a plurality of stages of output data delay circuits 21 and a plurality of stages of switching multiplexers 22.

  In the operation speed measurement circuit 10, the measurement data output from the measurement data output FF circuit 13 is input to the first stage of a plurality of measurement data delay circuits 14 constituting the operation speed detection circuit, and the operation speed (propagation speed) of the circuit is measured. Is detected. The delay amount (the number of stages of the delay circuit) of the measurement data delay circuit 14 of the plurality of stages is such that it is just reached during one cycle of the measurement clock signal supplied from the measurement clock signal line 11 under the best condition. .

  As the measurement clock signal, it is desirable to use a high-speed clock signal that does not change due to gear switching in the semiconductor integrated circuit, for example, an output clock signal of a phase-locked loop (PLL), which is either synchronous or asynchronous with the internal clock signal. Good. Then, several signals are output from the measurement data delay circuits 14 in a plurality of stages. These several signals are the output terminal of the final stage delay circuit, the output terminal of the delay circuit just before reaching the measurement clock signal in one cycle under the worst condition, and the output terminal of the intermediate delay circuit. Signal. The signal extracted in this way is input to a plurality of stages of speed detection FF circuits 15 and latched in synchronization with the measurement clock signal. In this case, if the signal is latched asynchronously, an unstable state (metastable state) may occur. Therefore, the output of the speed detection FF circuit 15 is further latched by the synchronization FF circuit 16 in synchronization with the measurement clock signal. . That is, a double latch configuration is adopted.

  If the operating condition is the best condition, “1” is latched up to the speed detection FF circuit 15 connected to the rear stage side of the measurement data delay circuit 14, and the output data delay circuit 21 uses this signal to make the longest path. The switching multiplexer 22 is switched so as to select.

  In contrast to the above, if the worst condition is satisfied, the signal does not reach the speed detection FF circuit 15, so that “0” is latched in all the speed detection FF circuits 15, and the output data delay circuit 21 is worsted using this signal. The switching multiplexer 22 is switched so as to select the minimum path necessary for the condition.

  2 shows measurement data output from the measurement data output FF circuit 13, latch enable (EN) signal output from the measurement control circuit 12, and measurement data reaching the speed detection FF circuit 15 in the output circuit of FIG. An example of the timing relationship is shown.

  When the data capture condition ranges (1) to (4) are different, the data fetched into the speed detection FF circuit 15 is different. The measurement data reaching the first stage FF circuit DFF1 of the speed detection FF circuit 15 is “1” in the condition ranges (1) to (4), but becomes “0” when the worst condition is approached. Note that the data contents of the respective stage FF circuits DFF1 to DFF4 of the speed detection FF circuit 15 immediately after the reset operation may be set to desired values, respectively.

  FIG. 3 shows an example of the relationship between the number of stages of the switching multiplexer 22 in FIG. 1, that is, the amount of delay inserted into the output data delay circuit 21 when the number of delay circuit switching stages is small. In FIG. 3, the magnitude relationship between the delay circuit switching stage numbers N1, N2, and N3 is N1 <N2 <N3.

  As shown in FIG. 3, for example, in worst conditions such as low power supply voltage, high operating temperature, and large variations in characteristics of transistors used, the circuit operates at point A in the delay characteristics under the worst conditions. Under the best condition, operation is performed at point F in the figure on the delay characteristic under the best condition.

<Modification of First Embodiment>
In the case where the AC characteristics are severe in the output circuit of FIG. 1, it can be modified to cope with an increase in the number of delay circuit switching stages.

  FIG. 4 shows an example of the relationship between the delay amounts inserted in the output data delay circuit 21 when the number of stages (the number of delay circuit switching stages) of the switching multiplexer 22 in FIG. 1 is large. In FIG. 4, the magnitude relationship between the delay circuit switching stage numbers N1, N2, N3, N4, and N5 is N1 <N2 <N3 <N4 <N5. By increasing the number of delay circuit switching stages in this way, it is possible to narrow the range of the AC timing represented by D1 and D2 in the figure, and thus it is possible to cope with a high-speed interface.

  According to the semiconductor integrated circuit of the first embodiment and the modified example described above, the propagation speed of the internal circuit is detected and the AC timing adjustment delay amount for the output circuit is switched. This makes the AC timing characteristics of the output circuit less susceptible to variations in electrical characteristics during manufacturing and changes in operating conditions such as power supply voltage and temperature during use, and can achieve constant AC timing. . In this case, the use of the synchronous clock signal can be easily realized without requiring special clock adjustment at the time of circuit design.

  In addition, since it is composed only of digital circuits, there is a degree of freedom in design. Furthermore, the accuracy can be easily adjusted by changing the number of speed detection flip-flop circuits. Therefore, even when the clock frequency is largely switched, it is possible to realize a high-speed interface with the outside.

<Second Embodiment>
FIG. 5 is a circuit diagram showing an input data AC timing adjustment circuit in the input circuit of the semiconductor integrated circuit according to the second embodiment of the present invention.

  The present embodiment is a circuit that adjusts the AC timing of the input data DATA with reference to the rising edge of the input clock signal CLOCK, for example, and takes it as internal data. Broadly speaking, it receives the operating speed measurement circuit 10a and the input clock signal CLOCK. A clock buffer 5a for receiving an internal clock signal, a data buffer 5b for receiving input data DATA and generating internal data, and a delay switching circuit 20a inserted on the output side of the data buffer 5b.

  The operation speed measurement circuit 10a of this example has three speed detection points, and the number of switching stages of the switching multiplexer 22 is also switched to three stages according to the number of detection points.

  According to the second embodiment, similar to the output circuit of the first embodiment, the AC timing characteristics of the input circuit are such as variations in electrical characteristics at the time of manufacture and operating conditions such as power supply voltage and temperature at the time of use. It is less affected by changes and can achieve a constant AC timing.

<Third Embodiment>
FIG. 6 is a circuit diagram showing an output data AC timing adjustment circuit in the output circuit of the semiconductor integrated circuit according to the third embodiment of the present invention.

  Compared with the output data AC timing adjustment circuit described above with reference to FIG. 1, the present embodiment has a point in which a synchronization FF circuit 30 for once latching the detected signal with the output clock signal 1 is added. Is different.

  According to this configuration, since the output data is switched in synchronization with the output clock signal, it is possible to prevent whisker-like noise from occurring at the leading edge or trailing edge of the output data when the number of switching stages is changed.

<Fourth Embodiment>
FIG. 7 is a circuit diagram showing an output data AC timing adjustment circuit in the output circuit of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

  Compared with the output data AC timing adjustment circuit described above with reference to FIG. 1, the present embodiment outputs a signal serving as a reference for the AC timing of the output data DATA instead of or in parallel with the output clock signal CLOCK. The difference is that a reference signal output circuit 70 is provided.

  The reference signal output circuit 70 is configured to output an internal clock signal as an output clock signal CLOCK2 through, for example, one flip-flop circuit F / F.

<Fifth Embodiment>
In each of the embodiments, the result detected by the operation speed detection circuit is a signal of a plurality of bits, and the delay amount switching circuit includes a plurality of switching circuits controlled one-to-one correspondingly by the signals of the plurality of bits. It was to be used.

  In the fifth embodiment, a decoder (not shown) for converting the multi-bit signal into a smaller number of bit signals is added, and the delay amount switching circuit is controlled by the output signal of the decoder. These switching circuits may be used.

1 is a circuit diagram showing an output data AC timing adjustment circuit in an output circuit of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 2 is a timing chart showing an example of a timing relationship between measurement data output from a measurement data output FF circuit, a latch enable signal output from a measurement control circuit, and measurement data reaching a speed detection FF circuit in the output circuit of FIG. 1; The characteristic view which shows an example of the relationship of the delay amount inserted in the output data delay circuit in case there are few delay circuit switching stages by the switching multiplexer in FIG. FIG. 3 is a characteristic diagram illustrating an example of a relationship between delay amounts inserted into an output data delay circuit when the number of delay circuit switching stages by the switching multiplexer in FIG. 1 is large. The circuit diagram which shows the input data AC timing adjustment circuit in the input circuit of the semiconductor integrated circuit of the 2nd Embodiment of this invention. The circuit diagram which shows the output data AC timing adjustment circuit in the output circuit of the semiconductor integrated circuit of the 3rd Embodiment of this invention. The circuit diagram which shows the output data AC timing adjustment circuit in the output circuit of the semiconductor integrated circuit of the 4th embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Output clock signal, 2 ... Output data latch circuit, 10 ... Operation speed measurement circuit, 11 ... Measurement clock signal, 12 ... Measurement control circuit, 13 ... Measurement data output flip-flop circuit, 14 ... Measurement data delay circuit, 15 ... Speed detection FF circuit, 16 ... synchronization FF circuit, 20 ... delay switching circuit, 21 ... output data delay circuit, 22 ... switching multiplexer.

Claims (5)

A measurement control circuit for generating and controlling measurement data for measuring the operating speed of the predetermined circuit;
A measurement data output flip-flop circuit for outputting measurement data;
A plurality of measurement data delay circuits for delaying the measurement data output from the measurement data output flip-flop circuit;
An operation speed detection circuit that latches each measurement data of a plurality of bits delayed by the measurement data delay circuit and output from the output node of the final stage and the intermediate stage in synchronization with a synchronous clock signal, and detects the operation speed of the circuit; ,
AC timing provided with a delay amount switching circuit for switching the delay amount of the predetermined data so as to satisfy the AC timing characteristics of the predetermined data output or input from the semiconductor integrated circuit based on the result detected by the operating speed detection circuit A semiconductor integrated circuit comprising an adjustment circuit.   2. The result detected by the operation speed detection circuit is a signal of a plurality of bits, and the delay amount switching circuit has a plurality of switching circuits controlled correspondingly by the signals of the plurality of bits. The semiconductor integrated circuit as described.   The operation speed detection circuit is output from a plurality of stages of delay circuits to which 1-bit measurement data output from the data output flip-flop circuit is input, and from the output nodes of the final stage and the intermediate stage of the plurality of stages of delay circuits. 3. The semiconductor integrated circuit according to claim 2, further comprising a plurality of first latch circuits that latch each measurement data in synchronization with the synchronous clock.   4. The operation speed detection circuit further comprises a plurality of stages of second latch circuits for latching outputs of the plurality of stages of first latch circuits in synchronization with the synchronous clock, respectively. Semiconductor integrated circuit.   The output circuit outputs a clock signal serving as a reference for AC timing together with the output data, and a plurality of third stage latches each of the outputs of the plurality of second latch circuits in synchronization with the clock signal. 2. The semiconductor integrated circuit according to claim 1, further comprising a latch circuit, wherein the delay amount of the output data is switched based on each output of the third latch circuit of the plurality of stages.

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