JP2011082744A - Voltage-controlled oscillator, and amplitude adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillator which solves the problem that time taken for amplitude adjustment is long. <P>SOLUTION: A logic circuit 105 uses each of digital control current sources 102 and 112 to gradually change each value of the generated current together and makes each of the generated current at each stage into different values. Then, the logic circuit 105 calculates each value of the generated current so that amplitude of each of oscillation output signals becomes a desired value according to reference voltage as the optimal value based on comparison results output from comparators 104 and 114 at each stage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage controlled oscillation device having a plurality of voltage controlled oscillators and an amplitude adjustment method.

  In the voltage controlled oscillator, as shown in Patent Document 1, in order to obtain desired phase noise and power consumption, the amplitude of the oscillation output signal of the voltage controlled oscillator is adjusted so as to approach the reference amplitude value. . Further, as shown in Patent Document 2, a plurality of voltage controlled oscillators may be used in order to widen the range of the oscillation frequency of the voltage controlled oscillator.

  FIG. 27 is a block diagram showing a configuration of a voltage controlled oscillator that can adjust the amplitude of the oscillation output signal and has a plurality of voltage controlled oscillators.

  In FIG. 27, the voltage controlled oscillator includes voltage controlled oscillators (VCO) 5101 and 5102, peak amplitude detection circuits (Peak Det.) 5103 and 5104, comparators 5105 and 5106, and a digitally controlled current source (DCCS). 5107 and 5108 and logic circuits (Logic) 5109 and 5110 are included. Here, the voltage control oscillator 5101, the peak amplitude detection circuit 5103, the comparator 5105, the digital control current source 5107 and the logic circuit 5109, the voltage control oscillator 5102, the peak amplitude detection circuit 5104, the comparator 5106, the digital control current source 5108 and The logic circuit 5110 forms an independent feedback loop.

  The logic circuit 5109 is an up / down counter constituted by a digital circuit, and counts an amplitude adjustment code indicating the value of the current generated by the digital control current source 5107.

  FIG. 28 is an explanatory diagram for explaining the operation of the voltage controlled oscillator shown in FIG. In addition, since the same operation | movement is performed in each feedback loop, below, operation | movement of the feedback loop which has the voltage control oscillator 5101 is demonstrated.

  First, in step T1, the amplitude adjustment code of the logic circuit 5109 is initialized to the maximum value, so that the generated current of the digital control current source 5107 is set to the maximum. This generated current is input to the voltage controlled oscillator 5101.

  Note that the amplitude of the oscillation output signal of the voltage controlled oscillator 5101 is proportional to the value of the current input to the voltage controlled oscillator 5101. Accordingly, since the current generated by the digital control current source 5107 is maximized, the amplitude of the oscillation output signal of the voltage controlled oscillator 5101 is also maximized. The amplitude adjustment code is a 4-bit binary signal. The generated current increases as the value of the amplitude adjustment code increases. Therefore, when the amplitude adjustment code is “1111”, the generated current is maximized.

  The peak amplitude detection circuit 5103 outputs a peak voltage corresponding to the amplitude of the oscillation output signal. The comparator 5105 compares the peak voltage from the peak amplitude detection circuit 5103 with the reference voltage (Vref1), and outputs a 1-bit digital signal indicating the magnitude relationship between the peak voltage and the reference voltage. Hereinafter, it is assumed that when the peak voltage is higher than the reference voltage, a digital signal indicating “1” is output, and when the peak voltage is equal to or lower than the reference voltage, a digital signal indicating “0” is output. In step T1, since the peak voltage is higher than the reference voltage, a digital signal indicating “1” is output. The reference voltage is set according to the reference amplitude value described above.

  When the digital signal indicating “1” is output, the next step (step T2) is executed.

  In step T2, the amplitude adjustment code of the logic circuit 5109 is decreased by “1”. As a result, the value of the generated current is reduced by one step, and as a result, the amplitude of the oscillation output signal of the voltage controlled oscillator is also reduced by one step.

  Thereafter, the amplitude adjustment code is decremented by one until the digital signal indicating “0” is output from the peak amplitude detection circuit 5103.

  When a digital signal indicating “0” is output, it can be seen that the peak voltage corresponding to the amplitude adjustment code at that time or the peak voltage corresponding to the amplitude adjustment code one step before is closest to the reference voltage. Therefore, the amplitude adjustment code represents the optimum amplitude of the oscillation output signal.

  In FIG. 28, since the process ends at step T10 which is the tenth step, it can be seen that the peak voltage is closest to the reference voltage when the amplitude adjustment code is “01111” or “0110”.

  As described above, the amplitude of the oscillation output signal of each voltage controlled oscillator can be adjusted by performing the amplitude adjustment processing a plurality of times using the digital signal.

  Note that the amplitude can be adjusted in an analog manner by using an operational amplifier instead of the comparators 5105 and 5106 and using an analog control current source instead of the digital control current sources 5107 and 5108. However, in the analog amplitude adjustment, there is a problem that the oscillation output signal is deteriorated due to the phase noise of the oscillation output signal generated due to the influence of the noise of the operational amplifier. On the other hand, in the digital amplitude adjustment described with reference to FIG. 28, since the low noise bias source can be used for the digital control current sources 5107 and 5109, the deterioration of the oscillation output signal can be reduced.

JP 2006-197571 A JP 2005-45405 A

  In the voltage controlled oscillator shown in FIG. 27, the amplitude of the oscillation output signal is adjusted independently for each voltage controlled oscillator. For this reason, when adjusting the amplitude of the oscillation output signal, it is necessary to shift the amplitude adjustment code one by one for each voltage controlled oscillator to find the optimum amplitude, and there is a problem that it takes a long time to adjust the amplitude. It was.

Specifically, assuming that the time required for one step is X, the time required for amplitude adjustment is 2 ^N X at the maximum. N is the number of bits of the amplitude adjustment code.

  For example, when the time X required for one step is 100 nanoseconds and the number of bits N of the amplitude adjustment code is 4, a maximum of 1.6 microseconds is required. The time per step is substantially equal to the time required for the peak voltage of the amplitude peak detection circuit to stabilize.

  In the future, it is considered that the number of bits of the amplitude adjustment code will increase due to the increase in the variation width of the oscillation output signal accompanying the miniaturization of the CMOS and the lowering of the power supply voltage. In this case, the amplitude adjustment time is further increased.

In addition, the voltage controlled oscillator normally has a rough frequency adjustment function for adjusting the frequency of the oscillation output signal. In the coarse frequency adjustment function, the optimum frequency of the oscillation output signal is determined while shifting the coarse frequency adjustment code by one as in the case of amplitude adjustment. At this time, the amplitude of the oscillation output signal is also shifted every time the frequency coarse adjustment code is deviated. Therefore, each step in the amplitude adjustment needs to be performed for each frequency coarse adjustment code. For this reason, when the frequency coarse adjustment code is an M-bit binary signal, the time required for amplitude adjustment is 2 ^N · 2 ^MX at maximum.

  For example, if the time X required for one step is 100 nanoseconds, the number of bits N of the amplitude adjustment code is 4, and the number of bits M of the frequency coarse adjustment code is 5, a maximum of 51.2 microseconds is required. It becomes.

  In particular, when the voltage controlled oscillator is applied to a technology that is desired to widen the oscillation frequency range, such as a multi-band radio apparatus or a multi-standard radio apparatus, the number of bits of the coarse frequency adjustment code becomes very large. The time required for amplitude adjustment becomes very long.

  An object of the present invention is to provide a voltage-controlled oscillation device and an amplitude adjustment method that solve the above-described problem that the time required for amplitude adjustment is long.

  A voltage-controlled oscillator according to the present invention includes a plurality of current sources and a plurality of voltage-controlled oscillators that output a plurality of oscillation output signals each having an amplitude corresponding to the magnitude of a generated current output from each current source, A plurality of detectors that output each of the peak voltages indicating the amplitude of the oscillation output signal output from each voltage controlled oscillator, and each of the peak voltages output from each detector are compared with the input reference voltage, and the peak Using each of the current sources and a plurality of comparison units that output comparison results indicating the magnitude relationship between the voltage and the input reference voltage, the values of the generated currents are changed together and stepwise. In addition, each of the generated currents at each stage is set to a different value, and based on the comparison result output from each comparison unit at each stage, each amplitude of the oscillation output signal is the input Such that the desired value corresponding to the irradiation voltage, and a control unit for determining the optimum values each value of the generated current.

  An amplitude adjustment method according to the present invention includes a plurality of current sources, a plurality of voltage controlled oscillators that output each of a plurality of oscillation output signals having an amplitude corresponding to the magnitude of the generated current output from each current source, and The amplitude control method using the voltage controlled oscillator having the output of each peak voltage indicating the amplitude of the oscillation output signal output from each voltage controlled oscillator, and comparing each peak voltage with the input reference voltage Then, each of the comparison results indicating the magnitude relationship between the peak voltage and the input reference voltage is output, and each value of the generated current is changed stepwise together using each current source. Each of the generated currents at each stage is set to a different value, and based on the comparison result at each stage, each amplitude of the oscillation output signal is a desired value corresponding to the input reference voltage. Become such, determining the respective values of the generated current as the optimum value.

  According to the present invention, it is possible to shorten the time required for amplitude adjustment.

1 is a block diagram showing a configuration of a voltage controlled oscillator according to a first embodiment. FIG. 3 is a circuit diagram showing a first specific example of a voltage controlled oscillator. It is the circuit diagram which showed the 2nd specific example of the voltage controlled oscillator. It is the circuit diagram which showed the 3rd specific example of the voltage controlled oscillator. It is the circuit diagram which showed the 4th specific example of the voltage controlled oscillator. It is a circuit diagram which shows the 1st specific example of a digital control current source. It is the circuit diagram which showed the 2nd specific example of the digital control current source. It is the circuit diagram which showed the 3rd specific example of the digital control current source. It is the circuit diagram which showed the specific example of the peak amplitude detection circuit. It is the circuit diagram which showed the specific example of the comparator. It is a flowchart for demonstrating an example of operation | movement of the voltage control transmission apparatus of 1st Embodiment. It is explanatory drawing for demonstrating the specific example of operation | movement of the voltage control transmission apparatus of 1st Embodiment. It is explanatory drawing for demonstrating the other specific example of operation | movement of the voltage control transmission apparatus of 1st Embodiment. It is explanatory drawing which showed the example of a specific logic operation of a logic circuit. It is a flowchart for demonstrating the other operation example of the voltage control transmission apparatus of 1st Embodiment. It is explanatory drawing which showed the other specific logic operation example of the logic circuit. It is explanatory drawing for demonstrating the other operation example of the voltage control transmission apparatus of 1st Embodiment. It is explanatory drawing for demonstrating the other operation example of the voltage control transmission apparatus of 1st Embodiment. It is the block diagram which showed the structure of the voltage controlled oscillation apparatus by 2nd Embodiment. It is a flowchart for demonstrating the operation example of the voltage control transmission apparatus of 2nd Embodiment. It is explanatory drawing which showed the relationship between a frequency adjustment code and the frequency of an oscillation output signal. It is explanatory drawing which showed the relationship between a frequency adjustment code and the amplitude of an oscillation output signal. It is explanatory drawing which showed an example of the simulation result of the output characteristic of the peak amplitude detection circuit with respect to the amplitude adjustment code | cord | chord of a voltage controlled oscillator. It is a flowchart for demonstrating the specific example of operation | movement of the voltage control transmission apparatus of 2nd Embodiment. It is a flowchart for demonstrating the specific example of operation | movement of the voltage control transmission apparatus of 2nd Embodiment. It is the block diagram which showed the structure of the voltage controlled oscillation apparatus by 3rd Embodiment. It is a flowchart for demonstrating the operation example of the voltage control transmission apparatus of 3rd Embodiment. It is the block diagram which showed the structure of the voltage controlled oscillation apparatus by 4th Embodiment. It is the block diagram which showed the structure of the voltage controlled oscillation apparatus which is related technology. It is explanatory drawing for demonstrating operation | movement of the voltage controlled oscillation apparatus shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, components having the same function may be denoted by the same reference numerals and description thereof may be omitted.

  FIG. 1 is a block diagram showing the configuration of the voltage controlled oscillator according to the first embodiment of the present invention.

  The voltage controlled oscillator includes voltage controlled oscillators (VCO) 101 and 111, digital controlled current sources (DCCS) 102 and 112, and a peak amplitude detection circuit (Peak-Det .: Peak Detector). ) 103 and 113, comparators 104 and 114, and a logic circuit (Logic: Logic Circuit) 105.

  Voltage controlled oscillator 101, digital control current source 102, peak amplitude detection circuit 103, comparator 104 and logic circuit 105, voltage controlled oscillator 111, digital control current source 112, peak amplitude detection circuit 113, comparator 114 and logic circuit 105 Constitute a feedback loop. In each field back loop, the logic circuit 105 is shared.

  Although the number of feedback loops is 2 in FIG. 1, in practice, it may be more than one. Therefore, a plurality of voltage controlled oscillators, digitally controlled current sources, peak amplitude detection circuits, and comparators may be provided. One logic circuit is shared by each field back loop.

  Each of the voltage controlled oscillators 101 and 111 outputs an oscillation output signal corresponding to the magnitude of the generated current output from each of the digitally controlled current sources 102 and 112. Here, the amplitude of the oscillation output signal changes according to the value of the generated current.

  FIG. 2 is a circuit diagram showing a first specific example of the voltage controlled oscillator. In FIG. 2, the voltage controlled oscillator includes an inductor 1001, a coarse frequency adjustment unit 1002, a fine frequency adjustment unit 1003, and a cross-coupled MOS 1004. Inductor 1001, coarse frequency adjustment unit 1002, fine frequency adjustment unit 1003, and cross-coupled MOS 1004 are connected in parallel.

  The coarse frequency adjustment unit 1002 is a varactor (variable capacitance diode). The frequency coarse adjustment unit 1002 receives a frequency coarse adjustment signal that is an analog signal, and the capacitance (electric capacity) changes according to the inputted frequency coarse adjustment signal.

  The frequency fine adjustment unit 1003 is a switch capacitance element including a capacitor and a switch. A frequency fine adjustment signal, which is a digital signal, is input to the switch of the frequency fine adjustment unit 1003, and the capacity of the frequency fine adjustment unit 1003 changes according to the input frequency fine adjustment signal.

  The cross-coupled MOS 1004 is formed of a pair of nMOSs whose gates and drains are cross-coupled. The cross couple MOS 1004 functions as a negative resistance for canceling out the parasitic resistance component existing in the inductor 1001, the frequency coarse adjustment unit 1002, and the frequency fine adjustment unit 1003.

  The digital control current source is connected to the source of the cross-coupled MOS 1004. Further, the intermediate tap of the inductor 1001 is connected to the power supply terminal.

  The oscillation frequency of the voltage controlled oscillator shown in FIG. 2 is determined according to the resonance frequency determined by the inductance of the inductor 1001 and the capacitance of the frequency coarse adjustment unit 1002 and the frequency fine adjustment unit 1003. Therefore, the oscillation frequency of the voltage controlled oscillator changes by changing the capacity of the frequency coarse adjustment unit 1002 and the frequency fine adjustment unit 1003. Note that a variable inductance element may be further provided in the voltage controlled oscillator. In this case, the oscillation frequency of the voltage controlled oscillator is changed by changing the inductance of the variable inductance element.

  If the voltage-controlled oscillator is configured so that different inductances are used as the inductors 1001 of each voltage-controlled oscillator and the oscillation output signals of those voltage-controlled oscillators are selectively output, the voltage-controlled oscillator It is possible to widen the oscillation frequency. Depending on the application, it may be possible to use an inductance having the same inductance as the inductor 1001 of each voltage controlled oscillator.

  FIG. 3 is a circuit diagram showing a second specific example of the voltage controlled oscillator. The voltage controlled oscillator shown in FIG. 3 is different from the voltage controlled oscillator shown in FIG. 2 in that the digital control current source is connected to the intermediate tap of the inductor 1001 and the GND terminal is connected to the source of the cross-coupled MOS 1004.

  In the voltage controlled oscillator shown in FIG. 3, it is possible to ignore the influence of the substrate bias effect, and it is possible to reduce current consumption.

  FIG. 4 is a circuit diagram showing a third specific example of the voltage controlled oscillator. In addition to the configuration shown in FIG. 2, the voltage controlled oscillator shown in FIG. 4 further includes a cross-coupled MOS 1005 formed of a pair of pMOSs whose gates and drains are cross-coupled. A power supply terminal is connected to the source of the cross-coupled MOS 1005.

  Since the cross-coupled MOS 1005 exists, the rising waveform and falling waveform of the oscillation output signal from the voltage controlled oscillator are symmetric. Therefore, the phase noise due to the 1 / f noise component can be reduced. However, since a parasitic capacitance corresponding to the cross-coupled MOS 1005 is newly added, the oscillation frequency range is narrowed. 2 does not have the cross-coupled MOS 1005, the parasitic capacitance is small, the variable capacitance width of the frequency coarse adjustment unit 1002 and the frequency fine adjustment unit 1003 can be increased, and the oscillation frequency It is advantageous for realizing a wide range of

  FIG. 5 is a circuit diagram showing a fourth specific example of the voltage controlled oscillator. The voltage controlled oscillator shown in FIG. 5 is different from the voltage controlled oscillator shown in FIG. 4 in that the digital control current source is connected to the source of the cross-coupled MOS 1005 and the GND terminal is connected to the source of the cross-coupled MOS 1004.

  The voltage controlled oscillator shown in FIG. 5 has substantially the same characteristics as the voltage controlled oscillator shown in FIG.

  As shown in FIGS. 2 to 5, the voltage controlled oscillators 101 and 111 each have an inductor, and output an oscillation output signal having an amplitude corresponding to the inductance of the inductor and the generated current. Further, the inductances of the inductors of the voltage controlled oscillators 101 and 111 may be different or the same.

  Returning to FIG. Digitally controlled current sources 102 and 112 are sometimes referred to as current sources.

  FIG. 6 is a circuit diagram showing a first specific example of the digital control current source. The digitally controlled current source shown in FIG. 6 is used in combination with the voltage controlled oscillator shown in FIGS.

  In FIG. 6, the digital control current source includes nMOSs 1101 to 1103 and switches 1201 to 1203. Note that the number of nMOSs and switches is 3 in FIG. The number of nMOSs and switches is equal to each other.

  The drains of the nMOSs 1101 to 1103 are commonly connected. The gate widths of the nMOSs 1101 to 1103 are different from each other. More specifically, the gate widths of the nMOSs 1101 to 1103 are binary weighted. For example, when the gate width of the nMOS 1101 is the reference gate width, the gate width of the nMOS 1102 is twice the reference gate width, and the gate width of the nMOS 1103 is four times the reference gate width.

  Further, the generated current of the digital control current source is output from the drain pair of the nMOSs 1101 to 1103.

  The switches 1201 to 1203 are sometimes called gate voltage switches. Each of the switches 1201 to 1203 has a one-to-one correspondence with any one of the nMOSs 1101 to 1103 and switches the gate voltage applied to the gate of the corresponding nMOS.

  As a result, the switches 1201 to 1203 can switch on and off the current flowing through the nMOSs 1101 to 1103. In FIG. 6, the switch 1201 corresponds to the nMOS 1101, the switch 1202 corresponds to the nMOS 1102, and the switch 1203 corresponds to the nMOS 1103.

  For example, a digital control signal a [2: 0] indicating the value of the generated current is input to each of the switches 1201 to 1203. Each of the switches 1201 to 1203 switches on / off of the gates of the nMOSs 1101 to 1103 in accordance with the digital control signal a [2: 0]. Note that turning off the gate means supplying a GND potential to the gate.

  Therefore, each of the switches 1201 to 1203 switches the current flowing through the drains of the nMOSs 1101 to 1103 (that is, the current generated by the digital control current source) stepwise in accordance with the digital control signal a [2: 0]. . This is because the gate width of the MOS and the current flowing through the MOS are in a proportional relationship. Specifically, when the on-current of the nMOS 1101 is I0, the current is a [2] · 4I0 + a [1] · 2I0 + a [0] · I0.

  The current source shown in FIG. 6 can generate the binary weighted generated current relatively accurately. However, since the parasitic capacitance between the MOS drain and GND increases, the influence of power supply noise becomes large.

  FIG. 7 is a circuit diagram showing a second specific example of the digital control current source. The digitally controlled current source shown in FIG. 7 is used in combination with the voltage controlled oscillator shown in FIGS.

  The digital control current source shown in FIG. 7 has a configuration in which the nMOSs 1101 to 1103 of the digital control current source shown in FIG. 6 are replaced with pMOSs 1301 to 1303.

  When the current flowing through the drains of the pMOSs 1301 to 1303 is turned off, the power supply potential (VDD potential) is applied to the gates of the pMOSs 1301 to 1303. The digital control current source shown in FIG. 7 has the same characteristics as the digital control current source shown in FIG.

  As shown in FIGS. 6 and 7, each of the digitally controlled current sources 102 and 112 has a plurality of drains connected in common and having a gate width binary-weighted and outputting a generated current from the commonly connected drains. And a gate voltage switch for switching the gate voltage applied to the gate of each MOS.

  FIG. 8 is a circuit diagram showing a third specific example of the digital control current source. The digitally controlled current source shown in FIG. 8 is used in combination with the voltage controlled oscillator shown in FIGS.

  In FIG. 8, the digital control current source includes an nMOS 1401 and a digital-analog converter (DAC) 1402.

  In the nMOS 1401, the source is grounded. The nMOS 1401 outputs a generated current from the drain.

  The digital-analog converter 1402 receives a digital control signal a [2: 0] that is a digital signal indicating the value of the generated current. The digital control signal a [2: 0] is sometimes called a current control signal.

  The digital-analog converter 1402 performs digital-analog conversion and converts the digital control signal a [2: 0] into an analog control signal that is an analog signal. The digital-analog converter 1402 inputs the analog control signal to the gate of the nMOS 1401, and changes the value of the generated current output from the drain of the nMOS 1401.

  In this case, since the parasitic capacitance existing at the drain end is reduced, the influence of power supply noise can be reduced. However, since the MOS gate voltage and the current flowing through the MOS are in a square relationship, it is difficult to accurately generate a binary-weighted generated current.

  Note that a pMOS may be used instead of the nMOS 1401. Such a digitally controlled current source can be used in combination with the voltage controlled oscillator shown in FIGS.

  Returning to FIG. The peak amplitude detection circuits 103 and 113 are sometimes called detection units. Each of the peak amplitude detection circuits 103 and 113 outputs a peak voltage indicating the amplitude of the transmission output signal output from the voltage controlled oscillator in its own feedback loop.

  FIG. 9 is a circuit diagram showing a specific example of the peak amplitude detection circuit. In FIG. 9, the peak amplitude detection circuit includes an AC coupling unit 1501, a current source 1502, a MOS differential pair 1503, and a low-pass filter 1504.

  The MOS differential pair 1503 includes a pair of nMOSs whose sources are commonly connected. The source pair of the MOS differential pair 1503 is connected to the current source 1502. The drain of each nMOS is connected to the power supply terminal.

  The oscillation output signal of the voltage controlled oscillator is input to the gates of the nMOSs of the MOS differential pair 1503 via the AC coupling unit 1501. As a result, the influence of fluctuations in the DC potential of the voltage controlled oscillator can be removed, and the dynamic range related to peak amplitude detection can be widened.

  In FIG. 9, the oscillation output signal input to the peak amplitude detection circuit is converted into a differential signal. A converter (not shown) for converting the oscillation output signal into a differential signal may be provided in the voltage-controlled oscillator, or may be provided in front of the AC coupling unit 1501 in the peak amplitude detection circuit. The pair 1503 uses a current for amplitude detection generated by the current source 1502 to generate a full-wave rectified rectified signal whose wave height monotonously increases according to the amplitude of the oscillation output signal, and shows a peak indicating the amplitude of the oscillation output signal. Outputs voltage from its own source pair. Note that the current source 1502 may be referred to as a detection current source.

  The peak voltage is input to the low pass filter 1504. The low pass filter 1504 removes the high frequency component of the peak voltage and outputs the peak voltage from which the high frequency component has been removed.

  As described above, the peak amplitude detection circuit shown in FIG. 9 can output a signal monotonously increasing with respect to the amplitude as the peak voltage.

  Note that the time required for stabilizing the output signal of the peak amplitude detection circuit is substantially determined by a time constant determined by the resistance and capacitance of the low-pass filter 1504. Further, by stopping the output of the amplitude detection current from the current source 1502, the amplitude detection current supplied to the peak amplitude detection circuit can be stopped, so that the operation of the peak amplitude detection circuit can be stopped. .

  Returning to FIG. The comparators 104 and 114 are also called a comparison unit. Each of the comparators 104 and 114 compares the peak voltage output from the peak amplitude detection circuit in its own feedback loop with a predetermined reference voltage, and shows a comparison result indicating the magnitude relationship between the peak voltage and the reference voltage. Is output. The reference voltage indicates a peak voltage corresponding to a desired value of the amplitude of the oscillation output signal. The reference voltage may also be referred to as an input reference voltage.

  FIG. 10 is a circuit diagram showing a specific example of the comparator. In FIG. 10, the comparator includes a pMOS differential pair input unit 1601, a current source 1602, an nMOS cross couple 1603, an output amplifier unit 1604, and a switch 1605.

  The pMOS differential pair input unit 1601 may be referred to as an input stage. The pMOS differential pair input unit 1601 is formed of a pair of pMOSs whose sources are commonly connected. The pMOS source pair is connected to a current source 1602. The drain of each pMOS is grounded via an nMOS cross couple 1603. A branch point is provided between the pMOS differential pair input unit 1601 and the nMOS cross couple 1603, and the branch point is connected to the output amplifier unit 1604. In addition, a switch 1605 is provided between the branch point and the output amplifier unit 1604.

  Note that the current source 1602 may be referred to as a comparative current source. The nMOS cross couple 1603 is formed of a pair of nMOSs whose gates and drains are cross-coupled, and functions as a load of the pMOS differential pair input unit 1601.

  A peak voltage is input to one of the gates of the pMOS of the pMOS differential pair input unit 1601, and a reference voltage is input to the gate of the other pMOS.

  As a result, the pMOS differential pair input unit 1601 compares the peak voltage with the reference voltage using the comparison current output from the current source 1602, and outputs the comparison result to the output amplifier unit 1604. .

  The output amplifier unit 1604 is sometimes called an output stage. The output amplifier unit 1604 amplifies and outputs the comparison result output from the pMOS differential pair input unit 1601. More specifically, the output amplifier unit 1604 has an nMOS in which the comparison result output from the pMOS differential pair input unit 1601 is input to the gate, and the voltage between the source and drain of the nMOS is amplified. Output as a comparison result.

  As shown in FIG. 10, the comparator has a two-stage configuration of the pMOS differential pair input unit 1601 and the output amplifier unit 1604, whereby high-precision and high-output characteristics can be obtained. When stopping the operation, the current source 1602 is turned off, and the pMOS differential pair input unit 1601 and the output amplifier are connected by a switch 1605 inserted between the pMOS differential pair input unit 1601 and the output amplifier unit 1604. The current is cut off by setting the portion 1604 to the GND potential. In this case, power consumption can be reduced.

  The specific example of each circuit described above is merely an example, and is not limited to these configurations and can be changed as appropriate.

  Returning to FIG. The logic circuit 105 is sometimes called a control unit. The logic circuit 105 sets an amplitude adjustment code indicating the amplitude of the oscillation output signal in its own circuit, and manages the amplitude of the oscillation output signal using the amplitude adjustment code. The amplitude adjustment code is a multi-bit binary signal. It is assumed that the amplitude of the oscillation output signal increases as the amplitude adjustment code increases. The amplitude adjustment code is set for each voltage controlled oscillator.

  Further, the logic circuit 105 inputs the digital control signal corresponding to the amplitude adjustment code to the digital control current sources 102 and 112, thereby setting the values of the generated currents of the digital control current sources 102 and 112, respectively.

  For example, when the digital control current sources 102 and 112 have the configuration shown in FIG. 6 or 7, the logic circuit 105 inputs digital control signals to the switches 1201 to 1203. When the digital control current sources 102 and 112 have the configuration shown in FIG. 8, the logic circuit 105 inputs a digital control signal to the digital-analog converter 1042.

  Therefore, the logic circuit 105 can change the value of the generated current using each of the digital control current sources 102 and 112.

  In this embodiment, the logic circuit 105 uses the digitally controlled current sources 102 and 112, respectively, to change the values of the generated currents output from the digitally controlled current sources 102 and 112 together from the initial value stepwise. At the same time, the generated current at each stage is set to a different value. Further, the logic circuit 105 generates each of the generated currents so that the amplitude of each oscillation output signal becomes a desired value corresponding to the reference voltage based on the comparison results output from the comparators 104 and 114 at each stage. Find the value as the optimal value.

  As a result, the logic circuit 105 can obtain the optimum value of each generated current in consideration of a plurality of comparison results, so that the number of steps for amplitude adjustment can be reduced.

  For example, the logic circuit 105 maximizes any value of the generated current, and then gradually decreases each value of the generated current until one of the magnitude relationships indicated by the comparison result changes. When the magnitude relationship changes, the logic circuit 105 obtains an optimum value based on the magnitude relationship at that time.

  Further, the logic circuit 105 may obtain an optimum value at each stage by determining the value of the generated current at the next stage based on the comparison result at that stage. An algorithm for obtaining such an optimum value is, for example, binary search.

  In the binary search, the logic circuit 105 divides the possible amplitude range as the amplitude of the oscillation output signal into a plurality of ranges, and sets the amplitude of the oscillation output signal to the boundary value of the plurality of ranges. Then, the logic circuit 105 specifies an amplitude range in which the optimum value is included based on the comparison result of each step, and determines the value of the generated current of the next step within the specified amplitude range.

  The above algorithm is not limited to binary search, and can be changed as appropriate.

  When the logic circuit 105 obtains the optimum value, it sets an amplitude adjustment code indicating the optimum value in its own circuit. The logic circuit inputs the digital control signal corresponding to the set amplitude adjustment code to the digital control current sources 102 and 112, thereby adjusting the value of the current generated by the digital control current sources 102 and 112 to the optimum value. Thereby, the logic circuit 105 can set the amplitude of the oscillation output signal to a desired value.

  Further, when the logic circuit 105 obtains the optimum value, the logic circuit 105 stops outputting the detection current by the current source 1502 of the peak amplitude detection circuits 103 and 113. Further, the logic circuit 105 stops the output of the comparison current from the comparison current source by the current source 1602 of the comparators 104 and 114, and applies the ground voltage to the gate of the output amplifier unit 1604 using the switch 1605. .

  Next, the operation of the voltage controlled transmitter according to this embodiment will be described in detail.

  FIG. 11 is a flowchart for explaining an operation example of the voltage-controlled transmission device of the present embodiment. In the same amplitude adjustment code, the amplitude of the voltage controlled oscillator 111 is the same as or smaller than that of the voltage controlled oscillator 101. Further, it is assumed that the amplitude of the voltage controlled oscillator 111 is larger than the amplitude of the voltage controlled oscillator 101 in the amplitude adjustment code one step lower.

  In the following, the amplitude adjustment code when the amplitude of the oscillation output signal of the voltage controlled oscillator 101 is equal to or greater than the reference voltage and the amplitude is closest to the reference voltage is the optimum amplitude indicating the optimum value of the amplitude of the oscillation output signal. Consider the case where it is determined as an adjustment code. However, an amplitude adjustment code when the amplitude of the oscillation output signal of the voltage controlled oscillator 101 is equal to or smaller than the reference voltage and the amplitude is closest to the reference voltage may be obtained.

  First, the logic circuit 105 sets the amplitude adjustment code of the voltage controlled oscillator 101 to the maximum value, and sets the amplitude adjustment code of the voltage controlled oscillator 101 to a value smaller by 1 bit than the maximum value (step S101). As a result, the amplitude of the oscillation output signal of the voltage controlled oscillator 101 becomes the maximum (Vmax), and the amplitude of the oscillation output signal of the voltage controlled oscillator 111 becomes a value (Vmax-1-step) that is one step lower than the maximum.

  Then, the logic circuit 105 waits for a predetermined settling time (step S102). The set time is the time from when the amplitude adjustment code is set until the peak voltage output from the peak amplitude detection circuits 103 and 113 is stabilized.

  Thereafter, the logic circuit 105 confirms the comparison results (Comp. OUT1, 2) of the comparators 104 and 114 (step S103). In the following, the comparison results of the comparators 104 and 114 are collectively treated as a 2-bit signal. For example, the first bit of the 2-bit signal indicates the comparison result of the comparator 114, and the second bit indicates the comparison result of the comparator 104.

  When the comparison result indicates “11”, that is, when the amplitudes of the oscillation output signals of the voltage controlled oscillators 101 and 111 are both larger than the reference voltage, the logic circuit 105 sets the amplitude adjustment codes of the voltage controlled oscillators 101 and 111. Both are reduced by two steps. (Procedure S104). Thereafter, the logic circuit executes step S102.

  On the other hand, when at least one of the comparison results of the comparators 104 and 114 indicates “0”, that is, when the amplitude of the oscillation output signal of at least one voltage controlled oscillator becomes smaller than the reference voltage, the logic circuit 105 The loop (procedures S102 to S104) is terminated.

  When the comparison result when the loop is terminated indicates “10”, the logic circuit 105 replaces the amplitude adjustment codes of the voltage controlled oscillators 101 and 111, and then waits for a set time. Then, the logic circuit 105 reconfirms the comparison result (step S106).

  When the comparison result when the loop is finished indicates “00”, and when the comparison result is reconfirmed, the logic circuit 105 generates the oscillation output signal of the voltage controlled oscillator 101 based on the comparison result at that time. And the optimum value (Vopt2) of the amplitude of the oscillation output signal of the voltage controlled oscillator 111 are obtained. Then, the logic circuit 105 inputs an optimum amplitude adjustment code indicating the obtained optimum value to the digital control current sources 102 and 112, and sets the optimum value of the amplitude of the oscillation output signal (step S107).

  Next, a specific example of the operation of the voltage control transmitter will be described.

  12 and 13 are explanatory diagrams for describing a specific example of the operation of the voltage control transmission device. In FIG. 12 and FIG. 13, step S101 is referred to as step S1, and thereafter, the step is advanced every time the amplitude adjustment code is reduced by two stages. The amplitude adjustment code is a 4-bit binary signal.

  In FIG. 12, the comparison result indicates “00” in step S5. In this case, it can be seen that there is a reference voltage between the amplitude of the oscillation output signal of the voltage controlled oscillator 111 in step S4 and the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S5. Therefore, the optimum amplitude adjustment code of the voltage controlled oscillators 101 and 111 is uniquely determined by the amplitude adjustment code “1000” of the voltage controlled oscillator 111 at step S4.

  Therefore, the logic circuit 105 adds 1 to the amplitude adjustment code of the voltage controlled oscillator 101 at the time of step S5 to obtain the optimum amplitude adjustment code of the voltage controlled oscillator 101, and the amplitude of the voltage controlled oscillator 111 at the time of step S5. 2 is added to the adjustment code to obtain the optimum amplitude adjustment code of the voltage controlled oscillator 111.

  With such an operation, as shown in FIG. 28, the conventional adjustment of 10 steps for amplitude adjustment can be reduced to 5 steps in this embodiment.

  In FIG. 13, the comparison result indicates “10” in step S5. In this case, unlike the case described in FIG. 12, there is a reference voltage between the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S5 and the amplitude of the oscillation output signal of the voltage controlled oscillator 111 in step S5. As can be seen, the amplitude adjustment code cannot be uniquely determined.

  For this reason, the logic circuit 105 replaces the amplitude adjustment codes of the voltage controlled oscillators 101 and 111 in step S5, and confirms the comparison result of the comparators 104 and 114 at that time (step S6).

  When the comparison result is “01” in step S6, there is a reference voltage between the amplitude of the oscillation output signal of the voltage controlled oscillator 111 in step S6 and the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S6. I understand. Therefore, the optimum amplitude adjustment code of the voltage controlled oscillators 101 and 111 is uniquely determined by the amplitude adjustment code “0111” set in the voltage controlled oscillator 111 at step S6.

  Therefore, the logic circuit 105 adds 1 to the amplitude adjustment code of the voltage controlled oscillator 101 at the time of step S6 to obtain the optimum amplitude adjustment code of the voltage controlled oscillator 101, and adjusts the amplitude of the voltage controlled oscillator at the time of step S6. The code is obtained as the optimum amplitude adjustment code of the voltage controlled oscillator 101.

  If the comparison result is “00” in step S6, the reference voltage is between the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S5 and the amplitude of the oscillation output signal of the voltage controlled oscillator 111 in step S6. I understand that there is. Therefore, the optimum amplitude adjustment code of the voltage controlled oscillator 101 is uniquely determined by the amplitude adjustment code “0111” of the voltage controlled oscillator 101 at the time of step S5, and the optimum amplitude adjustment code of the voltage controlled oscillator 111 is determined in step S4. The amplitude adjustment code “1000” of the voltage controlled oscillator 111 is uniquely determined.

  Therefore, the logic circuit 105 adds 1 to each of the amplitude adjustment codes of the voltage controlled oscillators 101 and 111 at the time of step S6 to obtain the optimum amplitude adjustment code of the voltage controlled oscillators 101 and 111.

  If the comparison result is “11” in step S6, the reference voltage is between the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S6 and the amplitude of the oscillation output signal of the voltage controlled oscillator 101 in step S5. I know that there is. Therefore, the optimum amplitude adjustment code of the voltage controlled oscillator 101 is uniquely determined by the amplitude adjustment code “0110” of the voltage controlled oscillator 101 at the time of step S6, and the optimum amplitude adjustment code of the voltage controlled oscillator 111 is determined in step S6. Is uniquely determined by the amplitude adjustment code “0111” of the voltage controlled oscillator 111.

  Therefore, the logic circuit 105 obtains the amplitude adjustment codes of the voltage controlled oscillators 101 and 111 at step S6 as the optimum amplitude adjustment codes of the voltage controlled oscillators 101 and 111, respectively.

  FIG. 13 shows the case where the comparison result is “01” in step S6.

  FIG. 14 is an explanatory diagram summarizing logical operation examples for obtaining an optimum amplitude adjustment code after the loop is completed.

  In FIG. 14, the first comparison result 201 that is the comparison result at the end of the loop, the second comparison result 202 that is the comparison result after replacement of the amplitude adjustment code, and the logical operation 203 on the amplitude adjustment code of the voltage controlled oscillator 101. And a logical operation 204 for the amplitude adjustment code of the voltage controlled oscillator 111 is shown.

  The logical operations 203 and 204 indicate the logical operation for the amplitude adjustment code at the last step (step S5 or S6 in FIG. 13). Specifically, when the logical operations 203 and 204 indicate “+2”, it indicates that 2 is added to the amplitude adjustment code at the last step, and when the logical operations 203 and 204 indicate “+1”, It indicates that 1 is added to the amplitude adjustment code at the time of step, and when the logical operations 203 and 204 indicate “+0”, it indicates that nothing is added to the amplitude adjustment code at the time of the last step.

  Note that, as shown in FIG. 14, there are four logical operations depending on the comparison result.

  FIG. 15 is a flowchart for explaining another example of the operation of the voltage controlled oscillator according to the present embodiment. FIG. 15 shows an operation when searching for the closest amplitude adjustment code equal to or higher than the reference voltage on the assumption that the amplitudes of the oscillation output signals of the voltage controlled oscillators 101 and 111 are the same in the same amplitude adjustment code. In this case, the amplitude adjustment codes of the voltage controlled oscillators 101 and 111 are the same.

  In FIG. 15, step S106 is not performed as compared with FIG. Therefore, the number of steps can be further reduced.

  FIG. 16 is an explanatory diagram summarizing logical operation examples for obtaining an optimum amplitude adjustment code after the loop is completed in the operation described in FIG.

  In FIG. 16, a comparison result 301 at the end of the loop, a logical operation 302 for the amplitude adjustment code of the voltage controlled oscillator 101, and a logical operation 303 for the amplitude adjustment code of the voltage controlled oscillator 111 are shown.

  Similar to the logical operations 203 and 204 in FIG. 14, the logical operations 302 and 303 indicate logical operations for the amplitude adjustment code at the last step.

  As shown in FIG. 16, there are two logical operations according to the comparison result.

  FIG. 17A and FIG. 17B are explanatory diagrams for explaining an operation example of the voltage control transmission device when the optimum value of amplitude is obtained using binary search.

  17A and 17B show the value of the amplitude adjustment code at each step for setting the amplitude adjustment code. 17A, the reference voltage is near the center of the full scale that can be set as the amplitude of the oscillation output signal. In FIG. 17B, the reference voltage is near the minimum value of the full scale that can be set as the amplitude of the oscillation output signal. It is in.

  In this case, the logic circuit 105 first sets the amplitude adjustment codes of the voltage controlled oscillators 101 and 111 to values that divide the full scale that can be set as the amplitude of the oscillation output signal into three equal parts. Based on the comparison results of the comparators 104 and 114, the logic circuit 105 can specify which range has the reference voltage among the three equally divided ranges.

  For example, in the first step U1 of FIG. 17A, the comparison result of the comparators 104 and 114 is “10”, and the amplitude of the oscillation output signal of the voltage controlled oscillator 101 and the amplitude of the oscillation output signal of the voltage controlled oscillator 111 are It can be seen that there is a reference voltage in the range between.

  In the first step V1 of FIG. 17B, the comparison result of the comparators 104 and 114 is “11”, and the minimum value of the oscillation output signals of the voltage controlled oscillators 101 and 111 and the oscillation output signal of the voltage controlled oscillator 111 are It can be seen that there is a reference voltage in the range between the amplitudes.

  Subsequently, the logic circuit 105 further divides the range where the reference voltage exists into three equal parts, and sets the amplitude adjustment code to the boundary value of the three divided ranges.

  The logic circuit 105 can obtain the optimum amplitude adjustment code value by repeating the above operation. In the example of FIG. 17A, the amplitude adjustment code at the third step, step U3, is the optimum amplitude adjustment code, and in the example of FIG. 17B, the amplitude adjustment code at the third step, step V3, is one. The value obtained by adding is the optimum amplitude adjustment code.

  If such a binary search is used, the number of steps can be reduced compared to the operations described with reference to FIGS. However, depending on the voltage controlled oscillator, oscillation may stop when a small amplitude adjustment code is set. In such a case, it may not be possible to search for an optimal amplitude adjustment code using binary search. Therefore, when searching for the optimum amplitude adjustment code using binary search, it is necessary to ensure that the voltage controlled oscillator oscillates in all amplitude adjustment codes.

  According to the present embodiment, the voltage controlled oscillators 101 and 111 output a plurality of oscillation output signals having amplitudes corresponding to the magnitudes of the generated currents output from the digital control current sources 102 and 112, respectively. Peak amplitude detection circuits 103 and 113 output peak voltages indicating the amplitudes of the oscillation output signals output from voltage controlled oscillators 101 and 111, respectively. Comparators 104 and 114 compare each of the peak voltages output from each of peak amplitude detection circuits 103 and 113 with a reference voltage, and compare each of the comparison results indicating the magnitude relationship between the peak voltage and the reference voltage. Output. The logic circuit 105 uses each of the digitally controlled current sources 102 and 112 to change each value of the generated current in a stepwise manner, and to change the generated current in each step to a different value. Then, the logic circuit 105 generates each of the generated currents so that the amplitude of each oscillation output signal becomes a desired value corresponding to the reference voltage based on the comparison results output from the comparators 104 and 114 at each stage. Find the value as the optimal value.

  In this case, each value of the generated current is changed stepwise. In addition, each of the generated currents at each stage has a different value. Then, the peak voltage indicating the amplitude of the oscillation output signal is compared with the reference voltage, and the optimum value of the generated current is obtained based on the comparison result.

  For this reason, each optimum value of the generated current can be obtained in consideration of a plurality of comparison results, so that the number of steps related to amplitude adjustment can be reduced. Therefore, it is possible to shorten the time required for amplitude adjustment.

  In the present embodiment, the voltage controlled oscillators 101 and 111 each have an inductor, and output an oscillation output signal having an amplitude corresponding to the inductance of the inductor and the current generated by the digital control current source. Further, the inductances of the inductors of the voltage controlled oscillators 101 and 111 are different from each other.

  In this case, it is possible to widen the oscillation frequency range of the voltage controlled oscillator.

  In the present embodiment, the digitally controlled current sources 102 and 112 include a plurality of MOSs that output a generated current from the drains, the drains of which are connected in common and whose gate width is binary weighted, and currents flowing through the MOSs. A plurality of gate voltage switches for switching on and off. Further, the logic circuit 105 changes each value of the generated current by turning on / off the gate voltage switch.

  In this case, the value of the generated current can be accurately changed.

  In this embodiment, the digital control current sources 102 and 112 convert the digital control signal into an analog control signal when a MOS that outputs the generated current and a digital control signal indicating the value of the generated current are input. And a digital-analog converter that inputs the analog control signal to the gate of the MOS and changes the value of the generated current. In addition, the logic circuit 105 inputs a current control signal to the digital-analog converter of each current source, and changes each value of the generated current.

  In this case, the influence of power supply noise can be reduced.

  Further, in the present embodiment, the logic circuit 105 maximizes any value of the generated current, and then gradually decreases each value of the generated current until the magnitude relationship indicated by the comparison result changes. When the magnitude relationship changes, an optimum value is obtained based on the magnitude relationship at that time. In this case, the optimum value can be obtained more accurately.

  In this embodiment, the logic circuit 105 obtains the optimum value by binary search. In this case, the time required for amplitude adjustment can be further shortened.

  Next, a second embodiment of the present invention will be described.

  FIG. 18 is a block diagram showing a configuration of a voltage controlled oscillator according to the second embodiment of the present invention. In FIG. 18, the voltage controlled oscillator includes a memory circuit (Memory) 106 in addition to the configuration shown in FIG. Note that the memory circuit 106 may be referred to as a storage unit.

  In the present embodiment, the logic circuit 105 sequentially changes the frequency of the oscillation output signal, obtains an optimum value for each frequency of the oscillation output signal, and stores the optimum value corresponding to each frequency in the memory circuit 106. .

  At this time, when the logic circuit 105 obtains the optimum value corresponding to the frequency at each frequency, the logic circuit 105 sets the amplitude of the oscillation output signal at that time as an initial value, and obtains the oscillation output when obtaining the optimum value corresponding to the next frequency. The signal amplitude is changed stepwise from the initial value.

  Thereafter, when the frequency signal indicating the frequency of the oscillation output signal is input, the logic circuit 105 acquires the optimum value corresponding to the frequency indicated by the frequency signal from the memory circuit 106, and the value of the generated current is obtained. Adjust to the value.

  Next, the operation of the voltage controlled transmitter according to this embodiment will be described in detail.

  FIG. 19 is a flowchart for explaining an example of the operation of the voltage controlled transmitter according to this embodiment.

  The logic circuit 105 sets a frequency adjustment code indicating the frequency of the oscillation output signal in its own circuit, and manages the frequency of the oscillation output signal using the frequency adjustment code. The frequency adjustment code is a multi-bit binary signal. It is assumed that the frequency of the oscillation output signal increases as the frequency adjustment code increases.

  Further, the logic circuit 105 generates a coarse frequency adjustment signal and a fine frequency adjustment signal according to the frequency adjustment code. The logic circuit 105 inputs the generated frequency coarse adjustment signal and frequency fine adjustment signal to the frequency coarse adjustment unit 1002 and the frequency fine adjustment unit 1003 of the voltage controlled oscillators 101 and 111, respectively, thereby the frequency of the oscillation output signal. To change.

First, the logic circuit 105 sets the frequency adjustment code (F _VCO1,2 ) of the voltage controlled oscillators 101 and 111 to the minimum value (F _min1,2 ) and the amplitude adjustment code (V _VCO1,2 ) of the voltage controlled oscillators 101 and 111 _{. 2} ) is set to the maximum value (V _min1,2 ) (step S301). That is, the logic circuit 105 sets the frequency of the oscillation output signal of the voltage controlled oscillators 101 and 111 to the lowest state.

  Next, the logic circuit 105 performs the operation described with reference to FIGS. 11 and 13, and stores the optimum amplitude adjustment code, which is the result, in the memory circuit 106 in association with the frequency adjustment code (step S302).

  Then, the logic circuit 105 determines whether or not the frequency adjustment code is maximum (step S303). When the frequency adjustment code is the maximum, the logic circuit 105 ends the operation. If the frequency adjustment code is not the maximum, the logic circuit 105 increases the frequency adjustment code by one (step S304), and then executes step S301.

  At this time, the logic circuit 105 performs the search for the amplitude adjustment code without resetting the amplitude adjustment code to the maximum value.

  20A is an explanatory diagram showing the relationship between the frequency adjustment code and the frequency of the oscillation output signal, and FIG. 20B is an explanatory diagram showing the relationship between the frequency adjustment code and the amplitude of the oscillation output signal. In FIG. 20A, the horizontal axis indicates the frequency adjustment code, and the vertical axis indicates the frequency of the oscillation output signal. In FIG. 20B, the horizontal axis indicates the frequency adjustment code, and the vertical axis indicates the amplitude of the oscillation output signal.

  As shown in FIG. 20A, the frequency of the oscillation output signal is switched in stages according to the frequency adjustment code.

  As shown in FIG. 20B, when the frequency of the oscillation output signal is switched stepwise by the frequency adjustment code, the amplitude of the oscillation output signal also changes stepwise. As shown in FIGS. 2 to 5, the parasitic resistance of the capacitance in the voltage controlled oscillator increases or decreases according to the on / off state of the frequency fine adjustment unit 1003 that is the switch capacitance in the voltage controlled oscillator. Because. Specifically, when the switch capacitance is turned off, the frequency of the oscillation output signal increases and the amplitude of the oscillation output signal also increases.

  FIG. 21 is an explanatory diagram showing an example of the simulation result of the output characteristics of the peak amplitude detection circuit with respect to the amplitude adjustment code of the voltage controlled oscillator in the same frequency adjustment code. In FIG. 21, the horizontal axis represents the amplitude adjustment code, and the vertical axis represents the peak voltage. The amplitude adjustment code changes with time. The voltage controlled oscillator 111 is designed to oscillate at a frequency of 5 to 7 GHz, and the voltage controlled oscillator 101 is oscillated at a frequency of 7 to 10 GHz. In this case, the voltage controlled oscillation device can cover a frequency range of 2 to 10 octaves of 5 to 10 GHz.

  As shown in FIG. 21, the peak voltage from the peak amplitude detection circuit 103 corresponding to the voltage controlled oscillator 101 is almost the same as the peak voltage from the peak amplitude detection circuit 113 corresponding to the voltage controlled oscillator 111. There are some differences. This slight voltage difference is due to inductance in the voltage controlled oscillators 101 and 111.

  FIG. 22 is an explanatory diagram showing a specific example of the operation described with reference to FIG.

  First, the logic circuit 105 sets the frequency adjustment code to “00000” at a minimum and searches for an optimum amplitude adjustment code.

  In this case, in step S6, which is the sixth step, the logic circuit 105 obtains “0111” as the optimum amplitude adjustment code, associates the optimum amplitude adjustment code with the current frequency adjustment code “00000”, and stores the memory. Store in circuit 106.

  Next, the logic circuit 105 raises the frequency adjustment code to “00001” by one step.

  At this time, it is assumed that the amplitude of the oscillation output signal increases by ΔVF. Therefore, the optimum amplitude adjustment code when the frequency adjustment code is “00001” is guaranteed to be equal to or less than the optimum amplitude adjustment code “0111” when the frequency adjustment code is “00000”.

  Accordingly, in step S7, which is the next step, the logic circuit 105 obtains an optimum amplitude adjustment code using the amplitude adjustment codes “0111” and “0110” as initial values. In this case, the comparison result is “00” in step S8, which is the eighth step, and the logic circuit 105 obtains the optimum amplitude adjustment code “0110”.

  With such a configuration, it is possible to create a lookup table indicating the relationship between the frequency adjustment code and the optimum amplitude adjustment code. If this lookup table is created at initial startup, the optimum amplitude adjustment code can be read from the lookup table during amplitude adjustment during actual operation, greatly increasing the time required for amplitude adjustment during actual operation. Can be reduced. This is particularly useful when the frequency must be changed frequently. Further, since the lookup table is created without resetting the amplitude adjustment code to the maximum value for each frequency adjustment code, the creation time can be shortened.

  FIG. 23 is a flowchart for explaining another example of the operation of the voltage controlled oscillator according to the present embodiment. Hereinafter, an example of an operation when the amplitude adjustment code is reset to the maximum value for each frequency adjustment code will be described.

  In this case, steps S301 to S303 are executed as in the case of FIG. Thereafter, the logic circuit 105 increments the frequency adjustment code by one and resets the amplitude adjustment code to the maximum value (step S305). Then, the logic circuit 105 executes step S301.

  With such a configuration, amplitude adjustment can be performed regardless of the amplitude change characteristic with respect to frequency adjustment code switching. Specifically, the amplitude change characteristic is a characteristic in which the amplitude increases as the frequency adjustment code increases as shown in FIG. Therefore, amplitude adjustment can be performed regardless of the order of the frequency adjustment codes. This is particularly effective when the frequency range of the oscillation output signal is small.

  According to the present embodiment, the logic circuit 105 sequentially changes the frequency of the oscillation output signal, obtains an optimum value for each frequency of the oscillation output signal, and stores the optimum value corresponding to each frequency in the memory circuit 106. To do. After that, when a frequency signal indicating the frequency of the oscillation output signal is input, the logic circuit 105 acquires an optimum value corresponding to the frequency indicated by the frequency signal from the memory circuit 106, and the obtained optimum value is calculated for the generated current. Value.

  In this case, the time for amplitude adjustment during actual operation can be greatly reduced.

  In this embodiment, when the logic circuit 105 obtains the optimum value corresponding to the frequency at each frequency, the logic circuit 105 obtains the optimum value corresponding to the next frequency using the amplitude of the oscillation output signal at that time as an initial value. In this case, the amplitude of the oscillation output signal is changed from its initial value.

  In this case, the time for obtaining the optimum value can be shortened.

  Next, a third embodiment of the present invention will be described.

  The optimum amplitude of the oscillation output signal of the voltage controlled oscillator may be different for each voltage controlled oscillator. In this case, the input reference voltage of the comparator is different for each comparator. In the present embodiment, a voltage-controlled oscillation device that is effective when the input reference voltage of the comparator is different for each comparator will be described.

  FIG. 24 is a block diagram showing the configuration of the voltage controlled oscillator in the present embodiment. The voltage controlled oscillator shown in FIG. 24 is different from the voltage controlled oscillator shown in FIG. 1 in that the reference voltages input to the comparators 104 and 114 are independent from each other.

  In this embodiment, first, the logic circuit 105 obtains the optimum value by setting the input reference voltages of the comparators 104 and 114 to the same value. For example, the logic circuit 105 sets one of the true reference voltages of the comparators 104 and 114 as the reference voltage of both the comparators 104 and 114.

  When obtaining the optimum value, the logic circuit 105 changes the reference voltage of the comparators 104 and 114 to a true reference voltage, and adjusts the obtained optimum value based on the comparison result of the comparators 104 and 114.

  FIG. 25 is a flowchart for explaining an operation example of the voltage controlled oscillator according to the present embodiment.

  The logic circuit 105 inputs the same reference voltage to the comparators 104 and 114 (step S401). Subsequently, as described with reference to FIGS. 11 and 15, the logic circuit 105 obtains an optimum amplitude adjustment code (step S402).

  Thereafter, the logic circuit 105 inputs reference voltages having different values to the comparators 104 and 114 (step S403).

  As a result, the magnitude relationship indicated by the comparison result usually changes. At this time, it is assumed that the reference voltage input in step S401 is close to the reference voltage input in step S403. In this case, the true optimum amplitude adjustment code is close to the amplitude adjustment code obtained in step S402.

  For this reason, the logic circuit 105 obtains the optimum amplitude adjustment code as described with reference to FIGS. 11 and 15 by using the optimum amplitude adjustment code as an initial value (step S402).

  With such a configuration, even when desired reference amplitude values are not the same, amplitude adjustment can be performed in a short time.

  In this embodiment, the logic circuit 105 obtains the optimum value of the amplitude of the oscillation output signal by setting the input reference voltages of the comparators 104 and 114 to the same value. Thereafter, the logic circuit 105 sets the input reference voltages of the comparators 104 and 114 to different values, and adjusts the obtained optimum value based on the comparison results of the comparators 104 and 114.

  For this reason, even when the optimum value of the amplitude of the oscillation output signal differs for each voltage controlled oscillator, it is possible to reduce the time required for amplitude adjustment.

  Next, the best mode for carrying out the fourth invention of the present invention will be described in detail with reference to the drawings.

  FIG. 26 is a block diagram showing a configuration of the voltage controlled oscillator according to the present embodiment. In FIG. 26, the voltage controlled oscillator includes a memory circuit 106 in addition to the configuration shown in FIG.

  In the present embodiment, as in the second embodiment, the logic circuit 105 obtains an optimum value for each frequency of the oscillation output signal. At this time, the logic circuit 105 obtains an optimum value corresponding to each frequency as in the third embodiment.

  Thereafter, the logic circuit 105 stores the optimum value of each frequency in the memory circuit 106 as in the second embodiment. Further, when a frequency signal is input, the logic circuit 105 acquires an optimum value corresponding to the frequency indicated by the frequency signal from the memory circuit 106, and sets the obtained optimum value as the value of the generated current.

  In the present embodiment, it is possible to configure a voltage controlled oscillation device having both the characteristics of the second embodiment and the characteristics of the third embodiment.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

101, 111 Voltage controlled oscillator 102, 112 Digitally controlled current source 103, 113 Peak amplitude detection circuit 104, 114 Comparator 105 Logic circuit 106 Memory circuit 1001 Inductor 1002 Frequency coarse adjustment unit 1003 Frequency fine adjustment unit 1004, 1005 Cross couple MOS
1101-1103, 1401 nMOS
1201 to 1203, 1605 switches 1301 to 1303 pMOS
1401 Digital-analog converter 1501 AC coupling unit 1502, 1602 Current source 1503 MOS differential pair 1504 Low-pass filter 1601 pMOS differential pair input unit 1603 nMOS cross couple 1604 output amplifier unit

Claims (13)

Multiple current sources;
A plurality of voltage controlled oscillators that output each of a plurality of oscillation output signals having an amplitude corresponding to the magnitude of the generated current output from each current source;
A plurality of detectors for outputting each of the peak voltages indicating the amplitude of the oscillation output signal output from each voltage controlled oscillator;
A plurality of comparison units that compare each of the peak voltages output from each detection unit with an input reference voltage and output a comparison result indicating a magnitude relationship between the peak voltage and the input reference voltage,
Using each current source, each value of the generated current is changed together and stepwise, and each of the generated currents in each step is changed to a different value, and is output from each comparison unit in each step. A voltage-controlled oscillation having a control unit that obtains each value of the generated current as an optimum value based on the comparison result so that each amplitude of the oscillation output signal becomes a desired value according to the input reference voltage apparatus. The voltage controlled oscillator according to claim 1,
Each voltage controlled oscillator has an inductor, and outputs an oscillation output signal having an amplitude corresponding to the inductance of the inductor and the generated current,
A voltage controlled oscillator in which the inductance of each inductor of each voltage controlled oscillator is different. In the voltage controlled oscillation device according to claim 1 or 2,
Each current source
A plurality of MOS transistors whose drains are connected in common and whose gate width is binary weighted and outputs the generated current from the drain;
A gate voltage switch for switching a gate voltage applied to the gate of each MOS,
The said control part is a voltage control oscillation apparatus which changes each value of the said generated electric current using the gate voltage switch of each current source. In the voltage controlled oscillation device according to claim 1 or 2,
Each current source
A MOS that outputs the generated current;
When a current control signal, which is a digital signal indicating the value of the generated current, is input, the current control signal is converted into an analog signal, and the current control signal converted into the analog signal is input to the gate of the MOS -An analog converter,
The voltage control oscillation device, wherein the control unit inputs the current control signal to a digital-analog converter of each current source to change each value of the generated current. In the voltage controlled oscillation device according to any one of claims 1 to 4,
Each detector is
A current source for detection;
A MOS differential pair that rectifies the oscillation output signal using the detection current output from the detection current source and outputs the rectified oscillation signal as the peak voltage;
When the control unit obtains the optimum value, the control unit stops output of the detection current from the detection current source. In the voltage controlled oscillation device according to any one of claims 1 to 5,
Each comparator is
An input stage that compares the peak voltage with the reference voltage using the comparison current source and the comparison current output from the comparison current source, and outputs the result as the comparison result;
An output stage for amplifying and outputting the comparison result output from the input stage,
When the control unit obtains the optimum value, the control unit stops output of the comparison current from the comparison current source. In the voltage controlled oscillation device according to any one of claims 1 to 6,
The control unit sets any value of the generated current to a maximum value, and then gradually decreases each value of the generated current until the magnitude relationship indicated by the comparison result changes. A voltage-controlled oscillation device that obtains the optimum value based on the magnitude relationship at the time when the value changes. In the voltage controlled oscillation device according to any one of claims 1 to 6,
The control unit is a voltage controlled oscillation device that determines a value of a next stage of the generated current in each stage based on a comparison result of the stage. In the voltage controlled oscillation device according to claim 8,
The voltage control oscillation device, wherein the control unit specifies an amplitude range in which the optimum value is included based on the comparison result, and determines a value of a generated current in a next stage within the specified amplitude range. The voltage controlled oscillator according to any one of claims 1 to 9,
A storage unit;
The control unit sequentially changes the frequency of the oscillation output signal, obtains the optimum value for each frequency, stores the optimum value corresponding to each frequency in the storage unit, and then the oscillation output signal When a frequency signal indicating the frequency of the input signal is input, an optimum value corresponding to the frequency indicated by the frequency signal is acquired from the storage unit, and the value of the generated current is adjusted to the acquired optimum value. apparatus. The voltage controlled oscillator according to claim 10,
When the control unit obtains the optimum value corresponding to the frequency at each frequency, the amplitude of the oscillation output signal at that time is set as an initial value, and when obtaining the optimum value corresponding to the next frequency, A voltage-controlled oscillator that changes the amplitude from the initial value. The voltage controlled oscillator according to any one of claims 1 to 11,
The control unit obtains the optimum value by setting the input reference voltage of each comparison unit to the same value, and then sets each input reference voltage of each comparison unit to a different value, based on the comparison result of each comparison unit, A voltage controlled oscillator that adjusts the optimum value. Amplitude adjustment by a voltage-controlled oscillator having a plurality of current sources and a plurality of voltage-controlled oscillators that output each of a plurality of oscillation output signals having an amplitude corresponding to the magnitude of the generated current output from each current source A method,
Output each peak voltage indicating the amplitude of the oscillation output signal output from each voltage controlled oscillator,
Each peak voltage is compared with the input reference voltage, and each of the comparison results indicating the magnitude relationship between the peak voltage and the input reference voltage is output.
Using each current source, each value of the generated current is changed stepwise together, and each of the generated currents in each step is changed to a different value, and the oscillation is made based on the comparison result in each step. An amplitude adjustment method for obtaining each value of the generated current as an optimum value so that each amplitude of an output signal becomes a desired value according to the input reference voltage.

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