JP2010233180A - Variable delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continuously set a delay time in detail with high-accuracy and wide variable delay width in a simple and compact configuration. <P>SOLUTION: A variable delay circuit provided with at least two sets of a fine motion unit and a coarse motion unit as delay circuit units and a selection circuit to switch each delay circuit unit. The variable delay circuit sets delay time of a second fine motion unit of a second delay circuit unit to a minimum value before delay time of a first fine motion unit of a first delay circuit unit is set to a maximum value, sets the delay time of the second fine motion unit of the second delay circuit unit to a maximum value before the delay time of the first fine motion unit of the first delay circuit unit is set to a minimum value, and switches from the first delay circuit unit to the second delay circuit unit by the selection circuit after the delay time of a second coarse motion unit of the second delay circuit unit is set so that the delay time of the first delay circuit unit and the second delay circuit unit become equal to each other. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a variable delay circuit capable of delaying an input signal and controlling a delay time.

  In optical transmission / reception systems, a small delay time is increased for input signals and clock signals to compensate for differences in path lengths of optical transmission lines, skew due to wavelength dispersion, etc., and skew due to differences in wiring length in semiconductor integrated circuits. There is a need for a delay circuit that can be set with accuracy and a wide variable width.

FIG. 5 shows a first configuration example of a conventional variable delay circuit (Non-Patent Document 1).
In FIG. 5, a conventional variable delay circuit is formed by connecting a plurality of delay circuits 91 in a cascade, branching the outputs of the delay circuits 91 and inputting them to a selector 92, and selecting and outputting one of them. The delay time is set according to the number of stages of the delay circuit.

FIG. 6 shows a second configuration example of a conventional variable delay circuit.
In FIG. 6, the conventional variable delay circuit has a configuration in which a plurality of variable load capacitors 94 are connected to an inverter 93 and a delay time corresponding to the capacitance value is set.

P. Chen, et.al., "A Portable Digitally Controlled Oscillator Using Novel Varactors", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL.52, NO.5, MAY 2005

  The minimum delay time that can be set in the first configuration example of the conventional variable delay circuit shown in FIG. 5 is limited to a delay time that can be set by one delay circuit if the delay time of each delay circuit is fixed. The variable delay width is determined by the product of the minimum delay time and the number of connection stages. Therefore, in order to achieve both a wide variable delay width and a minute delay time setting, it is necessary to reduce the minimum delay time set by one delay circuit and increase the number of connection stages. There is a problem that the circuit area is deteriorated, the circuit configuration is complicated, and the circuit area increases.

  The minimum delay time that can be set in the second configuration example of the conventional variable delay circuit shown in FIG. 6 is determined by the variable range of one variable load capacitor. However, since the variable range is generally limited, the variable delay width at one stage is reduced, and it is necessary to connect variable load capacitors in multiple stages to obtain a wide variable delay width. On the other hand, a large capacity may be used to obtain a wide variable delay width in one stage, but there is a problem that the waveform deteriorates when a high-speed signal is handled.

  The present invention provides a variable delay circuit capable of continuously setting a minute delay time with high accuracy and a wide variable delay width without being limited to a variable range of a variable load capacitance with a simple and small configuration. The purpose is to do.

  A variable delay circuit according to a first aspect of the present invention sets a minute delay time of less than 1 bit time of a data signal and has a variable delay width of a predetermined range at n bit time or more (n is an integer of 1 or more). Are connected in cascade with a coarse motion unit that sets the delay time in 1-bit units of the data signal, and when the delay time set in the fine motion unit is reduced by n bit time from the maximum value, the coarse motion unit increases n bit time. When the delay time set in the fine movement section is increased by n bits from the minimum value, the coarse movement section reduces the n bit time, and the delay time is continuously changed beyond the variable delay width of the fine movement section. is there.

  According to a second aspect of the present invention, there is provided a variable delay circuit comprising at least two sets of the fine movement part and the coarse movement part constituting the variable delay circuit of the first invention as a delay circuit part, and a selection circuit for switching each delay circuit part. The delay time of the second fine movement section of the second delay circuit section is set to the minimum value before the delay time of the first fine movement section of the first delay circuit section is set to the maximum value, or Before the delay time of the first fine movement unit of the first delay circuit unit is set to the minimum value, the delay time of the second fine movement unit of the second delay circuit unit is set to the maximum value, After setting the delay time of the second coarse movement unit of the second delay circuit unit so that the delay times of the delay circuit unit and the second delay circuit unit are equal, the selection circuit sets the delay time from the first delay circuit unit to the second delay circuit unit. The configuration is switched to two delay circuit units.

  In the first or second invention, the fine movement section is connected in parallel between the input terminal and the output terminal, and the data signals at the input terminals are delayed by the delay times Ta and Tb (Ta> Tb) when operated individually. ), The delay unit A and the delay unit B output to the output terminal and the analog control signals X and Y are input, and the amount of current flowing through the delay unit A and the delay unit B is changed according to the difference (XY). And a current control unit that sets a delay time that continuously changes in accordance with a difference (XY) between the delay times Ta and Tb.

  The variable delay circuit of the present invention realizes a wide variable delay width exceeding the variable delay width of the fine movement section by combining with the coarse movement section while setting a minute delay time of less than 1 bit time of the data signal in the fine movement section. be able to.

  The variable delay circuit according to the present invention includes at least two delay circuit units each including a fine movement unit and a coarse movement unit, and the delay time of the fine movement unit of the first delay circuit unit reaches the maximum value (minimum value). By completing the shift operation of the delay time of the fine movement section and coarse movement section of the delay circuit section 2, the correct delay time can be continuously obtained without being affected by the shift operation of the delay time of the fine movement section and coarse movement section. Can be output.

  The fine movement part of the variable delay circuit of the present invention uses the current control part to convert the currents flowing in the delay part A and the delay part B having inherent delay times Ta and Tb (Ta> Tb) into analog control signals X and Y, respectively. By controlling according to the difference between the delay times, the delay time can be continuously changed within the range of the delay times Ta and Tb. As a result, a minute delay time can be continuously varied with high accuracy and a wide variable width with a simple and small configuration.

It is a figure which shows the structural example of Example 1 of the variable delay circuit of this invention. It is a figure which shows the structural example of Example 2 of the variable delay circuit of this invention. It is a figure which shows the structural example of the coarse movement part. It is a figure which shows the structural example of the fine movement part. It is a figure which shows the 1st structural example of the conventional variable delay circuit. It is a figure which shows the 2nd structural example of the conventional variable delay circuit.

FIG. 1 shows a configuration example of a variable delay circuit according to a first embodiment of the present invention.
In FIG. 1, the variable delay circuit according to the first embodiment has a configuration in which a fine movement unit 11 that finely adjusts a delay time and a coarse movement unit 12 that performs coarse length are cascade-connected between an input terminal and an output terminal of a data signal. is there. The fine movement unit 11 is configured to be able to set a minute delay time of less than 1 bit time of the data signal in accordance with the control signal C1 input from the outside, and the variable delay width is n bit time or more (n is 1 or more) ) And a predetermined range, for example, n bit time or more and less than (n + 1) bit time. The coarse movement unit 12 has a configuration in which a delay time can be set in units of one bit time according to a control signal C2 and a clock signal CLK having the same bit rate as the data signal input from the outside, and the variable delay width is n bits. The value is sufficiently larger than the time. The order of the fine movement portion and the coarse movement portion may be changed.

  When the delay time set by the fine movement unit 11 reaches or approaches the maximum value, the delay time set by the fine movement unit 11 is reduced by n bit time and at the same time, the delay time set by the coarse movement unit 12 is reduced by n bit time. increase. When the delay time set by fine movement unit 11 reaches or approaches the minimum value, the delay time set by fine movement unit 11 is increased by n bit time and at the same time the delay time set by coarse movement unit 12 is set to n. Decrease bit time.

  That is, the delay time in units of bit time is transferred between the fine movement unit 11 and the coarse movement unit 12 so that the total delay time of the fine movement unit 11 and the coarse movement unit 12 is the same. As a result, it is possible to realize a wide variable delay width exceeding the variable delay width of the fine movement section 11 by combining with the coarse movement section 12 while setting a minute delay time of less than 1 bit time of the data signal in the fine movement section 11. it can.

FIG. 2 shows a configuration example of the variable delay circuit according to the second embodiment of the present invention.
2, the variable delay circuit according to the second embodiment includes a first delay circuit unit 10-1 configured by cascading a fine movement unit 11-1 and a coarse movement unit 12-1, a fine movement unit 11-2, and a coarse movement. The second delay circuit unit 10-2 having a configuration in which the units 12-2 are connected in cascade are arranged in parallel, the data signal input terminals are connected to the fine movement units 11-1 and 11-2, and the coarse movement unit 12- One of the outputs 1 and 12-2 is selected by the selector 13 and connected to the output terminal. The fine movement units 11-1 and 11-2 are configured to be able to set a minute delay time less than one bit time of the data signal in accordance with the control signals C1 and C1 ′ input from the outside, and have a variable delay width. The predetermined range is n bit time or more, for example, n bit time or more and less than (n + 1) bit time. Coarse movement units 12-1 and 12-2 can be configured to set a delay time in units of one bit time in accordance with control signals C2 and C2 ′ input from the outside and a clock signal CLK having the same bit rate as the data signal The variable delay width is set to a value sufficiently larger than the n bit time. The order of the fine movement portion and the coarse movement portion may be changed.

  Here, the selector 13 selects the output of the first delay circuit unit 10-1 including the fine movement unit 11-1 and the coarse movement unit 12-1, and the fine movement unit 11-1 of the first delay circuit unit 10-1. If the delay time set by the fine movement unit 11-2 of the second delay circuit unit 10-2 is reduced by n bit times with respect to the delay time of the fine movement unit 11-1 At the same time, the delay time set by the coarse motion unit 12-2 is increased by n bit times with respect to the delay time of the coarse motion unit 12-1. Further, when the delay time of the fine movement section 11-1 of the first delay circuit section 10-1 approaches the minimum value, the delay time set by the fine movement section 11-2 of the second delay circuit section 10-2 is set. At the same time as increasing the n-bit time with respect to the delay time of the fine movement section 11-1, the delay time set by the coarse movement section 12-2 is decreased with respect to the delay time of the coarse movement section 12-1.

  That is, the fine delay unit 11-2 and the coarse adjustment unit of the delay circuit unit 10-2 are set so that the total delay time of the delay circuit unit 10-1 and the delay circuit unit 10-2 is the same. Set to 12-2 respectively. Thereby, before the delay time of the fine movement part 11-1 of the delay circuit part 10-1 reaches the maximum value (minimum value), the fine movement part 11-2 and the coarse movement part 12-2 of the delay circuit part 10-2. The delay time shift operation can be completed. When the delay time of the fine movement unit 11-1 reaches the maximum value (minimum value), the selector 13 switches from the output of the coarse movement unit 12-1 to the output of the coarse movement unit 12-2. The correct delay time can be continuously output without being affected by the shift operation of the delay time of the coarse movement unit. The same applies to switching from the delay circuit unit 10-2 to the delay circuit unit 10-1.

(Configuration example of coarse motion part)
FIG. 3 shows a configuration example of the coarse motion unit 12.
In FIG. 3, the coarse motion unit 12 includes a shift register 41 that performs a shift operation by a clock signal CLK, and a selector 42 that selects and outputs one of the outputs of the shift register 41 by a control signal C2.

  The variable delay circuit of the present invention can be configured by using the conventional variable delay circuit shown in FIG. 5 or 6 as the fine movement unit 11 and in combination with the coarse movement unit 12 shown in FIG.

(Configuration example of fine movement part)
FIG. 4 shows a configuration example of the fine movement unit 11.
In FIG. 4, a delay unit A1 and a delay unit B2 are connected in parallel between differential inputs IN and IN and differential outputs OUT and OUT . Here, buffer circuits 14 and 15 are connected in front of the delay unit A1 and the delay unit B2, and the differential inputs IN and IN are connected to the delay units A1 and B2 through the buffer circuits 14 and 15, respectively. The delay unit A1 and the delay unit B2 have their own delay times Ta and Tb (Ta> Tb), respectively, and when they are individually operated, the input signals at the input terminals are delayed by the delay times Ta and Tb (Ta> Tb). Output to the output terminal. The current control unit 3 is connected to the delay unit A1 and the delay unit B2. The current control unit 3 receives the analog control signals X and Y, changes the amount of current flowing through the delay unit A1 and the delay unit B2 according to the difference (X−Y), and determines the difference between the delay times Ta and Tb ( A delay time that continuously changes in accordance with (XY) is set.

  The delay unit A1 has a configuration using differential transistors 21 and 22 and load capacitors 31 and 32, and the delay unit B2 has a configuration using differential transistors 23 and 24 and a peaking capacitor 33. Note that the peaking capacitor 33 of the delay unit B2 may be replaced with a peaking coil. Thereby, the delay times Ta and Tb of the delay unit A1 and the delay unit B2 are set so as to satisfy the relationship Ta> Tb.

  The current control unit 3 has a collector connected to a common emitter of the differential transistors 21 and 22, a transistor 25 connected to the base of the analog control signal X, and a collector connected to a common emitter of the differential transistors 23 and 24. A transistor 26 having an analog control signal Y connected to the base and a current source 34 connected to a common emitter of the transistors 25 and 26 are configured.

When the analog control signals X and Y have a sufficient difference, for example, a difference of about ± 100 mV, the transistors 25 and 26 operate as switches, current flows only in the delay unit A1 or only in the delay unit B2, and the delay time t is
t = Ta or t = Tb
Set to On the other hand, when the analog control signals X and Y have the same magnitude or the difference between them is small, a current corresponding to the difference (X−Y) flows through the delay unit A1 and the delay unit B2.
Ta>t> Tb
The delay time t is set.

  The variable delay circuit of the present invention can continuously set a minute delay time with high accuracy and a wide variable delay width with a simple and small configuration.

1 Delay part A
2 Delay part B
3 Current Control Unit 11 Fine Control Unit 12 Coarse Control Unit 13 Selector 14, 15 Buffer Circuit 21, 22 Differential Transistor 23, 24 Differential Transistor 25, 26 Transistor 31, 32 Load Capacitance 33 Peaking Capacitance 34 Current Source 41 Shift Register 42 Selector

Claims (3)

A fine delay part that sets a minute delay time of less than 1 bit time of the data signal and has a variable delay width within a predetermined range with n bit time or more (n is an integer of 1 or more), and delay in 1 bit unit of the data signal Cascade connection with coarse adjustment part to set time,
When the delay time set in the fine movement part is reduced by the n bit time from the maximum value, the coarse movement part increases the n bit time, and the delay time set in the fine movement part is increased from the minimum value to the n bit time. The variable delay circuit is configured to reduce the n-bit time in the coarse movement unit when the delay time is changed and continuously change the delay time beyond the variable delay width of the fine movement unit. A variable delay circuit comprising at least two sets of the fine movement section and the coarse movement section constituting the variable delay circuit according to claim 1 as a delay circuit section, and a selection circuit for switching each delay circuit section.
Before the delay time of the first fine movement unit of the first delay circuit unit is set to the maximum value, the delay time of the second fine movement unit of the second delay circuit unit is set to the minimum value, or the first Before the delay time of the first fine movement section of the delay circuit section is set to the minimum value, the delay time of the second fine movement section of the second delay circuit section is set to the maximum value, and the first delay circuit After the delay time of the second coarse movement unit of the second delay circuit unit is set so that the delay times of the second delay circuit unit and the second delay circuit unit become equal, the second circuit from the first delay circuit unit is A variable delay circuit characterized by being configured to switch to the delay circuit section. The variable delay circuit according to claim 1 or 2,
The fine movement part is
A delay unit A and a delay unit B, which are connected in parallel between the input terminal and the output terminal and output the data signal of the input terminal to the output terminal with delay times Ta and Tb (Ta> Tb) when individually operated. When,
Analog control signals X and Y are input, the amount of current flowing through the delay unit A and the delay unit B is changed according to the difference (X−Y), and the difference (X−Y) between the delay times Ta and Tb. And a current control unit that sets a delay time that continuously changes in response to a variable delay circuit.

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