JP4010328B2 - Delay circuit - Google Patents

Description

  The present invention relates to a delay circuit that outputs an input signal by delaying it by a predetermined delay time, and more particularly to a delay circuit that controls a delay time and an oscillation frequency according to a digital signal.

  An example of a delay circuit in which the delay time can be arbitrarily set according to the digital control signal is shown in FIG. As shown in the figure, the delay circuit selects n outputs from n stages of delay elements DLY1, DLY2,..., DLYn connected in series and n output signals from these delay elements. It consists of a selection circuit SEL. The n stages of delay elements connected in series output a delay signal obtained by delaying the input signal by a predetermined time to the delay element of the next stage. The selection circuit SEL selects and outputs one of the output signals of the n-stage delay elements according to the digital control signal.

For example, if each delay element is to provide the same delay time t _D input signal, the configured delay circuit as shown in FIG. 32, the t _D ~nt _D delay time in steps of t _D with respect to the input signal Can be given arbitrarily.

An example of an oscillation circuit configured using a delay circuit is shown in FIG. As shown in the figure, the delay circuit shown in FIG. 32 is provided with an inverter INV1, the output signal of the selection circuit SEL is input to the inverter INV1, and the output signal of the inverter INV1 is input to the delay element DLY1 of the first stage as the input signal of the delay circuit Is done. An oscillation signal (clock signal) CLK is obtained from the output circuit terminal of the selection circuit SEL.
That is, an oscillation circuit is constituted by a delay circuit connected in a ring shape (annular) through an inverter. Since the oscillation frequency of the oscillation circuit is controlled by the delay time of the delay circuit, the frequency of the clock signal CLK can be controlled by controlling the delay time using a digital control signal.

  Another example of an oscillation circuit that controls the oscillation frequency with a digital signal is shown in FIG. This example is composed of a digital / analog converter (D / A converter) DAC and a voltage controlled oscillator (VCO). The digital / analog converter DAC converts the digital control signal into a control voltage signal VC which is an analog signal. The oscillation frequency of the voltage controlled oscillator VCO is controlled by the control voltage signal VC. Thereby, the frequency of the clock signal CLK generated by the voltage controlled oscillator VCO can be controlled by the digital control signal.

  FIG. 35 shows an example of an oscillation circuit that changes the capacitance with a digital signal and controls the oscillation frequency in accordance with the capacitance change. As shown in the figure, the on / off states of the switches SW0, SW1, SW2,..., SWn are controlled according to the digital signal, and the total capacitance value of the capacitive element connected to the oscillation circuit OSC is controlled accordingly. The Since the oscillation frequency of the oscillation circuit OSC is set according to the capacitance of the connected capacitive element, the frequency of the clock signal CLK obtained from the oscillation circuit OSC can be controlled by a digital control signal.

  By the way, since the conventional digital control oscillation circuit described above, for example, the oscillation circuit shown in FIGS. 34 and 35 includes analog design elements, the oscillation frequency range depends on the specification of the oscillation circuit and the process of the LSI (large scale integrated circuit). There is a disadvantage that it is necessary to design and modify a troublesome circuit in consideration of trade-offs such as linear tee (linear characteristics) and circuit scale.

  On the other hand, a digitally controlled oscillation circuit configured with a selection circuit as shown in FIG. 33 using a normal gate circuit such as an inverter or a buffer as a delay element has a simple circuit configuration and no analog elements. Control of signal frequency and stability of circuit operation are good. However, since the delay time per one normal delay element is large, the frequency step width is large, and it is difficult to set the oscillation frequency finely.

For example, when the delay element is constituted by a two-stage inverter as shown in FIG. 36, the output terminal A of the preceding inverter constituted by the pMOS transistor PT1 and the nMOS transistor NT1 is the pMOS transistor PT2 constituting the latter inverter. And connected to both gates of the nMOS transistor NT2, the load on the inverter increases, and the operation speed decreases. Also, as shown in the waveform diagram of FIG. 37, the threshold voltage of the normal inverter is half of the power supply voltage VDD, that is, the output signal level of the inverter is about when the level of the input signal becomes approximately VDD / 2. since changes, the delay time t _D per stage inverter is increased.

  An object of the present invention is to provide a delay circuit that can finely control the delay time, reduce the step width of the oscillation frequency of the oscillation circuit, and can be controlled by a digital signal with a simple circuit configuration.

In order to achieve the above object, the present invention is a delay circuit in which a delay time is set in accordance with a control signal, and delays an input signal of a first input terminal by a predetermined time and outputs it to the first output terminal. a first delay element which, in response to said control signal, said first output signal and the input signal of the second input terminal of the delay element either second one of the signal delayed by a predetermined time A plurality of basic circuits each including a second delay element to be output to the output terminal are provided, and the first output terminal of each basic circuit is connected to the first input terminal of the next basic circuit. The second input terminal of the basic circuit of each stage is connected to the second output terminal of the basic circuit of the next stage, and the basic circuit inverts an input signal to the first input terminal to First inversion means for outputting to the first node and the first output signal by inverting the signal of the first node. A second inverting means for outputting to the terminal, a third inverting means for inverting the input signal to the second input terminal and outputting to the second node, and a signal for inverting the signal at the second node. A fourth inversion means for outputting to the second output terminal, and connected between the first input terminal and the second output terminal, and the on / off state is controlled in accordance with the first control signal. A plurality of delay elements each including a first switch and a second switch connected between the first and second nodes and controlled in an on / off state according to a second control signal, The first output terminal of the delay element of the stage is connected to the first input terminal of the delay element of the next stage, and the second input terminal of the delay element of the next stage is connected to the delay element of the next stage. It is configured to be connected to the second output terminal.

According to the present invention, a delay circuit is configured by connecting a plurality of delay elements in series, the delay elements are set in a precharge state in advance according to a precharge control signal, and each delay element is set according to a level change of an input signal. The state changes sequentially, and the change in signal level is sequentially transmitted to the output side of the delay circuit by each delay element. Since the delay time of the delay element is small, it is possible to finely adjust the delay time of the delay circuit configured thereby.
Further, a basic circuit composed of two stages of upper and lower delay elements forms two signal propagation paths, that is, a return path and a return path, and a selection means is provided between the propagation paths to constitute a ladder-type delay circuit. A signal propagation path is set by the selection means in accordance with the input delay control signal, and the delay time of the delay circuit is controlled accordingly. As a result, it is possible to easily cope with the increase / decrease of the delay time by increasing / decreasing the number of basic circuits, and the linear characteristic of the delay amount with respect to the delay control signal can be maintained without the maximum delay stage affecting the minimum delay time. .

  Further, according to the present invention, the selection means for controlling the delay path is constituted by a switch whose on / off state is controlled in accordance with the delay control signal, and in an actual circuit, it can be realized by one transistor. Therefore, the generation of unnecessary delay time in the selection means can be suppressed.

  By using the delay circuit of the present invention, an annular oscillation circuit can be configured by inverting the output signal of the delay circuit and feeding it back to the input side. In the oscillation circuit configured as described above, a plurality of oscillation signals having different oscillation frequencies and duty ratios can be obtained with fine change steps, and a wide range of oscillation frequencies can be handled by increasing or decreasing the number of basic circuits constituting the delay circuit. The minimum oscillation frequency can be set low, and the maximum oscillation frequency of the oscillation circuit is not affected by the adjustment of the minimum oscillation frequency. The linear characteristic of the oscillation frequency of the oscillation circuit with respect to the control signal is good. The frequency range that can be oscillated can be set widely.

  Further, according to the present invention, the first and second delay circuits whose delay times can be controlled independently are connected in series, and the output signal of the second delay circuit is inverted to form the first delay circuit. An annular oscillation circuit is configured by inputting, and the oscillation frequency and duty ratio can be controlled from the output side of the first delay circuit by independently setting the delay times of the first and second delay circuits. A signal is obtained.

According to the delay circuit of the present invention and the oscillation circuit using the delay circuit, the delay amount of the delay element is small, and the delay time can be controlled more finely. In addition, the maximum delay amount of the delay circuit can be dealt with by increasing or decreasing the number of stages of delay elements, the input / output position of the signal on the chip can be fixed, the maximum delay time can be set without affecting the minimum delay time, digital control There is an advantage that the delay time can be controlled by the signal, the linear characteristic of the delay amount with respect to the control signal is good, and it is resistant to noise.
Further, according to the present invention, the selection circuit for configuring the variable delay circuit can be realized by one transistor, the circuit configuration can be simplified, the linear characteristic of the delay amount can be improved, and the delay amount can be controlled. It is possible to simplify the configuration of the delay control signal generation circuit. Further, in the oscillation circuit constituted by the delay circuit of the present invention, the oscillation frequency and the duty ratio can be adjusted with a fine step width, and an oscillation circuit capable of controlling both the oscillation frequency and the duty ratio can be realized.
Furthermore, according to the present invention, there is an advantage that power consumption can be reduced without increasing the circuit scale in the delay element.

First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a delay circuit according to the present invention.
As shown in the figure, the delay circuit of this embodiment is composed of n stages of delay elements DLY1, DLY2,..., DLYn. These delay elements are connected in series. That is, the input terminal IN of each delay element is connected to the output terminal OUT of the preceding delay element. An input terminal IN of the first-stage delay element DLY1 is connected to an input terminal of the signal _{S IN.} Further, the delay elements DLY1, DLY2, ..., the input terminal PR of the precharge signal and its inverted signal to DLYn, and XPR is provided, the input terminal of the input terminals PR are signal _{S IN} of the precharge signal of each delay element The input terminal XPR of the inverted signal of the precharge signal is connected to the input terminal of the inverted signal S _XIN of the signal S _IN .

An example of the delay element constituting the delay circuit is shown in FIG. The delay element includes pMOS transistors P1 and P2 and nMOS transistors N1 and N2.
The gate of the pMOS transistor P1 is connected to the input terminal IN of the delay element, the source is connected to the supply line of the power supply voltage VDD, and the drain is connected to the node A. The gate of the nMOS transistor N1 is connected to the precharge signal input terminal PR, the drain is connected to the node A, and the source is grounded.
The gate of the pMOS transistor P2 is connected to the input terminal XPR for the inverted signal of the precharge signal, the source is connected to the supply line of the power supply voltage VDD, and the drain is connected to the output terminal OUT of the delay element. The gate of the nMOS transistor N2 is connected to the node A, the drain is connected to the output terminal OUT, and the source is grounded.

  In FIG. 2, the size of the symbol of the transistor indicates the driving capability of the transistor. That is, the driving capability of the nMOS transistor N1 is set larger than the driving capability of the pMOS transistor P1, and the driving capability of the pMOS transistor P2 is set larger than the driving capability of the nMOS transistor N2.

  In the delay element shown in FIG. 2, a high level signal, for example, a power supply voltage VDD level, is applied to the input terminal IN, a high level signal is applied to the precharge signal input terminal PR, and a low signal is applied to the inverted signal input terminal XPR. When a level signal, for example, a ground potential GND level signal is applied, the nMOS transistor N1 and the pMOS transistor P2 are in a conductive state, the node A is held at the ground potential GND, and the output terminal OUT is at the level of the power supply voltage VDD. Retained. At this time, since both the pMOS transistor P1 and the nMOS transistor N2 are in a non-conductive state, the levels of the node A and the output terminal OUT are held by the charges even when the level of the precharge signal changes.

  When the precharge signal is at the low level and the input signal applied to the input terminal IN changes from the high level to the low level, the pMOS transistor P1 is switched from the non-conductive state to the conductive state, and the node A is at the low level. The level changes from high to low. In response to this, the nMOS transistor N2 is switched from the non-conductive state to the conductive state, and the output terminal OUT of the delay element is switched from the high level to the low level.

FIG. 3 is a waveform diagram showing the operation of the delay circuit shown in FIG. 1. The input signal S _IN and its inverted signal S _XIN , the input / output terminals of the delay elements DLY1, DLY2,. The waveform is shown.
In the initial state, the input signal S _IN is held at a high level, for example, the power supply voltage VDD, and the inverted signal S _XIN is held at a low level, for example, the ground potential GND. In each delay element DLY1, DLY2,..., DLYn, the node A is held at a low level, and the output signals OUT1, OUT2, ..., OUTn are held at the power supply voltage VDD level.

At time t ₀ , the input signal S _IN switches from the high level to the low level, and at the same time, the inverted signal S _XIN switches from the low level to the high level. In the delay element DLY1, when the level of the input signal _SIN decreases and exceeds the threshold voltage V _thp of the pMOS transistor P1, the pMOS transistor P1 becomes conductive and the potential of the node A increases. When the potential of the node A exceeds the threshold voltage V _thn of the nMOS transistor N2, the nMOS transistor N2 becomes conductive, and the output signal OUT1 of the delay element DLY1 switches from high level to low level. That is, through the falling fixed delay element time from the edge of the input signal S _IN, and the output signal OUT1 of the delay element DLY1 is switched from the high level to the low level.

The delay elements DLY2, DLY3,..., DLYn connected in the subsequent stage of the delay element DLY1 perform the same operation as the delay element DLY1 described above, and each delay element is constant with respect to the falling edge of the input signal. A delay signal giving the delay time of 1 is output to the output terminal.
Here, if each delay element similarly gives a delay time t _D to the input signal, the output signals of the delay elements DLY1, DLY2,..., DLYn are t _D , 2t _D ,. A delay time of nt _D is given. The delay element of n stages with respect to the input signal _{S IN} is given a delay time of up to nt _D.

At time _{t 1,} the input signal _{S IN} is switched from a low level to a high level. In response to this, in the delay element DLY1, the nMOS transistor N1 is switched from the non-conductive state to the conductive state, and the node A is switched from the high level to the low level. For this reason, the nMOS transistor N2 is switched from the conducting state to the non-conducting state, and the signal input to the inversion signal terminal of the precharge signal becomes the low level, so that the pMOS transistor P2 becomes the conducting state, and the delay element DLY1 The output signal OUT1 becomes high level.

Other delay elements DLY2, DLY3, ..., in DLYn, the input signal _{S IN} is high level, at the moment when the inverted signal _{S XIN} is switched to the low level, all of the transistors P1, P2, N1, N2 conductive state Thus, a through current flows through these transistors for a moment. However, as described above, the transistors are formed to have different sizes, and the driving capabilities of these transistors are also different accordingly. For example, the driving capability of the nMOS transistor N1 is larger than the driving capability of the pMOS transistor P1, and the pMOS transistor P2 is larger than the driving capability of the nMOS transistor N2. Therefore, the potential of the node A drops in each delay element DLY2, DLY3,..., DLYn without waiting for the sequential propagation of the state change of the first-stage delay element DLY1, and the potential of the output terminal rises. And this change in state become more weakening the driving ability of the pMOS transistor P1 and an nMOS transistor N2, so that all of the delay elements without waiting for sequential propagation of a change in the input signal _{S IN} of the first-stage delay element DLY1 DLY1, DLY2,..., DLYn change almost simultaneously, and the output signals OUT1, OUT2,.

The input signal _{S IN} is high level, when the inverted signal _{S XIN} is held at a low level, the delay elements DLY1, DLY2, ..., node A is a low level of DLYn, the output terminal is held at the high level state The The falls from the input signal _{S IN} is high level to a low level at time _{t 2,} the output signal OUT1, OUT2 of the delay elements, ..., OUTn changes from the high level to the low level through the respective delay times.

As described above, according to the present embodiment, a delay circuit is configured by connecting a plurality of delay elements in series, and each delay element includes the pMOS transistor P1, the nMOS transistor N1, the nMOS transistor N2, and the nMOS transistor N2. The pMOS transistor P2 has a larger driving capability, and an input signal is applied to the gate of the pMOS transistor P1, the gate of the nMOS transistor N1 is connected to the precharge signal terminal PR, and the gate of the pMOS transistor P2 is connected to the precharge signal. Connected to the inverted signal terminal XPR, the gate of the nMOS transistor N2 is connected to the intermediate node A composed of the drains of P1 and N1, and the input signal _SIN is input to each delay element as a precharge signal, which is held at a high level. When node A is low, output Terminal OUT is in the precharge state of the high level, the falling edge of the input signal S _IN sequentially propagated by the delay elements, the delay signal OUTn is obtained from the output terminal of the delay circuit, the step width with a simple circuit configuration A small delay time can be obtained.

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the delay circuit according to the present invention.
As shown in the figure, the delay circuit of the present embodiment is composed of n stages of delay elements DLY1A, DLY2A,..., DLYnA that are connected in series in substantially the same manner as the first embodiment shown in FIG. The input terminal IN of each delay element is connected to the output terminal OUT of the preceding delay element. The input terminal IN of the first-stage delay element DLY1A is connected to the input terminal of the inverted signal S _XIN of the signal S _IN . Further, the delay elements DLY1A, DLY2a, ..., the input terminal PR of the precharge signal and its inverted signal to DLYnA, and XPR is provided, the input terminal of the input terminals PR are signal _{S IN} of the precharge signal of each delay element The input terminal XPR of the inverted signal of the precharge signal is connected to the input terminal of the inverted signal S _XIN of the signal _SIN .

An example of a delay element constituting the delay circuit of FIG. 4 is shown in FIG. The delay element includes pMOS transistors P1 and P2 and nMOS transistors N1 and N2.
The gate of the pMOS transistor P2 is connected to the input terminal XPR of the inverted signal of the precharge signal, the source is connected to the power supply voltage VDD, and the drain is connected to the node A. The gate of the nMOS transistor N2 is connected to the input signal terminal IN, the drain is connected to the node A, and the source is grounded.
The gate of the pMOS transistor P1 is connected to the node A, the source is connected to the power supply voltage VDD, and the drain is connected to the output terminal OUT. The gate of the nMOS transistor N1 is connected to the input terminal PR for the precharge signal, the drain is connected to the output terminal OUT, and the source is grounded.

  The pMOS transistor P2 is set to have a higher driving capability than the nMOS transistor N2, and the nMOS transistor N1 is set to have a higher driving capability than the pMOS transistor P1.

  When a low level signal is input to the input signal terminal IN of the delay element, a high level signal is input to the input terminal PR of the precharge signal, and a low level signal is input to the inverted signal terminal XPR, the pMOS transistor P2 and the nMOS transistor Since N1 is held conductive and the nMOS transistor N2 and the pMOS transistor P1 are held nonconductive, the node A is precharged by the power supply voltage VDD and held at the high level, and the output terminal OUT is connected to the ground potential GND. Retained.

When the signal at the input terminal IN changes from low level to high level, the precharge signal changes from high level to low level, and its inverted signal changes from low level to high level, the nMOS transistor N2 is in a conductive state. Since the pMOS transistor P2 is switched to the non-conductive state, the node A is discharged and changes from the high level to the low level. The pMOS transistor P1 is switched from the non-conductive state to the conductive state in response to the potential change of the node A, and the nMOS transistor N1 is switched to the non-conductive state by the low-level precharge signal. It is charged by the voltage VDD and switched from the low level to the high level.
Such a change sequentially propagates from the delay element DLY1A to the subsequent stage, the falling edge of the input signal passes through a certain delay time, and the output signal OUTn of the last-stage delay element rises from the low level to the high level.

FIG. 6 is a waveform diagram showing the operation of the delay circuit shown in FIG. Hereinafter, the operation of the delay circuit of this embodiment will be described with reference to FIG.
As shown in FIG. 6, in the initial state the input signal S _IN is kept at a high level, the inverted signal S _XIN is held at a low level. In each delay DLY1A, DLY2A, ..., DLYnA, the node A is precharged to the power supply voltage VDD level, and the output signals OUT1, OUT2, ..., OUTn are held at the low level.

At time t ₀ , the input signal S _IN switches from the high level to the low level, and at the same time, the inverted signal S _XIN switches from the low level to the high level. In the delay element DLY1A, the nMOS transistor N2 is switched from the non-conductive state to the conductive state, and the node A is discharged and switched to the low level. In response to this, the pMOS transistor P1 is switched from the non-conductive state to the conductive state, the output terminal is charged by the power supply voltage VDD, and is switched from the low level to the high level. That is, the falling edge of the input signal _{S IN,} and that is, via its inverted signal _{S XIN} predetermined delay time from the rising edge of the output signal OUT1 of the delay element DLY1A rises from the low level to the high level. Similarly, in each delay element DLY2A, DLY3A,..., DLYnA in the subsequent stage of the delay element DLY1A, a delay signal is output by giving a predetermined delay time to the signal input to the input terminal IN.
Here, assuming that each delay element similarly gives a delay time t _D to the input signal, the output signals of the delay elements DLY1A, DLY2A,..., DLYnA are t _D , 2t _D ,. A delay time of nt _D is given. The delay element of n stages with respect to the input signal _{S IN} is given a delay time of up to nt _D.

At time t _1, switches from the input signal S _IN is low level to a high level, the inverted signal S _XIN switches from the high level to the low level. In response to this, in the delay element DLY1A, the node A changes from the low level to the high level, and the output terminal OUT changes from the high level to the low level.

Other delay elements DLY2A, DLY3A, ..., in DLYnA, the input signal _{S IN} is high level, at the moment when the inverted signal _{S XIN} is switched to the low level, all of the transistors P1, P2, N1, N2 conductive state Thus, a through current flows through these transistors for a moment. However, as described above, the transistors are formed to have different sizes and have different driving capabilities. Therefore, in each delay element DLY2A, DLY3A,..., DLYnA without waiting for the sequential propagation of the state change of the first-stage delay element DLY1A. The potential at node A rises and the potential at the output terminal falls. This potential change further weakens the driving capability of the nMOS transistor N1 and the pMOS transistor P1, and as a result, all delay elements DLY1A, DLY2A,. As a result, the output signals OUT1, OUT2,..., OUTn are switched to the low level almost simultaneously.

At time t ₂ , the input signal _SIN changes from the high level to the low level, and the output signals OUT 1, OUT 2,. Change to level.

FIG. 7 shows a waveform when the state of the delay element shown in FIG. 5 changes. This figure shows the level change of the node A and the output terminal OUT when the input signal of the delay element changes from low level to high level. Here, the precharge signal input terminal PR of the delay element is held at a low level, and the input terminal XPR of the inverted signal is held at a high level. In the waveform diagram of FIG. 7, the node A is precharged by the power supply voltage VDD and held at a high level, and the output terminal OUT is held at a low level. The operation is shown.
As illustrated, when the input terminal IN is held at a low level, the node A is held at a high level and the output terminal OUT is held at a low level. When the level of the signal applied to the input terminal IN rises and exceeds the threshold voltage _Vthn of the illustrated nMOS transistor N1, the potential of the node A changes from high level to low level. When the potential of the node A becomes lower than the threshold voltage V _thp of the pMOS transistor P1, the pMOS transistor P1 becomes conductive, the potential of the output terminal OUT rises, and finally reaches the power supply voltage VDD level.

The delay time t _D of the delay element operating in this way is as shown in FIG. Compared to the operation waveform of the delay element in which the conventional inverter shown in FIG. 37 is configured in two stages in series, it can be seen that the delay time of the delay element of this embodiment is short.
In the delay element of this embodiment, only the gate of one transistor of the delay element in the subsequent stage is connected to the output terminal in the previous stage, and the load capacitance of the output terminal of each delay element is small. In the conventional delay element, the gates of the two transistors of the subsequent delay element are connected to the output terminal of the previous stage, and the load capacity of the delay element is large. Further, in the normal inverter, the output signal level changes when the input signal voltage reaches almost half the level of the power supply voltage VDD. However, in the delay element of this embodiment, the output is _performed with the threshold voltages V _thp and V _thn of the transistor. The pin level changes. For these reasons, the delay time of the delay element of this embodiment is smaller than the delay time of the delay element constituted by the conventional inverter, and the delay time can be finely adjusted accordingly.

As described above, according to the present embodiment, a plurality of delay elements are connected in series to form a delay circuit, and each delay element is composed of a pMOS transistor P1, an nMOS transistor N1, an nMOS transistor N2 having a higher driving capability than the pMOS transistor P1. The pMOS transistor P2 has a higher driving capability, and an input signal is applied to the gate of the nMOS transistor N2. The gate of the pMOS transistor P2 is connected to the input terminal XPR of the inverted signal of the precharge signal, and the gate of the nMOS transistor N1. Is connected to the input terminal PR of the precharge signal, the gate of the pMOS transistor P1 is connected to the intermediate node A composed of the drains of P2 and N2, and each delay element is obtained by using the inverted signal S _XIN of the input signal as the inverted signal of the precharge signal. enter, the input signal S _iN to the high level When it is lifting, the node A is at a high level, and data output terminal OUT is in the low level, the falling edge of the input signal S _{IN, and} that is, the rising edge of the inverted signal S _XIN sequentially propagated by the delay elements, the delay Since the delay signal OUTn is obtained from the output terminal of the circuit, a delay circuit can be formed with a simple circuit configuration, and a delay time with a small delay step width can be obtained.

Third Embodiment FIG. 8 is a circuit diagram showing a third embodiment of the delay circuit according to the present invention.
In the present embodiment, a ladder-type variable delay circuit is constituted by the delay elements DLY1B, DLY2B,..., DLYnB and the selectors SEL1, SEL2,. Each of the delay elements DLY1B, DLY2B,..., DLYnB is composed of a delay element that has an amplifying function and does not invert the logical signal values of the input and output. Each of the selectors SEL1, SEL2,..., SELn selects one of the two signals input to the input terminals A, B according to the delay control signals S1, S2,.

As shown in FIG. 8, the delay elements DLY1B, DLY2B,..., DLYnB and the selectors SEL1, SEL2,. Input terminal A for the selector SEL1 is connected to the input terminal _{T IN} of the signal _{S IN,} the input terminal B is connected to the output terminal of delay element DLY1B. The input terminal of the delay element DLY1B is connected to the output terminal of the selector SEL2. Input terminal A of the selector SEL2 is connected to the input terminal _{T IN,} the input terminal B is connected to the output terminal of the selector SEL3.

Input terminal of the delay element DLY2B is connected to the input terminal _{T IN} together with the input terminal A of the selector SEL2. The input terminal A of the selector SEL3 is connected to the output terminal of the delay element DLY2B, and the input terminal B is connected to the output terminal of the delay element DLY3B. The input terminal of the delay element DLY3B is connected to the output terminal of the selector SEL4. The input terminal A of the selector SEL4 is connected to the output terminal of the delay element DLY2B, and the input terminal B is connected to the output terminal of the selector SEL5.
Similarly, the subsequent portions of the delay circuit are configured by connecting a delay element and a selector.

Here, each of the selectors SEL1, SEL2,..., SELn selects the signal at the input terminal A when the delay control signals S1, S2,. It is assumed that the signal at the terminal B is selected and output to the output terminal OUT. In such a delay circuit, the delay control signal S1, S2 is a digital signal, ..., the turning point of the input signal _{S IN} is determined according to the Sn, the delay time of the output signal _{S OUT} to the input signal _{S IN} Be controlled.

For example, the delay control signal S1~S4 is high level, when S5 is at the low level, the input signal _{S IN} is delayed by a delay element DLY2B, is input to the input terminal A of the selector SEL4. The selector SEL4 selects the output signal of the delay element DLY2B and inputs it to the delay element DLY3B. Further, it is output to the output terminal T _OUT as the output signal S _{OUT through} the paths of the selectors SEL3, SEL2, the delay element DLY1B, and the selector SEL1. The signals S6 to Sn after the delay control signal S6 do not affect the delay time of the delay circuit, and can be set to arbitrary values.
Thus, by setting the respective bits of the delay control signals S1, S2,..., Sn, the delay time of the delay circuit becomes the sum of the delay times of the delay elements DLY1B, DLY2B, DLY3B, DLY4B.

In accordance with the delay time required delay control signals S1, S2, ..., by setting the bits of Sn, the output terminal T _OUT delayed signal by a predetermined delay time is given from S _OUT is obtained. For example, if the delay time of the delay elements of the m-stage is required, among the delay control signal, to set the S1~Sm to high level, setting Sm + 1 to a low level, the output signal from the output terminal T _OUT of the delay circuit S _OUT is a delay signal delayed by a total delay time of m stages of delay elements with respect to the input signal _SIN .

  Compared with the conventional variable delay circuit shown in FIG. 32, the variable delay circuit of the present embodiment has a minimum delay time that is not affected by the number of delay stages, and a linear characteristic of the delay control signal and the delay time. For example, when the delay time is controlled by an n-input 1-output selector as in a conventional variable delay circuit, if the maximum delay stage number n is increased, the circuit configuration and the delay amount of the selector portion change, and the minimum delay time becomes large. In order to make the circuit in which the minimum delay time is not changed, the wiring length and the number of gate stages required for the selector differ between the initial delay selection path and the subsequent delay selection path as the maximum delay stage number n is increased. The linear characteristic of the delay time is deteriorated.

  According to the present embodiment, the delay elements DLY1B, DLY2B,..., DLYnB and the selectors SEL1, SEL2,. Since the delay time of the delay circuit is controlled by controlling and changing the signal propagation path, the number of delay stages can be easily increased and decreased by repeating the same circuit, and the maximum delay stage number n does not affect the minimum delay time. The linear characteristic of the delay time is kept uniform with respect to the delay control signal. Further, the input / output positions of signals on the chip are fixed, and the circuit can be easily designed and changed.

Fourth Embodiment FIG. 9 is a circuit diagram showing a fourth embodiment of the delay circuit according to the present invention.
In this embodiment, the delay elements DLY1a, DLY1b, DLY2a, DLY2b, ..., DLYna, DLYnb and the selectors SEL1, SEL2, ..., SELn constitute a ladder type variable delay circuit. Each of the delay elements DLY1a, DLY1b,..., DLYna, DLYnb is composed of, for example, a delay element that has an amplifying function and inverts the input and output logic signal values. Each of the selectors SEL1, SEL2,..., SELn selects one of the two signals input to the input terminals A, B according to the delay control signals S1, S2,.

As shown in FIG. 9, the delay elements DLY1a, DLY1b, DLY2a, DLY2b,..., DLYna, DLYnb, and selectors SEL1, SEL2,. Input terminal A of the selector SEL1 is connected to the input terminal _{T IN} of the signal _{S IN} together with the input terminal of the delay element DLY1a, the input terminal B is connected to the output terminal of the delay element DLY1b. The input terminal of the delay element DLY1b is connected to the output terminal of the selector SEL2. The input terminal A of the selector SEL2 is connected to the output terminal of the delay element DLY1a, and the input terminal B is connected to the output terminal of the delay element DLY2b.
The subsequent stages of the delay circuit have the same configuration, and a ladder-type delay circuit is configured by each delay element and selector.

Here, each of the selectors SEL1, SEL2,..., SELn selects the signal at the input terminal A when the delay control signals S1, S2,. It is assumed that the signal at the terminal B is selected and output to the output terminal OUT. In such a delay circuit, the delay control signal S1, S2 is a digital signal, ..., the turning point of the input signal _{S IN} is determined according to the Sn, the delay time of the output signal _{S OUT} to the input signal _{S IN} Be controlled.

For example, when a delay time corresponding to four stages of delay elements is required, by setting S1 and S2 of the delay control signals S1, S2,..., Sn to a high level and setting the signal S3 to a low level, the signal _{S iN} input terminal _{T iN} via delay element DLY1a, the DLY2a, folded by the selector SEL3, since it is outputted to the output terminal _{T OUT,} the delay time of the delay circuit delay element DLY1a, DLY2a, DLY2b, DLY1b It is the sum of the respective delay times.

  In general, when a delay time of 2 m stages of delay elements is required, the delay control signals S1 to Sm are set to a high level, and the delay control signal Sm + 1 is set to a low level, so that the delay circuit can set the desired delay time. The delay time is obtained.

  As described above, according to the present embodiment, the delay elements DLY1a, DLY1b, DLY2a, DLY2b,..., DLYna, DLYnb and the selectors SEL1, SEL2,. Since the selector is controlled by the control signals S1, S2,..., Sn, and the delay time of the delay circuit is controlled by changing the signal propagation path, the number of delay stages can be easily increased or decreased by repeating the same circuit, The maximum delay stage number n does not affect the minimum delay time, the linear characteristic of the delay time is kept uniform with respect to the delay control signal, and the input / output position of the non-delayed signal on the chip can be fixed.

Fifth Embodiment FIG. 10 is a circuit diagram showing a fifth embodiment of the delay circuit according to the present invention.
The delay circuit of this embodiment is composed of n stages of delay elements DLYW1, DLYW2,..., DLYWn. Each delay element DLYW1, DLYW2,..., DLYWn is provided with a precharge signal input terminal PR, its inverted signal input terminal XPR, signal input terminals IN1, IN2, and delay signal output terminals OUT1, OUT2.

Precharge signal input terminal PR of each delay element is connected to the input terminal T _IN of the delay circuit, the inverted signal input terminal XPR is connected to the output terminal of the inverter INV1. Input terminal of the inverter INV1 is connected to the input terminal T _IN of the delay circuit. The buffer BUF1, BUF2 amplifies the input signal S _IN and the inverted signal of the precharge signal is supplied to the farther arranged to have a delay element from the output terminal of the input terminal T _IN and the inverter INV1 and the inverted signal Keep the level constant.

The output terminal OUT1 of the delay element DLYW1 is connected to the input terminal IN1 of the delay element DLYW2, the input terminal IN2 of the delay element DLYW1 is connected to the output terminal OUT2 of the delay element DLYW2, and the output terminal OUT2 is connected to the output terminal T _OUT of the delay circuit. It is connected.
The output terminal OUT1 of the delay element DLYW2 is connected to the input terminal IN1 of the delay element DLYW3, and the input terminal IN2 is connected to the output terminal OUT2 of the delay element DLYW3.
The delay elements of the respective delay stages after the delay element DLYW3 are similarly connected. In the delay element DLYWn constituting the final stage, the output terminal OUT1 is connected to the input terminal IN2.

In this way, a delay circuit is configured by the delay elements DLYW1, DLYW2,..., DLYWn. The delay circuit has two upper and lower signal propagation paths, in which signals are propagated from left to right in the upper propagation path and signals are propagated from right to left in the lower propagation path. Delay control signals S1, S2, S3, S4,..., S2n-1, S2n are input to each delay element, and a signal turn-back point in the delay circuit is set according to the delay control signal, and a signal propagation path is set. The delay time of the output signal S _OUT with respect to the input signal S _IN is controlled.

  FIG. 11 shows a configuration example of the delay element. As shown in the figure, the delay element of this example is configured by arranging the delay elements of the first embodiment of the present invention shown in FIG. In the upper part, the signal input to the input terminal IN1 is given a predetermined delay time and output to the output terminal OUT1, and in the lower part, the signal input to the input terminal IN2 is given a predetermined delay time and output. Output to the terminal OUT2. An nMOS transistor N1 is connected between the upper input terminal and the lower output terminal OUT2, and a pMOS transistor P1 is connected between the upper intermediate node A and the lower intermediate node B.

The gate of the nMOS transistor N1 is connected to the output terminal of the inverter INVA, and the input terminal of the inverter INVA is connected to the input terminal of the delay control signal SA. The gate of the pMOS transistor P1 is connected to the input terminal of the delay control signal SB.
When the delay control signal SA is held at a high level, a low level signal is applied to the gate of the nMOS transistor N1, the nMOS transistor N1 is in a non-conductive state, and the signal input to the input terminal IN1 is the intermediate node A. Is transmitted to the output terminal OUT1 with a predetermined delay time.
On the other hand, when the delay control signal SA is held at a low level, a high level signal is applied to the gate of the nMOS transistor N1, and the nMOS transistor N1 is held in a conductive state, so that the signal input to the input terminal IN1 Is directly output to the output terminal OUT2 without passing through the delay element.

When the delay control signal SB is held at a high level, the pMOS transistor P1 is in a non-conductive state, the signal at the node A is output to the output terminal OUT1 in the upper circuit, and is input to the input terminal IN2 in the lower circuit. The output signal is output to the output terminal OUT2 via the intermediate node B.
On the other hand, when the delay control signal SB is held at the low level, the pMOS transistor P1 is held in the conducting state, the upper intermediate node A and the lower intermediate node B are conducted, and the signal of the upper intermediate node A is the lower stage. Is output to the lower output terminal OUT2.

In this way, by setting the levels of the delay control signals SA and SB input to the delay element, the signal propagation or folding operation in the delay element is controlled, and one delay element has both functions of signal delay and selection. Share. Hereinafter, the operation of the delay circuit of this embodiment will be described with reference to FIGS.
Before the delay circuit operates, the upper stage circuit and the lower stage circuit are precharged according to the precharge signal and its inverted signal, respectively. Each falling edge of the signal input to the input terminal is propagated to the output terminal after a predetermined delay time.
For example, in the delay element shown in FIG. 11, when both the delay control signals SA and SB are held at a high level, the signal input to the input terminal IN1 in the upper circuit is output to the output terminal OUT1 after a delay time. The The change in the signal level at the time of discharge is transmitted from the upper input terminal IN1 to the output terminal OUT1, and the change in the signal returns through the subsequent circuit as shown in FIG. 10 and is input to the lower input terminal IN2. In the lower circuit, the signal input to the input terminal IN2 is output to the output terminal OUT1 after a predetermined delay time.

When the delay control signal SA is held at the high level and SB is held at the low level, the upper intermediate node A and the lower intermediate node B are connected. In this case, the intermediate node A of the upper circuit switches from the low level to the high level according to the falling edge of the signal input to the upper input terminal IN1, and the intermediate node B of the lower circuit similarly changes accordingly. The level changes. In response to the level change of the intermediate node B, the lower output terminal OUT2 changes from the high level in the precharge state to the low level in the discharge state. In this case, the pMOS transistor P4 constituting the lower circuit, the pMOS transistor P5 constituting the upper circuit, the nMOS transistor N3 constituting the lower circuit, and the nMOS transistor N5 constituting the upper circuit are formed in the same size. In this case, the delay time of the delay signal output to the output terminal OUT2 is the same as the delay time for one delay element shown in FIG. The delay time of the delay element shown in FIG. 2 When t _D, in this case, the delay time of the delay signals with respect to input to the input terminal IN1 signal is outputted from the output terminal OUT2 is t _D.
Thereafter, the level change of the intermediate node A in the upper stage is output to the outside via the output terminal OUT1, and is input to the lower input terminal IN2 through the subsequent circuit as shown in FIG. However, at that time, the lower intermediate node B is already at the high level, and the level of the node B does not change.

  When the delay control signal SA is held at a low level, the upper input terminal IN1 and the lower output terminal OUT2 are connected, and the signal input to the input terminal IN1 is output to the output terminal OUT2 without delay.

That is, when the delay control signals SA and SB are both held at a high level, the upper and lower circuits operate as delay elements, respectively, and the delay time corresponding to one delay element shown in FIG. give.
When the delay control signal SA is held at the high level and SB is held at the low level, a delay time corresponding to one delay element is given to the signal input to the upper input terminal IN1, and the delay signal is output at the lower stage. Output to the terminal OUT2.
When the delay control signal SA is held at a low level, the signal input to the upper input terminal IN1 is output to the lower output terminal OUT2 without delay.

  In the delay circuit constructed by connecting such delay elements as shown in FIG. 10, the delay control signals S1, S2, S3, S4,..., S2n input to the delay elements DLYW1, DLYW2,. By controlling −1 and S2n, the delay time of the delay circuit can be controlled. In addition, in each delay element DLYW1, DLYW2,..., DLYWn, the signal selection part for controlling the signal propagation path is configured by one transistor, and the circuit configuration is simplified.

  As described above, according to the present embodiment, the delay elements arranged in two upper and lower stages constitute a delay circuit with n stages, and the signal in the delay circuit is determined according to the delay control signal input to each delay element. Since the propagation path is changed, the delay time of the delay circuit is controlled, and the signal selection circuit in each delay element can be configured by a single transistor, the functions of both the delay element and the selection circuit can be realized with a simple circuit configuration. The scale can be reduced, and the delay amount of the signal in the selection circuit can be reduced as compared with the selection circuit constituted by the logic circuit, and a delay circuit with excellent linear characteristics of the delay control signal and the delay time can be realized.

Sixth Embodiment FIG. 12 is a circuit diagram showing a sixth embodiment of the delay circuit according to the present invention.
This embodiment is a circuit for supplying delay control signals S1, S2,..., Sn to the variable delay circuits of the third, fourth and fifth embodiments described above.
As described above, the signal propagation path in the delay circuit changes according to the value of each bit of the delay control signal supplied to the variable delay circuit, and the delay time is controlled. Specifically, the signal turn-back point is first determined by the low-level bits in the order of the delay control signals S1, S2,..., Sn, and the delay time is set accordingly.

In actual applications, the delay control signals S1, S2,..., Sn are often generated according to the up / down signal _SUD instructing increase / decrease of the delay time. FIG. 12 shows an example of such a delay control signal generation circuit.
As shown in the figure, the generation circuit of this example receives the up / down signal S _UD and the clock signal CLK, and controls the delay control signals S1, S2, and S2 for controlling the delay time of the variable delay circuit according to the instruction of the up / down signal S _UD . ..., Sn is generated.

The delay control signal generation circuit includes latch circuits C1, C2,. Each latch circuit receives the up / down signal S _UD and the clock signal CLK, and further receives the inverted signal XQ of the output signal Q of the preceding latch circuit from the PXQ terminal and the inverted signal XQ of the succeeding latch circuit from the NXQ terminal. The next output is determined based on the result of performing the logical operation on the signal No., and the number of delay stages of the delay control signal is increased or decreased by one stage every cycle of the clock signal CLK. Further, the PXQ terminal of the first-stage latch circuit C1 is held at a low level, for example, the ground potential GND, and the terminal NXQ of the last-stage latch circuit Cn is held at a high level, for example, the power supply voltage VDD level.

FIG. 13 shows a configuration example of the latch circuit. As illustrated, the latch circuit includes an AND gate G1, a NOR gate G2, and a D flip-flop D1.
One input terminal of the AND gate G1 is connected to an input terminal UP of the up-down signal S _UD, the other input terminal is connected to the input terminal NXQ inverted output signal of the subsequent latch circuit, one input of the NOR gate G2 The terminal is connected to the input terminal PXQ of the inverted output signal of the preceding latch circuit, and the other input terminal is connected to the output terminal of the AND gate G1. The signal input terminal D of the D flip-flop is connected to the output terminal of the NOR gate G2, and the clock signal input terminal is connected to the input terminal CK of the clock signal CLK. One bit of the delay control signal is output from the output terminal Q of the D flip-flop, and its inverted signal is output from the output terminal XQ.

Here, when the delay time of the delay circuit is increased, the up / down signal _SUD is set to a low level by the external control circuit, and when the delay time is decreased, the up / down signal _SUD is set to a high level. Assume. In the delay control signal generation circuit shown in FIG. 12, only one latch circuit outputs a low level signal, and the other latch circuits output a high level signal.

For example, as an initial state, among the delay control signals S1, S2,..., Sn, S1 to Sx are at a high level, and Sx + 1 to Sn are at a low level. When the up / down signal _SUD is held at the low level by the external control circuit in order to increase the delay time, the output signal Q of the latch circuit Cx + 1 changes from the low level to the high level at the change timing of the clock signal CLK, for example, at the rising edge. Can be switched to. Accordingly, the signal propagation path in the variable delay circuit changes and the number of delay stages increases, so that the delay time increases by one delay element.
On the other hand, in the same initial state, when the up / down signal _SUD is held at a high level by the external control circuit in order to reduce the delay time, the output signal Q of the latch circuit Cx-1 at the rising edge of the clock signal CLK. Is switched from high level to low level. Accordingly, the number of delay stages in the variable delay circuit is reduced, so that the delay time is reduced by one delay element.

In the latch circuit shown in FIG. 13, when the up / down signal _SUD is held at the low level by the external control circuit, the input signal level to the D flip-flop D1 is determined according to the output signal of the latch circuit in the previous stage. For example, when a high-level delay control signal is output from the preceding latch circuit, a low-level signal is input from the PXQ terminal, the output terminal of the NOR gate G2 is held at a high level, and the rising edge of the clock signal CLK , The output terminal Q of the D flip-flop D1 is switched to the high level. As a result, the number of delay elements in the signal propagation path in the variable delay circuit increases and the delay time increases.

On the other hand, when the up / down signal _SUD is held at the high level by the external control circuit, the output signal level of the D flip-flop D1 is determined according to the output signal of the latch circuit at the subsequent stage. For example, when a low-level delay control signal is output from the latch circuit at the subsequent stage, a high-level signal is input from the terminal NXQ, and a high-level signal is output from the AND gate G1, so that the output of the NOR gate G2 The terminal is held at the low level, and the output terminal Q of the D flip-flop D1 is switched to the low level at the rising edge of the clock signal CLK. As a result, the number of delay element stages in the signal propagation path in the variable delay circuit is reduced, and the delay time is reduced.

  There are many latch circuits for generating the delay control signal described above, and only one example is shown in FIG. Here, for example, if “·” represents a logical product, “+” represents a logical sum, and INV (x) represents a logical inversion of the signal x, a signal y shown in the following equation is generated and supplied to the D flip-flop D1. Any logic circuit may be used.

[Equation 1]
y = INV ( _SUD · INV (Q of the next stage) + INV (Q of the previous stage)) (1)

FIG. 14 shows waveforms of delay control signals S1, S2,..., Sn output from the delay control signal generation circuit shown in FIG. 12 in response to the up / down signal _SUD and the clock signal CLK. As shown in the figure, among the delay control signals S1, S2,..., Sn, S1, S2, and S3 start from an initial state in which the level is high and S4 to Sn are in a low level. The clock signal CLK rises at time t _1, since this time the up-down signal S _UD is held at a high level, the delay control signal S3 is switched from the high level to the low level. Delay control signal S2 is switched from high level to low level at more time t _2. In response to this, the number of delay elements in the signal propagation path of the variable delay circuit shown in FIG. 12 is reduced by one, and the delay time is reduced by two delay elements.

At time t _3, the up-down signal S _UD is switched from the high level to the low level, the clock signal CLK rises at time t ₄ in response to this, the delay control signal S2 is switched from a low level to a high level. Further, the delay control signal S3 is switched from the low level to the high level in response to the rising edge of the clock signal CLK at time t _5. As a result, the number of delay elements in the signal propagation path of the variable delay circuit increases by one, and the delay time increases by two delay elements.

As described above, according to the present embodiment, the delay control signal generation circuit is configured using the latch circuits C1, C2,..., Cn configured by the logic circuit including the AND gate G1 and the NOR gate G2 and the D flip-flop D1. The logic circuit of each latch circuit operates in accordance with the output signal of the latch circuit in the preceding and following stages, the up / down signal S _UD that controls increase / decrease in delay time, and the clock signal CLK that controls the operation timing. _Since the delay time is controlled by controlling the output signal of each latch circuit according to the level of _UD and changing the propagation path of the signal in the variable delay circuit that receives this, setting the up / down signal _SUD Thus, a desired delay time can be obtained by the variable delay circuit.

Seventh Embodiment FIG. 15 is a circuit diagram showing a seventh embodiment of the delay circuit according to the present invention.
This embodiment is a delay control signal generating circuit for supplying delay control signals S1, S2,..., Sm to the variable delay circuit as in the sixth embodiment of the present invention described above, but is different from the sixth embodiment. In this embodiment, the delay control signals S1, S2,..., S2m-1 are obtained by using the latch circuits CS1, CS2,..., CSm composed of the SR latches SRLAT1, SRLAT2 and NAND gates G1, G2, G3, G4. , S2m.

FIG. 16 shows a configuration example of the latch circuit. As shown in the figure, the latch circuit of this example is composed of SR latches SRLAT1, SRLAT2 and NAND gates G1, G2, G3, G4, and control signals CLA, PRA, CLB, PRB for instructing increase / decrease in delay time from the outside and the previous stage The output signals QA and QB are set in response to the output signal of the latch circuit at the subsequent stage.
The control signals CLA, PRA, CLB, and PRB are supplied by an external control circuit. For example, when the number of delay elements is an even number in a variable delay circuit and the number of delay elements is increased from that, a pulse is given to the PRA. When the number of delay stages is an even number and the number of delay elements is reduced from that, a pulse is given to CLB. When the number of delay elements is an odd number and the number of delay elements is reduced from that, a pulse is given to PRB. In the case where the number of delay elements is decreased from the odd number stage, a pulse is given to CLA. The delay control signal generation circuit of this embodiment generates delay control signals S1, S2,..., S2m-1, S2m according to such control signals CLA, PRA, CLB, PRB, and the number of delay element stages in the variable delay circuit Increase or decrease.

  NAND gates G1, G2, G3, and G4 are NAND gates having inputs A1 and A2, respectively. The input terminal A1 of the NAND gate G1 is connected to the input terminal PQ of the latch circuit, and the input terminal PQ is the latch of the previous stage. It is connected to the output terminal QB of the circuit. The input terminal A2 of the NAND gate G1 is connected to the input terminal of the control signal PRA. The input terminal A1 of the NAND gate G2 is connected to the input terminal of the control signal CLA, and the input terminal A2 is connected to the output terminal XQ of the SR latch SRLAT2. The output terminals of the NAND gates G1 and G2 are connected to the input terminals XR and XS of the SR latch SRLAT1, respectively.

  The input terminal A1 of the NAND gate G3 is connected to the output terminal Q of the SR latch SRLAT1, and the input terminal A2 is connected to the input terminal of the control signal PRB. The input terminal A1 of the NAND gate G4 is connected to the input terminal of the control signal CLB, and the input terminal is connected to the input terminal NXQ of the latch circuit. The output terminals of the NAND gates G3 and G4 are connected to the input terminals XR and XS of the SR latch SRLAT2, respectively.

  The SR latches SRLAT1 and SRLAT2 have the same configuration, and FIG. 17 shows the configuration. As shown in the figure, the SR latch is composed of two NAND gates S1 and S2. One input terminal of the NAND gate S1 is connected to the XR terminal, and the other input terminal is connected to the output terminal of the NAND gate S2. One input terminal of S2 is connected to the XS terminal, and the other input terminal is connected to the output terminal of the NAND gate S1.

  In such an SR latch, the signals of the output terminals XQ and Q are set at the level change of the signals input to the input terminals XR and XS, here the falling edge. Here, when the high level signal is “1”, the low level signal is “0”, and the input signals XR and XS are “10” and “01”, the output signals XQ and Q are “01” and “01”, respectively. When set to “10” and the input signal is “11”, the output signal retains the previous state. When the input signal is “00”, the output signal is indefinite, which is a prohibited state.

  Since the SR latch circuit shown in FIG. 17 is composed of two NAND gates S1 and S2, the entire latch circuit shown in FIG. 16 is composed of eight NAND gates. Since one NAND gate can be composed of four MOS transistors, one latch circuit shown in FIG. 16 is composed of a total of 32 transistors.

  FIG. 18 is a waveform diagram showing the waveforms of a part of the control signals CLA, PRA, CLB, PRB and the delay time control signals S1, S2,..., S2m-1, S2m set accordingly. Hereinafter, the operation of the delay control signal generation circuit of this embodiment will be described with reference to FIGS. 15 and 18.

As shown in FIG. 18, in the initial state, S1 (not shown), S2, S3, S4, and S5 are held at a high level, and signals after S6 and S7 (not shown) are held at a low level. At time t _0, the control signal CLA pulse is applied to, since the delay control signal S5 in response thereto is switched from the high level to the low level, the signal propagation path is changed by the variable delay circuits controlled, delayed The delay time is reduced by one element.

Then, at time t _1, a pulse is given to the control signal CLB, the delay control signal S4 in accordance with this since is switched from the high level to the low level, the delay time of the variable delay circuit is further reduced delay-element stages. Similarly pulse is given to the control signal CLA at time t _2, since the delay control signal S3 in response thereto is switched from the high level to the low level, the signal propagation path is changed by the variable delay circuits controlled, The delay time is reduced by one delay element.

At time t ₃ , a pulse is given to the control signal PRA, and the delay control signal S 3 is switched from the low level to the high level accordingly, so that the signal propagation path changes in the variable delay circuit, and the delay time is delayed by one delay element. Will increase. Then a pulse is given to the control signal PRB at time t _4, the delay control signal S4 in accordance with this is switched from a low level to a high level, the signal propagation path is changed by the variable delay circuit, the delay element of one stage of the delay time Will increase. Further, at time _t5 , a pulse is given to the control signal PRA, and the delay control signal S5 is switched from the low level to the high level accordingly, so that the signal propagation path is changed in the variable delay circuit, and the delay time is delayed by one delay element. Will increase.

As described above, according to the present embodiment, the delay control signal generation circuit is configured using the latch circuits CS1, CS2,..., CSm including the SR latches SRLAT1 and SRLAT2 and the NAND gates G1, G2, G3, and G4. Each latch circuit receives the output signals of the preceding and following latch circuits and control signals CLA, PRA, CLB, PRB for controlling the increase / decrease of the delay time, and generates delay control signals S1, S2,..., S2m-1, S2m. In response to this, the delay time is controlled by changing the signal propagation path in the variable delay circuit. Therefore, the desired delay time is set by the variable delay circuit by setting the control signals CLA, PRA, CLB, and PRB. can get.
For example, in the method of generating the delay control signals S1 to Sn necessary for the variable delay circuit by the decoder including the logic gate from the output of the counter, an unnecessary glitch may occur when the count value is switched. According to the delay signal generation circuits of the sixth and seventh embodiments, there is no concern about the occurrence of glitches compared to such a method. Further, the delay signal generation circuit can be realized simply and by repeating the same circuit, and the delay time of the delay circuit can be controlled without using a counter or a large-scale decoder circuit.

Eighth Embodiment FIG. 19 is a circuit diagram showing an eighth embodiment of the delay circuit according to the present invention.
This embodiment shows another configuration example of the latch circuits CS1, CS2,..., CSm constituting the delay control signal generation circuit shown in FIG.
As shown in FIG. 19, the latch circuit of this embodiment is composed of pMOS transistors P1 to P8 and nMOS transistors N1 to N12, and can be composed of a total of 20 MOS transistors as a single stage latch circuit. Compared to the above, the number of MOS transistors for forming the latch circuit is greatly reduced.

The gates of the pMOS transistor P1 and the nMOS transistor N3 are both connected to the node ND2, and the gates of the nMOS transistor N1 and the pMOS transistor P2 are both connected to the input terminal of the control signal PRA. The gate of the nMOS transistor N2 is connected to the terminal PQ, and is connected to the output terminal QB of the preceding latch circuit.
The gates of pMOS transistor P3 and nMOS transistor N4 are both connected to node ND1, and the gates of nMOS transistor N5 and pMOS transistor P4 are both connected to the input terminal of control signal CLA. The gate of the nMOS transistor N6 is connected to the node ND4.

The sources of the pMOS transistors P1 and P3 are both connected to the supply line of the power supply voltage VDD, the drain of the pMOS transistor P1 is connected to the source of the pMOS transistor P2, and the drain of the pMOS transistor P2 is connected to the node ND1. The drains of the nMOS transistors N1 and N3 are commonly connected to the node ND1, the source of the nMOS transistor N1 is connected to the drain of the nMOS transistor N2, and the sources of the nMOS transistors N2 and N3 are grounded.
The drain of the pMOS transistor P3 is connected to the source of the pMOS transistor P4, and the drain of the pMOS transistor P4 is connected to the node ND2. The drains of the nMOS transistors N4 and N5 are commonly connected to the node ND2, the source of the nMOS transistor N5 is connected to the drain of the nMOS transistor N6, and the sources of the nMOS transistors N4 and N6 are grounded.

The pMOS transistors P5 to P8 and the nMOS transistors N7 to N12 are connected in substantially the same manner as described above.
The output terminal QA of the latch circuit is connected to the node ND2, and the output terminal XQA is connected to the node ND1. Further, the output terminal QB is connected to the node ND4, and the output terminal XQB is connected to the node ND3. Further, odd-numbered signals S1, S3,..., S2m-1 of the delay control signal are output from the output terminal QA of the latch circuit, and even-numbered signals S2, S4,. Is output.

The operation of the latch circuit configured as described above will be described from the initial state in which a high level signal is output from the output terminal QA and a low level signal is output from the output terminal QB. In this case, the output terminal XQA is held at a low level, and the output terminal XQB is held at a high level. That is, the node ND1 is held at a low level, the node ND2 is held at a high level, the node ND3 is held at a high level, and the node ND4 is held at a low level.
For example, as shown in the waveform diagram of FIG. 18, when a positive pulse is applied to the control signal CLA, the nMOS transistor N5 becomes conductive. At this time, since a high level signal is output from the output terminal XQB of the latch circuit, the nMOS transistor N6 is also turned on. In response to this, the node ND2 is switched from the high level to the low level, and accordingly, the pMOS transistors P1 and P2 are both turned on, and the node ND1 is switched from the low level to the high level.
That is, the output terminal QA of the latch circuit is switched from the high level to the low level. In the variable delay circuit controlled by the output signal of the latch circuit, the delay time is reduced by one delay element.

Next, when the same initial state as described above, that is, when a high level signal is output from the output terminal QA and a low level signal is output from the output terminal QB, a positive pulse signal is given to the control signal PRB. The operation in the case of failure will be described. At this time, the nMOS transistor N7 is switched from the non-conductive state to the conductive state, and the nMOS transistor N8 is also in the conductive state, so that the node ND3 is switched from the high level to the low level. In response to this, the pMOS transistor P7 is switched from the non-conductive state to the conductive state, and the pMOS transistor P8 is also in the conductive state, so that the node ND4 is switched from the low level to the high level.
That is, the output terminal QB of the latch circuit is switched from the low level to the high level. In the variable delay circuit controlled by the output signal of the latch circuit, the delay time increases by one delay element.

  As described above, according to the present embodiment, each latch circuit constituting the delay control signal generation circuit is composed of 20 MOS transistors, and compared with the above-described seventh embodiment of the present invention, The number of MOS transistors for configuring the circuit can be reduced, and the configuration of the entire delay control signal generation circuit can be simplified.

Ninth Embodiment FIG. 20 is a circuit diagram showing a ninth embodiment of the delay circuit according to the present invention.
This embodiment shows another circuit example of the latch circuit constituting the delay control signal generation circuit, similarly to the above-described eighth embodiment. However, this embodiment realizes a latch circuit that can further reduce the number of MOS transistors as compared with the eighth embodiment shown in FIG. 19 by adjusting the drive capability of the pMOS transistor and the nMOS transistor constituting the latch circuit. .

  As shown in FIG. 20, the driving capabilities of the pMOS transistors P1, P3, P5 and P7 are set sufficiently smaller than N1, N2, N5, N6, N7, N8, N11 and N12, and the pMOS transistors P2, P4, P6 and P8 are set. 19 is short-circuited, the pMOS transistors P2, P4, P6, and P8 in the latch circuit of FIG. 19 can be deleted, and the number of transistors constituting the latch circuit Is further reduced.

Tenth Embodiment FIG. 21 is a circuit diagram showing a first embodiment of an oscillation circuit according to the present invention.
As shown in the figure, the oscillation circuit of the present embodiment is realized by using the first embodiment of the delay circuit shown in FIG. Here, the same components of the circuit are denoted by the same reference numerals, and in the following description, the delay circuit portion including the delay elements DLY1, DLY2,..., DLYn is omitted.

The output signal CKn of the delay element DLYn at the last stage of the delay circuit is fed back to the input terminal of the delay circuit via the NAND gate NGT1, thereby forming a ring oscillation circuit (ring oscillator). One input terminal of NAND gate NGT1 are connected to the output terminal OUT of delay elements DLYn, the other input terminal is connected to an input terminal of a control signal S _ON to control the operation / stop state of the oscillation circuit.
When the control signal _{S ON} is held at a low level, the output terminal of the NAND gate NGT1 is held at a high level, the delay elements DLY1, DLY2, ..., the output signal CK1 of DLYn, CK2, ..., all CKn High The oscillation circuit is set to a stopped state.
On the other hand, when the control signal _{S ON} is held at a high level, the inverted signal output of the output signal CKn of the delay element DLYn to the output terminal of NAND gate NGT1, which input terminal of the delay element DLY1 as an input signal of the delay circuit The oscillation circuit is set in an operating state by being input to IN, and clock signals CK1, CK2,..., CKn are output from the delay elements DLY1, DLY2,.

  FIG. 22 shows an output signal when the oscillation circuit shown in FIG. 21 operates. As shown in the figure, clock signals CK1, CK2,..., CKn having different duties are obtained from the delay elements DLY1, DLY2,.

  As described above, according to the present embodiment, a delay circuit is configured by a plurality of delay elements DLY1, DLY2,..., DLYn, and an output signal from the last-stage delay element DLYn is passed through the NAND gate NGT1. Since the inverted signal is input to the input terminal of the delay element DLY1 in the first stage to form a ring oscillator, a plurality of clock signals CK1, CK2,..., CKn having different duty ratios can be obtained simultaneously.

Eleventh Embodiment FIG. 23 is a circuit diagram showing a second embodiment of the oscillation circuit according to the present invention.
The oscillation circuit of this embodiment is configured using the delay circuit shown in FIG.
As shown in the figure, the oscillation circuit of this example is composed of a variable delay circuit including a NAND gate NGT1, delay elements DLY1, DLY2,..., DLYn and selectors SEL1, SEL2,. The delay time of the delay circuit is controlled in accordance with the delay control signals S1, S2,..., Sn input to the selectors SEL1, SEL2,.

The output signal _{S OUT} of the selector SEL1 constituting a delay circuit is input to one input terminal of NAND gate NGT1, the output signal _{S IN} of the NAND gate NGT1 is input to the delay circuit as the input signal of the delay circuit. The other input terminal of the NAND gate NGT1 is connected to the input terminal of the control signal S _ON to control the operation / stop state of the oscillation circuit.
When the control signal S _ON is held at a low level, when the output terminal of the NAND gate NGT1 is held at a high level, the oscillation operation is set to the stop state, the control signal S _ON is held at a high level, Since the inverted signal S _IN of the output signal S _OUT of the delay circuit is output from the output terminal of the NAND gate NGT1, and the inverted signal S _IN is further input to the delay circuit, an oscillation operation is performed in the annular oscillation circuit.

  The delay time of the delay circuit is controlled by the delay control signals S1, S2,..., Sn input to the selectors SEL1, SEL2, ..., SELn, and the oscillation frequency of the oscillation circuit is controlled accordingly. That is, an oscillation circuit having a variable frequency can be configured by the variable delay circuit. For example, when the delay time is set to be small by the delay control signals S1, S2,..., Sn, the oscillation frequency becomes large, and conversely, when the delay time is set to be large, the oscillation frequency becomes small.

  As described above, according to the present embodiment, the variable delay circuit constituted by the delay elements DLY1, DLY2, ..., DLYn and the selectors SEL1, SEL2, ..., SELn and the NAND gate NGT1 constitute the annular oscillation circuit, Since the oscillation frequency is controlled by controlling the delay time of the delay circuit by the delay time control signals S1, S2,..., Sn input to the selectors SEL1, SEL2,. A circuit can be realized, and the number of delay stages can be easily increased and decreased by repeating the same circuit, and the position of the output terminal of the signal on the circuit layout does not change when the number of delay elements is increased. In addition, since the maximum delay stage number n does not affect the minimum delay time and the linear characteristic of the delay time with respect to the delay control signal is kept uniform, the linear characteristic of the oscillation frequency with respect to the delay control signal is good, and the maximum oscillation frequency Can be set larger.

Twelfth Embodiment FIG. 24 is a circuit diagram showing a third embodiment of the oscillation circuit according to the present invention.
The oscillation circuit of this embodiment is configured using the delay circuit shown in FIG.
As shown in the figure, the oscillation circuit of this example is constituted by a variable delay circuit including a NAND gate NGT1, delay elements DLY1a, DLY1b, DLY2a, DLY2b,..., DLYna, DLYnb and selectors SEL1, SEL2,. The delay time of the delay circuit is controlled in accordance with the delay control signals S1, S2,..., Sn input to the selectors SEL1, SEL2,.

  Except for the difference in the components of the delay circuit, this embodiment has a configuration substantially similar to that of the second embodiment of the oscillation circuit shown in FIG. The effect is almost the same as that of the oscillation circuit.

Thirteenth Embodiment FIG. 25 is a circuit diagram showing a fourth embodiment of the oscillation circuit according to the present invention.
The oscillation circuit of the present embodiment is configured using the delay circuit shown in FIG.
As shown in the figure, the oscillation circuit of this example is composed of a variable delay circuit including a NAND gate NGT1 and delay elements DLYW1, DLYW2,..., DLYWn. The configuration of the delay elements DLYW1, DLYW2,..., DLYWn is shown in FIG. 11, and the configuration and operation of the variable delay circuit constituted by these delay elements have already been described in detail in the fifth embodiment of the delay circuit. Therefore, the description of the delay circuit portion is omitted here.

The output signal _{S OUT} of the delay circuit is input to one input terminal of NAND gate NGT1, is connected to an input terminal of the control signal _{S ON} to control the other operating / stop state of the oscillator circuit to the input terminal of the NAND gate NGT1 Yes. The output signal S _OUT of the NAND gate NGT1 is input to the delay circuit as an input signal of the delay circuit.

  Each of the delay elements DLYW1, DLYW2,..., DLYWn has both a delay function and a selection function, and the delay control signals S1, S2, S3, S4,. Accordingly, since the delay time of the delay circuit is controlled, the oscillation frequency of the oscillation circuit is controlled accordingly.

  As described above, according to the present embodiment, the annular oscillation circuit is configured by the variable delay circuit including the NAND gate NGT1 and the delay elements DLYW1, DLYW2,..., DLYWn, and the delay control signals S1, S2, S3, S4. ,..., S2n-1 and S2n control the delay time of the delay circuit to control the oscillation frequency of the oscillation circuit, so that the oscillation frequency can be controlled according to the digital signal and the delay element has a simple configuration Thus, both delay and selection functions are provided, and the degree to which the minimum frequency step width becomes larger due to the delay time of the selector is reduced. Further, there is an advantage that the number of transistors and the area for configuring the circuit can be reduced.

14th Embodiment FIG. 26 is a circuit diagram showing a fifth embodiment of an oscillation circuit according to the present invention.
The oscillation circuit of this embodiment is configured by connecting two delay circuits shown in FIG. 10 in cascade. By taking out the output of the oscillation signal CK from the middle point of the two delay circuits and independently controlling the delay time of the two output circuits, the oscillation signal CK having both the oscillation frequency and the duty ratio variable is obtained.

As shown, the delay elements ADLYW1, ADLYW2, ..., ADLYWn and delay elements DBLYW1, BDLYW2, ..., by BDLYWn, the two delay circuits 10 and 20 respectively configured, the delayed output signal _{SA OUT} of the delay circuit 10 is the circuit 20 Are input to the delay circuit 20. The output signal _{SB OUT} of the delay circuit 20 is input to one input terminal of NAND gate NGT1, control signal _{S ON} to control the other operating / stop state of the oscillator circuit to the input terminal of the NAND gate NGT1 is input.

Output signal _{S IN} of the NAND gate NGT1 as the precharge signal of the delay elements of the delay circuits 10 and 20, is input to a precharge signal input terminal PR of each delay element. The output signal _{S IN} of the NAND gate NGT1 is inverted through the inverter AINV1, as an inverted signal of the precharge signal is input to the terminal XPR of the delay elements of the delay circuit 10. Output signal _{S IN} is inverted by the inverter BINV1, input to the terminal XPR of the delay elements of the delay circuit 20.

  The delay control signals AS1, AS2, AS3, AS4, AS4, AS2n-1, AS2n are input to the delay elements ADLYW1, ADLYW2,..., ADLYWn of the delay circuit 10, and the delay time of the delay circuit 10 is determined according to these signals. Be controlled. The delay control signals BS1, BS2, BS3, BS4,..., BS2n-1, BS2n are input to the delay elements BDLYW1, BDLYW2,. Be controlled. The delay times of the delay circuits 10 and 20 are controlled in accordance with a delay control signal input to each delay circuit.

When the control signal _{S ON} the low level to the NAND gate NGT1 is inputted, the output signal _{S IN} of the NAND gate NGT1 is held at a high level, the output terminal OUT1, OUT2 of the delay elements constituting the delay circuit is at the high level The oscillation circuit is set to a stopped state.
When the control signal _{S ON} goes high, a short time delay elements ADLYW1, ADLYW2, ..., ADLYWn and BDLYW1, BDLYW2, ..., an output terminal OUT1, OUT2 of BDLYWn is precharged, the output from the output terminal OUT2 of BDLYW1 A signal is input to the NAND gate NGT1. When the input signal _{S ON} is at a high level, the change is propagated to the output terminal of the NAND gate NGT1, the output signal _{S IN} of the NAND gate NGT1 becomes low level. Further, the change propagates sequentially from the input terminal IN1 of ADLY1 to the output terminal and then from the input terminal IN1 of ADLYW2 to the output terminal OUT1. Here, when bypassed by the delay path set by the delay control signals AS1, AS2, AS3, AS4,..., AS2n-1, AS2n, this time, in the reverse direction, the output terminal OUT2 via the input terminal IN2 of the delay element ADLYW1 And is output as the output signal SA _OUT of the delay circuit 10. In each delay element BDLYW1, BDLYW2,..., BDLYWn of the delay circuit 20, the signal propagates in the same manner as before, and is set by the delay control signals BS1, BS2, BS3, BS4,..., BS2n-1, BS2n. after the signal is delayed in the signal path, and reaches the output terminal OUT2 of the delay elements BDLYW1, since the input to the NAND gate NGT1 as the output signal _{SB OUT} of the delay circuit 20, the high level output of the NAND gate NGT1 from low level The delay elements constituting the delay circuits 10 and 20 are again in the precharge state.

Ring oscillation is performed by signal propagation as described above. The output signal SA _OUT of the delay circuit 10 is output to the outside as the oscillation signal CK. Therefore, the oscillation frequency of the oscillation circuit is determined by the sum of the delay amounts before and after the oscillation signal CK, that is, the sum of the delay times of the delay circuits 10 and 20.
Further, the delay amount from the high level to the low level before and after the output terminal of the oscillation signal CK is the delay control signals AS1, AS2, AS3, AS4,..., AS2n-1, AS2n and BS1, BS2, BS3, BS4,. Since it can be controlled independently by BS2n-1 and BS2n, the duty ratio of the oscillation signal CK can be controlled.

As described above, according to the present embodiment, the delay circuits ADLYW1, ADLYW2,..., ADLYWn and BDLYW1, BDLYW2,. the output signal _{SB OUT} of the circuit 20 to the NAND gate NGT1, also input to the delay circuit 10 the output signal _{S iN} of the NAND gate NGT1, the midpoint of the delay circuits 10 and 20, that is, the output from the output terminal of the delay circuit 10 Since the signal SA _OUT is extracted and output as the oscillation signal CK, the frequency and duty ratio of the oscillation signal CK can be controlled by setting the delay control signals input to the delay circuits 10 and 20 independently. It becomes.

  Further, when an actual circuit is laid out on an LSI, it can be realized by adding a delay element on the right side in each of the delay circuits 10 and 20 when lowering the minimum oscillation frequency, and at that time, a change is made on the left side of the circuit. Therefore, when the minimum oscillation frequency is lowered, that is, when the oscillation frequency variable range is widened, problems such as a decrease in the maximum oscillation frequency and a decrease in the linear characteristic of the oscillation frequency relative to the control signal can be avoided. Reduction of the step width and increase of the variable range can be realized.

Fifteenth Embodiment FIGS. 27 and 28 are circuit diagrams showing other configuration examples of the delay elements constituting the delay circuit and the oscillation circuit according to the present invention.
FIG. 27 shows an example of a delay element constituted by a domino inverter. The delay element of this example is composed of pMOS transistors P1, P2, P3 and nMOS transistors N1, N2, N3.

  The source of the pMOS transistor P1 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the source of the pMOS transistor P2. The source of the pMOS transistor P2 is connected to the drain of the pMOS transistor P1, and the drain is connected to the node A. The drain of the nMOS transistor N1 is connected to the node A, and the source is grounded. The gates of the pMOS transistor P1 and the nMOS transistor N1 are commonly connected to the precharge signal input terminal PR, and the gate of the pMOS transistor P2 is connected to the input terminal IN of the delay element.

  The source of the pMOS transistor P3 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the output terminal OUT of the delay element. The drain of the nMOS transistor N2 is connected to the output terminal OUT, and the source is connected to the drain of the nMOS transistor N3. The drain of the nMOS transistor N3 is connected to the source of the nMOS transistor N2, and the drain is grounded. The gates of the pMOS transistor P3 and the nMOS transistor N3 are connected to the input terminal XPR of the inverted signal of the precharge signal, and the gate of the nMOS transistor N2 is connected to the node A.

  In this delay element, when a high level signal is input to the precharge signal terminal PR and a low level signal is input to the inverted signal terminal XPR, the nMOS transistor N1 and the pMOS transistor P3 are held in the conductive state, and the node A is at the low level. For example, the output terminal OUT is held at a high level, for example, the power supply voltage VDD level, for example, at the ground potential GND, that is, the delay element is set to the precharge state.

  After precharging, a low level signal is input to the terminal PR, and a high level signal is input to the terminal XPR. In response, nMOS transistor N1 and pMOS transistor P3 are held in the non-conductive state, and the precharged state of the delay element is held. When the precharge state is held while the signal input to the input terminal IN is at the high level and the input signal is switched from the high level to the low level, the pMOS transistor P2 and the nMOS transistor N3 become conductive, and the node A Charged by the power supply voltage VDD and switched to the high level. In response to this, the nMOS transistor N2 is also turned on, and the output terminal OUT is discharged and switched to the low level. The time from the falling edge of the input signal to the falling edge of the output signal is the delay time of the delay element.

  As described above, the delay element of this example can obtain substantially the same effect as the delay element shown in FIG. 2, and the delay value and the circuit area slightly increase as the number of transistors constituting the delay element increases. Instead, the through current at the time of delay element precharging is reduced, and the power consumption of the circuit can be reduced.

By using the delay element of the present embodiment, when constituting a delay circuit shown in FIG. 1, for example, the precharge signal terminal PR of each delay element is connected to a terminal of the input signal S _IN, and the inverted signal of the precharge signal It is connected to the input terminal XPR inverted signal terminals of the input signal S _iN, and an input terminal iN of the first-stage delay element is connected to the terminal of the input signal S _iN, and an input terminal iN of the delay elements of the subsequent pre-stage of the delay elements Connected to the output terminal OUT.

When the input signal S _IN is held at a high level, the delay elements are set to the precharge state, and at the falling edge of the input signal S _IN, both conductive state pMOS transistors P1, P2 in the first-stage delay element The node A is charged by the power supply voltage VDD and is held at the high level. In response to this, the nMOS transistor N2 is held conductive, and the nMOS transistor N3 is also conductive, so that the output terminal OUT is discharged and switched to the low level. Depending on the level change of the first-stage output terminals, the next stage of each delay element is changed sequentially state, the falling edge of the input signal S _IN is transmitted to the output terminal OUT of the delay elements of the final stage through each delay element Is done.

  As described above, according to the present embodiment, a delay element is configured by a domino inverter including pMOS transistors P1, P2, and P3 and nMOS transistors N1, N2, and N3, and a through current is generated when the state of the delay element changes. Since it can be suppressed, a reduction in power consumption can be realized in the delay circuit and the oscillation circuit configured by the delay element of this embodiment.

  FIG. 28 shows another example of a delay element constituted by a domino inverter. The delay element of this example is composed of pMOS transistors P1, P2, P3 and nMOS transistors N1, N2, N3. However, the connection relationship of these transistors is different from that of the delay element example shown in FIG.

In the delay element of this example, when the precharge signal is at the low level, both the pnp transistor P1 and the nMOS transistor N3 are held in the conductive state, the node A is held at the high level, and the output terminal OUT is held at the low level. When the precharge signal is held at the high level and the input signal to the input terminal IN is switched from the low level to the high level, the nMOS transistors N1 and N2 are both held in the conductive state, the node A is discharged, and its potential Switches to low level. In response to this, the pMOS transistor P3 is switched to the conductive state, and the pMOS transistor P2 is also in the conductive state, so that the output terminal OUT is charged by the power supply voltage VDD and switched to the high level.
Thus, the rising edge of the signal input to the input terminal IN is delayed by the delay element.

Note that the delay circuit shown in FIG. 4 can be applied when the delay circuit is constituted by the delay elements shown in FIG. The precharge signal terminal PR of each delay element is connected to a terminal of the input signal S _{IN, and} an input terminal XPR of the inverted signal of the precharge is connected to the inverted signal S _XIN terminal of the input signal S _IN. The input terminal IN of the delay element at the first stage is connected to the terminal of the inverted signal S _XIN of the input signal S _IN , and the input terminal IN of each subsequent delay element is connected to the output terminal OUT of the delay element at the previous stage.

Sixteenth Embodiment FIGS. 29, 30, and 31 are circuit diagrams showing another configuration example of the delay elements constituting the delay circuit and the oscillation circuit according to the present invention.
For example, by configuring the delay circuit shown in FIG. 10 with the delay element of this embodiment, the delay time of the delay circuit is set by the delay control signals S1, S2, S3, S4,..., S2n-1, S2n, A variable delay circuit can be realized.

  FIG. 29 shows an example of a delay element configured using a domino inverter. The delay element of this example has substantially the same configuration as the delay element shown in FIG. However, the delay element of this example is configured using a domino inverter. As shown in the figure, this embodiment is constituted by two delay elements, and the upper delay element outputs the signal input to the input terminal IN1 to the output terminal OUT1 via the node A. The lower delay element outputs the signal input to the input terminal IN2 to the output terminal OUT2 via the node B.

  A switch element composed of an nMOS transistor N1 is connected between the upper input terminal IN1 and the lower output terminal OUT2. When a low-level control signal is input to the delay control signal input terminal SA, a high-level signal is applied to the gate of the nMOS transistor N1, the nMOS transistor N1 is held conductive, and the upper input terminal IN1 and the lower stage The output terminal OUT2 is connected, and the signal input to the input terminal IN1 is output to the lower output terminal OUT2 without being given a delay time.

  In addition, when a switching element composed of a pMOS transistor P1 is connected between the upper node A and the lower node B, and a low level control signal is input to the delay control signal input terminal SB, the pMOS transistor P1 becomes conductive. In this state, the upper node A and the lower node B are connected. At this time, when a high-level control signal is input to the delay control signal input terminal SA, the signal input to the upper input terminal IN1 is output to the lower output terminal OUT2 via the nodes A and B. . In this case, the signal output to the lower output terminal OUT2 is given a delay time corresponding to one delay element.

  Further, when a high level control signal is input to both of the delay control signal input terminals SA and SB, both the nMOS transistor N1 and the pMOS transistor P1 are held in a non-conductive state, and in this case, the upper input terminal IN1 is connected. The input signal is output to the upper output terminal OUT1 via the node A, further delayed by another delay element connected to the subsequent stage, and then input to the lower input terminal IN2. The input signal is output via the node B to the lower output terminal OUT2. That is, in this case, the input signal is delayed by the upper and lower delay elements, respectively.

  The delay element shown in FIG. 29 has both delay and selection functions, and signal selection can be realized by one transistor, and the circuit configuration is simplified by a variable delay circuit configured using a selector. Furthermore, the occurrence of a through current is suppressed when the state of the delay element changes, and the power consumption of the circuit can be reduced.

  FIG. 30 shows another configuration example of the delay element. The delay element of this example is an improvement of the delay element shown in FIG. 11, and an nMOS transistor N8 for inhibiting signal propagation is added.

  An nMOS transistor N8 is added between the nMOS transistor N5 and the ground potential GND with respect to the delay element shown in FIG. The drain of the nMOS transistor N8 is connected to the source of the nMOS transistor N5, and the source is grounded. The gate of the nMOS transistor N8 is connected to the delay control signal input terminal SA.

As described above, when a low level signal is input to the delay control signal input terminal SA, the nMOS transistor N1 is held in a conductive state, the upper input terminal IN1 and the lower output terminal OUT2 are connected, and the input terminal The input signal to IN1 is output as it is to the lower output terminal OUT2. At this time, since the added nMOS transistor N8 is held in a non-conducting state, the upper output terminal OUT1 is held at a high level, for example, the power supply voltage VDD level. As a result, the state of each delay element after the output terminal OUT1 in the upper stage does not change, and power consumption associated with charging and discharging is reduced.
When a high level signal is input to the delay control signal input terminal SA, the nMOS transistor N8 is held conductive, and the delay element of this example operates in the same manner as the delay element shown in FIG.

FIG. 31 shows another configuration example of the delay element. The delay element of this example is an improvement of the delay element shown in FIG. 29, and an nMOS transistor N8 for inhibiting signal propagation is added.
As shown in the figure, the delay element of this example has substantially the same configuration as the delay element shown in FIG. 29 except that an nMOS transistor N8 is added. When the nMOS transistor N8 is added, a low level signal is input to the delay control signal input terminal SA, the input signal is bypassed by the conductive nMOS transistor N1, and is directly output to the lower output terminal OUT2. The nMOS transistor N8 is held in a non-conductive state, and the upper output terminal OUT1 is held at a high level, for example, the power supply voltage VDD level. Accordingly, in each subsequent delay element connected to the output terminal OUT1 in the upper stage, there is no change in state, and power consumption can be reduced.

  When a high-level control signal is input to the delay control signal input terminal SA, the nMOS transistor N8 is held conductive, and the delay element of this example operates in the same manner as the delay element shown in FIG.

  As described above, according to the present embodiment, the delay element is added with the nMOS transistor N8 for prohibiting the change of state, and the on / off state of the nMOS transistor N8 is controlled according to the delay control signal. When the control signal input terminal SA is held at a high level, the nMOS transistor N8 is held in a non-conductive state, and the upper output terminal OUT1 changes according to an input signal to the upper input terminal IN1. When the delay control signal input terminal SA is held at the low level, the input signal to the upper input terminal IN1 is bypassed to the lower output terminal OUT2, and the nMOS transistor N8 is held in the non-conductive state. Although the output terminal OUT1 is precharged, it is held at a high level without being discharged, signal propagation to the subsequent stage is stopped, and unnecessary power consumption associated with a state change in the subsequent stage can be suppressed.

FIG. 3 is a circuit diagram showing a first embodiment of a delay circuit according to the present invention. FIG. 3 is a circuit diagram of a delay element according to the first embodiment. It is a wave form diagram of the delay circuit of a 1st Example. FIG. 6 is a circuit diagram showing a second embodiment of the delay circuit according to the present invention. It is a circuit diagram of the delay element of a 2nd Example. It is a wave form diagram of the delay circuit of a 2nd Example. It is a wave form diagram which shows the delay time of a delay element. FIG. 6 is a circuit diagram showing a third embodiment of the delay circuit according to the present invention. FIG. 6 is a circuit diagram showing a fourth embodiment of the delay circuit according to the present invention. FIG. 9 is a circuit diagram showing a fifth embodiment of the delay circuit according to the present invention. It is a circuit diagram of the delay element which comprises the delay circuit of a 5th Example. It is a circuit diagram of a delay control signal generation circuit. It is a circuit diagram of a delay signal generation element. It is a wave form diagram of a delay control signal generation circuit. It is another circuit example of a delay control signal generation circuit. FIG. 3 is a circuit diagram of a delay control signal generation element including a latch circuit and a NAND gate. It is a circuit diagram which shows the structure of a latch circuit. It is a wave form diagram of a delay control signal generation circuit. It is a circuit diagram which shows the other structural example of a delay signal generation element. It is a circuit diagram which shows the other structural example of a delay signal generation element. 1 is a circuit diagram showing a first embodiment of an oscillation circuit according to the present invention. It is a wave form diagram of an oscillation circuit. 1 is a circuit diagram showing a first embodiment of an oscillation circuit according to the present invention. FIG. 3 is a circuit diagram showing a second embodiment of the oscillation circuit according to the present invention. FIG. 6 is a circuit diagram showing a third embodiment of the oscillation circuit according to the present invention. FIG. 6 is a circuit diagram showing a fourth embodiment of the oscillation circuit according to the present invention. It is a circuit diagram which shows an example of the delay element which consists of a domino inverter. It is a circuit diagram which shows the other example of the delay element which consists of a domino inverter. It is a circuit diagram which shows an example of the delay element of the upper and lower stages which consists of a domino inverter. It is a circuit diagram which shows the example of improvement of the delay element of the upper and lower stages which consists of a domino inverter. It is another example of improvement of the delay element of the upper and lower stages which consists of a domino inverter. It is a circuit diagram of the conventional variable delay circuit. It is a circuit diagram of the conventional frequency variable oscillation circuit. FIG. 6 is a circuit diagram of a conventional variable frequency oscillation circuit including a DAC and a VCO. It is a circuit diagram of a conventional variable frequency oscillation circuit comprising a switch and a capacitive element. It is a circuit diagram of the conventional delay element which consists of an inverter. It is a wave form diagram which shows the delay time of the conventional delay element.

Explanation of symbols

DLY1, DLY2,..., DLYn, DLY1A, DLY2A,..., DLYnA, DLY1B, DLY2B,. , DLYW1, DLYW2, ..., DLYWn ... delay elements, C1, C2, ..., Cn, CS1, CS2, ..., CSn ... delay control signal generating elements, SRLAT1, SRLAT2 ... latch circuits, P1, P2, P3, P4, P5 , P6, P7 ... pMOS transistors, N1, N2, N3, N4, N5, N6, N7, N8 ... nMOS transistors, VDD ... power supply voltage, GND ... ground potential.

Claims (14)

A delay circuit in which a delay time is set according to a control signal,
A first delay element that delays an input signal of the first input terminal by a predetermined time and outputs the delayed signal to the first output terminal;
In accordance with the control signal, a second signal that delays one of the output signal of the first delay element and the input signal of the second input terminal by a predetermined time and outputs the delayed signal to the second output terminal. Having multiple stages of basic circuits consisting of delay elements,
The first output terminal of the basic circuit of each stage is connected to the first input terminal of the basic circuit of the next stage, and the second input terminal of the basic circuit of each stage is connected to the basic circuit of the next stage. Connected to the second output terminal ,
The basic circuit is
First inverting means for inverting an input signal to the first input terminal and outputting the inverted signal to the first node;
A second inversion means for inverting the signal of the first node and outputting the inverted signal to the first output terminal;
Third inverting means for inverting the input signal to the second input terminal and outputting the inverted signal to the second node;
A fourth inversion means for inverting the signal of the second node and outputting the inverted signal to the second output terminal;
A first switch connected between the first input terminal and the second output terminal, the on / off state of which is controlled in accordance with a first control signal;
A plurality of delay elements each including a second switch connected between the first and second nodes and including a second switch whose on / off state is controlled according to a second control signal;
The first output terminal of the delay element of each stage is connected to the first input terminal of the delay element of the next stage, and the second input terminal of the delay element of each stage is connected to the delay element of the next stage. A delay circuit configured to be connected to the second output terminal . The first inversion means has a first conductivity type insulated gate electric field in which a gate is connected to the first input terminal, a source is connected to a first power source, and a drain is connected to the first node. An effect transistor;
The gate is connected to the input terminal of the precharge control signal, the drain is connected to the first node, the source is connected to the second power supply, and the driving capability is larger than that of the first conductivity type insulated gate field effect transistor. the delay circuit of claim 1, wherein which is constituted by a second conductivity type insulated gate field effect transistor. The first inversion means includes a first first conductivity type insulated gate field effect transistor having a source connected to a first power source and a gate connected to an input terminal of a precharge control signal;
A second second source having a source connected to the drain of the first first conductivity type insulated gate field effect transistor, a drain connected to the first node, and a gate connected to the first input terminal. One conductivity type insulated gate field effect transistor;
And a second conductivity type insulated gate field effect transistor having a drain connected to the first node, a source connected to a second power source, and a gate connected to the input terminal of the precharge control signal. The delay circuit according to claim 1 . The second inverting means has a source connected to a first power supply, a drain connected to the first output terminal, and a gate connected to an input terminal of an inverted signal of the precharge control signal. Type insulated gate field effect transistor,
The drain is connected to the first output terminal, the source is connected to the second power source, the gate is connected to the first node, and the driving capability is smaller than that of the first conductivity type insulated gate field effect transistor. the delay circuit of claim 1, wherein which is constituted by a second conductivity type insulated gate field effect transistor. The second inverting means has a source connected to a first power supply, a drain connected to the first output terminal, and a gate connected to an input terminal of an inverted signal of the precharge control signal. Type insulated gate field effect transistor,
A first second conductivity type insulated gate field effect transistor having a drain connected to the first output terminal and a gate connected to the first node;
The drain is connected to the source of the first second conductivity type insulated gate field effect transistor, the source is connected to the second power supply, and the gate is connected to the input terminal of the inverted signal of the precharge control signal. the delay circuit of claim 1, wherein which is constituted by a second second conductivity type insulation gate type electric field effect transistor. The third inversion means includes a first conductivity type insulated gate electric field in which a gate is connected to the second input terminal, a source is connected to a first power source, and a drain is connected to the second node. An effect transistor;
The gate is connected to the input terminal of the precharge control signal, the drain is connected to the second node, the source is connected to the second power source, and the driving capability is larger than that of the first conductivity type insulated gate field effect transistor. the delay circuit of claim 1, wherein which is constituted by a second conductivity type insulated gate field effect transistor. The third inversion means includes a first first conductivity type insulated gate field effect transistor having a source connected to a first power source and a gate connected to an input terminal for a precharge control signal;
A second second source having a source connected to the drain of the first first conductivity type insulated gate field effect transistor, a drain connected to the second node, and a gate connected to the second input terminal. One conductivity type insulated gate field effect transistor;
And a second conductivity type insulated gate field effect transistor having a drain connected to the second node, a source connected to a second power source, and a gate connected to the input terminal of the precharge control signal. The delay circuit according to claim 1 . The fourth inversion means has a source connected to the first power source, a drain connected to the second output terminal, and a gate connected to an input terminal of the inverted signal of the precharge control signal. Type insulated gate field effect transistor,
The drain is connected to the second output terminal, the source is connected to the second power supply, the gate is connected to the second node, and the driving capability is smaller than that of the first conductivity type insulated gate field effect transistor. the delay circuit of claim 1, wherein which is constituted by a second conductivity type insulated gate field effect transistor. The fourth inversion means has a source connected to the first power source, a drain connected to the second output terminal, and a gate connected to an input terminal of the inverted signal of the precharge control signal. Type insulated gate field effect transistor,
A first second conductivity type insulated gate field effect transistor having a drain connected to the second output terminal and a gate connected to the second node;
The drain is connected to the source of the first second conductivity type insulated gate field effect transistor, the source is connected to the second power supply, and the gate is connected to the input terminal of the inverted signal of the precharge control signal. the delay circuit of claim 1, wherein which is constituted by a second second conductivity type insulation gate type electric field effect transistor. The precharge control signal delay circuit as claimed in any one of claims 2 9 which is the input signal input to the first delay element. The first switch, the gate of the first control signal is applied to, claim 1, the diffusion layer is respectively a transistor connected to said first input terminal and the second output terminal The delay circuit according to any one of 10 . Said second switch, said second control signal is applied to the gate, claim 1 to 11, the diffusion layer is respectively a transistor connected to said first and second nodes The delay circuit according to 1. Holding means connected to the second inverting means, receiving the first control signal, and holding the first output terminal at a predetermined level when the first switch is set in a conducting state. The delay circuit according to any one of claims 1 to 12 . A delay control signal generating circuit for receiving a control signal and outputting a delay control signal for controlling a delay time to a delay circuit configured by connecting a plurality of delay elements in series;
The delay control signal generating circuit receives a delayed control signal and the control signal input to the upstream and downstream of the delay element, claims 1 to set the level of the delay control signal output according to the signals 13 The delay circuit according to any one of the above.

Images