JP2009253829A - Oscillator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make an oscillator circuit oscillate faster with low power consumption. <P>SOLUTION: The oscillator circuit includes: inverter circuit pairs 110, 120, 130 for inverting one (the other) input end signal to output to one (the other) output end; and a NAND circuit/NOR circuit pair 140. The inverter circuit pair 110 connects one input end to the NOR circuit's output end, and the other input end to the NAND circuit's output end. The inverter circuit pair 120 (130) connects one input end to the inverter circuit pair 110 (120)'s one output end, and the other input end to the 110 (120) inverter circuit pair's other output end. The NAND circuit with two inputs connects one input end to the inverter circuit pair 130's one output end, and the other input end to the inverter circuit pair 120's other output end. Further, the NOR circuit with two inputs connects one input end to the inverter circuit pair 130's other output end, and the other input end to the inverter circuit pair 120's one output end. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an oscillation circuit, and more particularly to a technique for reducing the voltage and speed of the oscillation circuit.

  In recent years, along with demands for realizing high-speed interfaces such as CPUs and high-speed interfaces such as DDR with low voltage and low current consumption, high-speed operation with low voltage is also required for oscillation circuits. As such an oscillation circuit, a ring oscillator in which delay circuits are cascade-connected in a ring shape and a modified circuit thereof are widely known.

  FIG. 5 is a circuit diagram of a delay circuit constituting the oscillation circuit of Patent Document 1, and FIG. 6 is a circuit diagram of an oscillation circuit using the delay circuit. First, the configuration of FIG. 5 will be described.

  The delay circuit of FIG. 5 is a transistor that forms a differential pair with a first amplifier composed of transistors 25 and 26 and a second amplifier composed of transistors 28 and 30, and interconnects the outputs of the first and second amplifiers. 27, a fourth amplifier by a transistor 29, and a variable current source by transistors 31 and 32. Capacitance elements 33 and 34 indicate capacitances parasitic between the output terminal Vout1, the output terminal Vout2, and the input terminal of the next stage.

  Next, the operation of the delay circuit having such a configuration will be described. The first and second amplifiers are inverting amplifiers (inverter circuits), and output an inverted input. The third and fourth amplifiers are feedforward connected between the output terminal Vout1 and the output terminal Vout2 which are outputs of the differential pair, detect a minute potential difference generated between the differential pair outputs, and output the differential pair output. Forcibly operate on the power supply side or ground side. Even if Vin1 and Vin2 that are inputs of the differential pair are both at the ground level, a minute difference potential generated at the output of the differential pair due to device noise or the like is amplified so that the output of the differential pair becomes a reverse phase output. Works.

  Furthermore, the current of the variable current source can be varied by changing the voltages Vcontp and Vcontn. By changing the current of the variable current source, the delay from the input to the output in the delay circuit can be changed.

  Next, the configuration of the oscillation circuit will be described. 6 includes the delay circuits 18-d, 18-e, 18-f, and 18-g of FIG. 5 connected in cascade, and the output terminal Vout1 and the output terminal Vout2 of the final-stage delay circuit 18-g are respectively connected to the first-stage delays. The circuit 18-d is connected so as to cross the input terminals Vin2 and Vin1.

  Next, the operation of the oscillation circuit having such a configuration will be described. If Vin1 of the delay circuit 18-d is at a high level and Vin2 is at a low level, the output terminal Vout1 of the delay circuits 18-d, 18-e, 18-f and 18-g is at a high level, and the delay circuit 18-d , 18-e, 18-f, and 18-g output terminals Vout2 are at a low level. Since the output signal pair of the delay circuit 18-g is crossed and fed back to the input terminal of the delay circuit 18-d, Vin1 of the delay circuit 18-d changes from high level to low level, and the delay circuit 18-d. Vin2 of the signal transitions from a low level to a high level. Thereby, in the outputs of the delay circuits 18-d, 18-e, 18-f, and 18-g, the output terminal Vout1 sequentially transitions to the low level, and the output terminal Vout2 transitions to the high level. Further, Vin1 of the delay circuit 18-d transits from the low level to the high level by feedback, and Vin2 of the delay circuit 18-d transits from the high level to the low level. The oscillation operation is performed by repeating this.

  As described above, by changing the voltages of Vcontp and Vcontn, the delay of each delay circuit can be changed, and thus the oscillation frequency in the oscillation circuit can be changed.

  Relatedly, Patent Document 2 discloses an oscillation circuit that is entirely composed of an inverter circuit.

JP 2001-358565 A JP 2005-333645 A

  The following analysis is given in the present invention.

  The transistors 27 and 29 constituting the third and fourth amplifiers in FIG. 5 have gate capacities as load capacities of the output terminals Vout1 and Vout2, respectively. Further, the drains are connected to the output terminals Vout2 and Vout1, respectively, and the output terminal Vout1 and the output terminal Vout2 operate in opposite phases during the oscillation operation. In this case, the gate capacitance is multiplied by the gain by the Miller effect as a load capacitance and added to the output terminals Vout1 and Vout2.

  In the oscillation circuit of FIG. 6, both the output terminal Vout1 and the output terminal Vout2 of the delay circuit 18-d are low level, the output terminal Vout1 and the output terminal Vout2 of 18-e are both high level, and the output terminal Vout1 of the delay circuit 18-f. Both the output terminal Vout2 and the output terminal Vout2 of the delay circuit 18-g are at a low level, and the output terminal Vout2 and the output terminal Vout2 are both at a high level. In order to avoid this, the transistors 27 and 29 constituting the third and fourth amplifiers are arranged so that the output terminal Vout1 and the output terminal Vout2 are in reverse phase output even when both Vin1 and Vin2 are at a low level. The current capability when the gates of the transistors 27 and 29 are at a high level is approximately the same as that of the transistors 25 and 28, so that the current capability when the gates of the transistors 27 and 29 are at a high level. Is set to the dimension. Therefore, the gate capacitance of the transistors 27 and 29 cannot be ignored with respect to the gate capacitance of the next stage.

  In the oscillation circuit as described above, the load capacitances of the output terminals Vout1 and Vout2 are the gate capacitance of the transistors 27 and 29 in addition to the gate capacitance of the next stage, and the gate capacitance of the transistors 29 and 27 multiplied by the gain by the Miller effect. Therefore, there is a possibility that a sufficiently high-speed oscillation operation cannot be performed.

  An oscillation circuit according to one aspect (side surface) of the present invention inverts a signal at one input end and outputs the inverted signal to one output end, and inverts a signal at the other input end and outputs the inverted signal to the other output end. A first to N-th (N is an odd number of 3 or more) inverter circuit pair and a NAND circuit / NOR circuit pair, and the first inverter circuit pair has one input terminal connected to the output terminal of the NOR circuit The other input terminal is connected to the output terminal of the NAND circuit, and for K = 2 to N (where K is an integer), the Kth inverter circuit pair has one input terminal connected to the (K−1) th inverter. One output terminal of the circuit pair is connected, the other input terminal is connected to the other output terminal of the (K−1) th inverter circuit pair, the NAND circuit has two inputs, and one input terminal is connected to the Nth input terminal. Is connected to one output terminal of the inverter circuit pair, and the other input terminal is connected to the (N-1) th inverter. The NOR circuit has two inputs connected to the other output terminal of the circuit pair, one input terminal is connected to the other output terminal of the Nth inverter circuit pair, and the other input terminal is connected to the (N-1) th. Connected to one output terminal of the inverter circuit pair.

  An oscillation circuit according to another aspect (side surface) of the present invention includes an N (N is an integer of 2 or more) stage delay circuit, and for K = 2 to N (where K is an integer), The stage delay circuit has one input terminal connected to one output terminal of the (K-1) th stage delay circuit, and the other input terminal connected to the other output terminal of the (K-1) th stage delay circuit, When N is an odd number, the first stage delay circuit connects one input terminal to one output terminal of the Nth delay circuit and the other input terminal to the other output of the Nth delay circuit. When N is an even number, one input terminal is connected to the other output terminal of the Nth stage delay circuit, and the other input terminal is connected to one output terminal of the Nth stage delay circuit. The delay circuit at each stage can operate differentially, inverts the signal at one input terminal and outputs it to one output terminal, and inverts the signal at the other input terminal. A pair of inverter circuits that output to the other output terminal, a first inverter circuit that inverts the signal at one input terminal and outputs it to one output terminal, and a signal from the other input terminal that inverts the other output terminal A second inverter circuit that outputs to the first FET, a first FET that grounds the source and has a gate connected to one output terminal and a drain connected to the other output terminal, and a ground that connects the source and a gate connected to the other output terminal And a second FET having a drain connected to one of the output terminals, and includes at least one or more inverter circuit pairs and one or more differential circuits.

  According to the present invention, in an oscillation circuit in which delay circuits are cascade-connected, a circuit that oscillates at high speed with low power consumption can be realized by configuring at least one delay circuit as a pair of inverter circuits. .

  An oscillation circuit according to an embodiment of the present invention is a ring oscillator in which a plurality of stages of delay circuits including a delay circuit composed of an inverter circuit pair are connected in a ring shape.

  As the oscillation circuit of the first embodiment, the first to Nth signals that invert the signal at one input terminal and output it to one output terminal, and invert the signal at the other input terminal to output to the other output terminal. (N is an odd number of 3 or more) inverter circuit pairs and NAND circuit / NOR circuit pairs. In the first inverter circuit pair, one input terminal is connected to the output terminal of the NOR circuit, the other input terminal is connected to the output terminal of the NAND circuit, and K = 2 to N (where K is an integer) The Kth inverter circuit pair has one input terminal connected to one output terminal of the (K-1) th inverter circuit pair and the other input terminal connected to the other output terminal of the (K-1) th inverter circuit pair. Connecting. The NAND circuit has two inputs, one input terminal is connected to one output terminal of the Nth inverter circuit pair, and the other input terminal is connected to the other output terminal of the N-1th inverter circuit pair. To do. The NOR circuit has two inputs, one input terminal is connected to the other output terminal of the Nth inverter circuit pair, and the other input terminal is connected to one output terminal of the N-1th inverter circuit pair. To do.

  A variable current source for controlling the power supply current in at least one of the inverter circuit pair and the NAND circuit / NOR circuit pair may be provided.

  The oscillation circuit according to the second embodiment is composed of N (N is an integer of 2 or more) stage delay circuit, and for K = 2 to N (where K is an integer), the K-th stage delay circuit is One input terminal is connected to one output terminal of the (K-1) th stage delay circuit, the other input terminal is connected to the other output terminal of the (K-1) th stage delay circuit, and the first stage delay circuit is connected. When N is an odd number, the circuit connects one input terminal to one output terminal of the Nth stage delay circuit, and connects the other input terminal to the other output terminal of the Nth stage delay circuit; When N is an even number, one input terminal is connected to the other output terminal of the Nth delay circuit, and the other input terminal is connected to one output terminal of the Nth delay circuit. Each stage delay circuit inverts the signal at one input terminal and outputs it to one output terminal, inverts the signal at the other input terminal and outputs it to the other output terminal, and one input A first inverter circuit that inverts the signal at one end and outputs it to one output end, a second inverter circuit that inverts the signal at the other input end and outputs it to the other output end, A first FET having a gate connected to the output terminal and a drain connected to the other output terminal; a second FET having a source grounded, a gate connected to the other output terminal, and a drain connected to one output terminal; And a differential circuit including any of the above. It includes at least one or more inverter circuit pairs and one or more differential circuits.

  In the above, N = 4 may be sufficient.

  The first and second delay circuits are preferably configured by differential circuits, and the third and fourth delay circuits are preferably configured by inverter circuit pairs.

  One inverter circuit pair is configured as a NAND circuit and a NOR circuit. The NAND circuit has two inputs, one input terminal is used as one input terminal of the inverter circuit pair, and the other input terminal is used for oscillation control. Connected to the first terminal, the output terminal is one output terminal of the inverter circuit pair, the NOR circuit has two inputs, one input terminal is the other input terminal of the inverter circuit pair, and the other input terminal May be connected to the second terminal for oscillation control, and the output terminal may be the other output terminal of the inverter circuit pair.

  A variable current source for controlling the power supply current in at least one of the N-stage delay circuits may be provided.

  According to the semiconductor device as described above, at least one delay circuit is constituted by an inverter pair. Accordingly, the number of amplifiers connected in feedforward is reduced or unnecessary, load capacity is reduced, and high-speed oscillation operation is possible.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention. In FIG. 1, the oscillation circuit is configured to cascade the delay circuits 110, 120, 130, and 140. That is, the nodes 115 and 116 that are the outputs of the delay circuit 110 are connected to the respective inputs of the delay circuit 120, and the nodes 125 and 126 that are the outputs of the delay circuit 120 are connected to the respective inputs of the delay circuit 130, Nodes 135 and 136 which are outputs of the delay circuit 130 are connected to respective inputs of the delay circuit 140. Nodes 145 and 146 which are outputs of the delay circuit 140 at the final stage intersect and are fed back to the respective input terminals of the delay circuit 110 at the first stage.

  The delay circuit 110 constitutes a differential pair including an amplifier composed of complementary transistors 111 and 112 (corresponding to an inverter circuit) and an amplifier composed of complementary transistors 113 and 114 (corresponding to an inverter circuit). . The transistors 111 and 112 share a gate and a drain, respectively. The gate is connected to the node 146 of the delay circuit 140 in the preceding stage, and the drain is connected to the node 115. The source of the transistor 111 is connected to the power supply, and the source of the transistor 112 is connected to the ground. The transistors 113 and 114 share a gate and a drain, respectively. The gate is connected to the node 145 of the delay circuit 140 in the preceding stage, and the drain is connected to the node 116. The source of the transistor 113 is connected to the power supply, and the source of the transistor 114 is connected to the ground.

  The delay circuit 120 has the same configuration as the delay circuit 110, and the transistors 121, 122, 123, and 124, and the nodes 125 and 126 correspond to the transistors 111, 112, 113, and 114, and the nodes 115 and 116, respectively. The delay circuit 130 has the same configuration as the delay circuit 110, and the transistors 131, 132, 133, and 134, and the nodes 135 and 136 correspond to the transistors 111, 112, 113, and 114, and the nodes 115 and 116, respectively.

  The delay circuit 140 includes one amplifier (corresponding to a NAND circuit) composed of transistors 1411, 1412, 1421 and 1422, and another amplifier (corresponding to a NOR circuit) composed of transistors 1431, 1432, 1441 and 1442. Consists of. One amplifier and another amplifier form a differential pair (NAND circuit / NOR circuit pair).

  Transistors 1411 and 1421 have gates connected to node 135 and drains connected to node 145 together. Transistors 1412 and 1422 both have their gates connected to node 126, and the drain of transistor 1412 is connected to node 145. The sources of the transistors 1411 and 1412 are both connected to the power supply. The drain of the transistor 1422 is connected to the source of the transistor 1421, and the source of the transistor 1422 is connected to the ground.

  Transistors 1431 and 1441 have gates connected to node 136 and drains connected to node 146 together. Transistors 1432 and 1442 have gates connected to node 125, and the drain of transistor 1442 is connected to node 146. The sources of the transistors 1441 and 1442 are both connected to the ground. The drain of the transistor 1432 is connected to the source of the transistor 1431, and the source of the transistor 1432 is connected to the power supply.

  Next, the operation of the oscillation circuit configured as described above will be described. The oscillation circuit crosses the nodes 145 and 146 of the delay circuit 140 and feeds back to the respective input terminals of the delay circuit 110. Therefore, if the node 145 is at a low level and the node 146 is at a high level, the node 115 is at a low level, 116 is at a high level, the node 125 is at a high level, 126 is at a low level, the node 135 is at a low level, and 136 is at a high level. The node 145 changes from low level to high level, and 146 changes from high level to low level. As a result, the node 115 becomes high level, 116 becomes low level, the node 125 becomes low level, 126 becomes high level, the node 135 becomes high level, 136 becomes low level, the node 145 changes from high level to low level, 146 Transition from low level to high level. The oscillation operation is performed by repeating this.

  Next, a case where the nodes 115 and 116 are in the in-phase state will be described. When the nodes 115 and 116 are both at the low level, the nodes 125 and 126 are both at the high level, and the nodes 135 and 136 are both at the low level. At this time, since the transistor 1411 is turned on and 1421 is turned off, the node 145 is at a high level. Further, since the transistor 1442 is turned on and 1432 is turned off, the node 146 is at a low level. Therefore, the nodes 145 and 146 are output in reverse phase.

  When the nodes 115 and 116 are both at the high level, the nodes 125 and 126 are both at the low level, and the nodes 135 and 136 are both at the high level. At this time, the transistor 1412 is in an on state and 1422 is in an off state, so that the node 145 is at a high level. Further, since the transistor 1441 is turned on and 1431 is turned off, the node 146 is at a low level. Therefore, the nodes 145 and 146 are output in reverse phase.

  As described above, regardless of the initial state of the nodes 115 and 116, the nodes 145 and 146 are output in reverse phase and shift to the oscillation operation described above.

  According to the oscillation circuit as described above, the following effects are brought about.

  Regardless of the initial state of the oscillation circuit, the two outputs of the delay circuit 140 are reversed-phase outputs, which can be avoided as a trigger for oscillation and not oscillate. Thus, it is not necessary to provide the third and fourth amplifiers (transistors 27 and 29) provided in the conventional circuit of FIG.

  Compared with the conventional circuit of FIG. 6, the gate capacity of the delay circuit 140 is added to the nodes 125 and 126 of the delay circuit 120 as a load capacity in addition to the gate capacity of the delay circuit 130 of the next stage. However, when the node 125 transitions from the high level to the low level, the state of the node 146 does not transition, and thus the mirror effect does not appear. Further, when the node 126 transitions from the low level to the high level, the state of the node 145 does not transition, so that the mirror effect does not appear. Therefore, only the gate capacitance of the delay circuit 140 is added to the nodes 125 and 126 of the delay circuit 120, and the gate capacitance multiplied by the gain by the Miller effect is not added. It will not be.

  Also, when node 125 transitions from a low level to a high level and node 126 transitions from a high level to a low level, the transition of nodes 145 and 146 is caused by nodes 125 and 126 and bypasses delay circuit 130, so that mirror The effect appears. However, the delay time from the transition of the nodes 125 and 126 to the transition of the nodes 145 and 146 is not delayed, and does not hinder the speeding up of the oscillation operation.

  From the above, since the gate capacitance does not increase as in the prior art, the oscillation operation can be performed at higher speed.

  FIG. 2 is a diagram illustrating the relationship between the oscillation frequency and the current consumption obtained by the simulation in the oscillation circuit. The solid line represents the case of this embodiment, and the broken line represents the case of the conventional circuit. Oscillation frequency and current consumption are expressed by standardizing the maximum value of the conventional circuit as 1, respectively. When compared with the same current consumption, it is shown that the oscillation circuit of the present invention is approximately 35% faster than the conventional circuit.

  In the above description, an example in which the three-stage delay circuits 110, 120, and 130 are inverter circuit pairs is shown. However, the present invention is not limited to this, and an inverter circuit pair may be provided as each of N (N is an odd number of 3 or more) stages of delay circuits.

  FIG. 3 is a circuit diagram of an oscillation circuit according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. In the oscillation circuit in FIG. 3, the sources of the transistors 112, 114, 122, 124, 132, 134, 1422, 1441, and 1442 in FIG. 1 connected to the ground are connected to the common node 302. The transistor 300 constituting the variable current source is different from FIG. 1 in that the drain is connected to the node 302, the source is connected to the ground, and the control signal 301 is supplied to the gate.

  The current of the variable current source is made variable by changing the voltage of the control signal 301, and the delay times of the delay circuits 110, 120, 130 and 140 can be made variable. Thus, the oscillation frequency of the oscillation circuit can be controlled by the voltage of the control signal 301, and a function as a voltage control oscillation circuit used in a PLL or the like can be realized.

  In FIG. 3, the variable current source is common to all delay circuits. However, the variable current source may be provided in each of the delay circuits 110, 120, 130, and 140 as in the prior art shown in FIGS. It is clear that a voltage controlled oscillation circuit can be constructed. Further, the variable current source may be provided only on the ground side as shown in FIG. 3, or may be provided only on the power source side or on both the power source side and the ground side. Further, it is obvious that the voltage-controlled oscillation circuit can be configured even if the variable current source is provided not only in all the delay circuits but only in a part of the delay circuits, for example, the delay circuits 110 and 120.

  FIG. 4 is a circuit diagram of an oscillation circuit according to the third embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. The difference from the first embodiment is that the gates of the transistors 1432 and 1442 connected to the node 125 in FIG. 1 are connected to the terminal 202, and the gates of the transistors 1412 and 1422 connected to the node 126 are connected to the terminal 201. It is in the point connected to. The control signals of the terminals 201 and 202 are in an opposite phase relationship. If the terminal 201 is at a high level, the terminal 202 is at a low level, and if the terminal 201 is at a low level, the terminal 202 is at a high level.

  Further, the delay circuit 110a is further provided with feedforward-connected transistors 117 and 118, and the delay circuit 120a is further provided with feedforward-connected transistors 127 and 128, which is different from the first embodiment. The transistor 117 has a drain connected to the node 115, a gate connected to the node 116, and a source connected to the ground. The transistor 118 has a drain connected to the node 116, a gate connected to the node 115, and a source connected to the ground. The transistor 127 has a drain connected to the node 125, a gate connected to the node 126, and a source connected to the ground. The transistor 128 has a drain connected to the node 126, a gate connected to the node 125, and a source connected to the ground.

  Next, the operation of the oscillation circuit configured as described above will be described. Before the oscillation operation is started, the terminals 201 and 202 are set to a low level and a high level, respectively. Accordingly, the transistor 1412 is turned on and the transistor 1422 is turned off, so that the node 145 is at a high level. Further, since the transistor 1432 is turned off and the transistor 1442 is turned on, the node 146 is at a low level. As a result, the nodes 115 and 116 of the cascaded delay circuits are set to the high level and the low level, the nodes 125 and 126 are set to the low level and the high level, respectively, and the nodes 135 and 136 are set to the high level and the low level, respectively. The output signal of the circuit is in a reverse phase state.

  When starting the oscillation operation, the terminals 201 and 202 are changed to a high level and a low level, respectively. Accordingly, the transistor 1412 is turned off, the transistor 1422 is turned on, the transistor 1432 is turned on, and the transistor 1442 is turned off. Here, since the nodes 135 and 136 are at a high level and a low level, respectively, the nodes 145 and 146 of the delay circuit 140 transition to a low level and a high level, respectively. In response to this transition, the oscillation operation is started as in the first embodiment.

  The transistors 117, 118, 127, and 128 provided in the delay circuit 110a and the delay circuit 120a correct the difference in delay time due to the variation of each delay circuit by the feedforward action. Node 115 and node 116 are associated by transistors 117 and 118, and node 125 and node 126 are associated by transistors 127 and 128. As a result, even if a difference in delay time occurs between the node 135 and the node 136 and between the node 145 and the node 146 due to variations in the delay circuit, the node 115 and the node 116 and the node 125 and the node 126 maintain the reverse phase relationship. . Therefore, even if there is a difference in delay time due to variations in the delay circuit, the difference is accumulated and the oscillation does not stop, and the output of each delay element maintains the reverse phase and continues to oscillate.

  As described above, even when the gates of the transistors 1412, 1422, 1432, and 1442 of the delay circuit 140 are external terminals instead of the output of the delay circuit 120, the output of each delay circuit is set to a reverse phase output. Initialization can be performed, and the problem of no oscillation can be avoided.

  As a result, the dimensions of the transistors 117, 118, 127, and 128 corresponding to the third and fourth amplifiers provided in the conventional circuit of FIG. 5 can be greatly reduced. The dimension may be about 1/20 of the conventional circuit, and its influence on the delay time is so small that it can be ignored.

  Further, since it is not necessary to connect the node 125 and the node 126 of the delay circuit 120a to the delay circuit 140, the load capacity of the node 125 and the node 126 can be reduced, and the speed can be further increased as compared with the first embodiment. Is possible.

  In the above description, an example including four stages of delay circuits is shown. However, the present invention is not limited to this, and an N-stage configuration (N is an integer of 2 or more) may be used. In this case, when N is an odd number, the first-stage delay circuit connects one input terminal to one output terminal of the N-th delay circuit and the other input terminal to the N-th delay circuit. Connected to the other output terminal, and when N is an even number, one input terminal is connected to the other output terminal of the Nth delay circuit, and the other input terminal is one output of the Nth delay circuit. Connect to the end. Further, it is preferable that at least one of the N stages of delay circuits is configured as the delay circuit 130 or 140.

  Further, as described in the second embodiment, a variable current source for controlling the power supply current in at least one of the N-stage delay circuits may be provided.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention. It is a figure showing the relationship between the oscillation frequency and current consumption in this invention and the conventional oscillation circuit. FIG. 6 is a circuit diagram of an oscillation circuit according to a second example of the present invention. FIG. 6 is a circuit diagram of an oscillation circuit according to a third example of the present invention. It is a circuit diagram of the delay circuit which comprises the conventional oscillation circuit. It is a circuit diagram of the conventional oscillation circuit.

Explanation of symbols

110, 110a, 120, 120a, 130, 140 Delay circuits 115, 116, 125, 126, 135, 136, 145, 146, 302 Nodes 111, 112, 113, 114, 121, 122, 123, 124, 131, 132 133, 134, 1411, 1412, 1421, 1422, 1431, 1432, 1441, 1442, 300 Transistor 201, 202 Terminal 301 Control signal

Claims (7)

First to Nth inverters (N is an odd number of 3 or more) that inverts the signal of one input terminal and outputs the inverted signal to one output terminal, and inverts the signal of the other input terminal and outputs the inverted signal to the other output terminal A circuit pair,
NAND circuit / NOR circuit pair;
With
The first inverter circuit pair has one input terminal connected to the output terminal of the NOR circuit, the other input terminal connected to the output terminal of the NAND circuit,
For K = 2 to N (where K is an integer), the Kth inverter circuit pair has one input terminal connected to one output terminal of the K-1th inverter circuit pair, and the other input terminal connected. Connected to the other output terminal of the K-1th inverter circuit pair;
The NAND circuit has two inputs, one input terminal is connected to one output terminal of the Nth inverter circuit pair, and the other input terminal is connected to the other output terminal of the N-1th inverter circuit pair. connection,
The NOR circuit has two inputs, one input terminal is connected to the other output terminal of the Nth inverter circuit pair, and the other input terminal is connected to one output terminal of the N-1th inverter circuit pair. An oscillation circuit characterized by being connected.   2. The oscillation circuit according to claim 1, further comprising a variable current source that controls a power supply current in at least one of the inverter circuit pair and the NAND circuit / NOR circuit pair. N (N is an integer of 2 or more) stage delay circuit,
For K = 2 to N (where K is an integer), the Kth delay circuit has one input terminal connected to one output terminal of the (K-1) th delay circuit and the other input terminal connected to the K-1th delay circuit. Connected to the other output terminal of the delay circuit of the (K-1) th stage,
When N is an odd number, the first stage delay circuit connects one input terminal to one output terminal of the Nth delay circuit and the other input terminal to the other output of the Nth delay circuit. When N is an even number, one input terminal is connected to the other output terminal of the Nth stage delay circuit, and the other input terminal is connected to one output terminal of the Nth stage delay circuit. And
The delay circuit of each stage is
A pair of inverter circuits that inverts the signal at one input end and outputs it to one output end, inverts the signal at the other input end and outputs to the other output end;
A first inverter circuit that inverts a signal at one input terminal and outputs the inverted signal to one output terminal, a second inverter circuit that inverts a signal at the other input terminal and outputs the inverted signal to the other output terminal, and a source A first FET that is grounded and has a gate connected to one output end and a drain connected to the other output end, and a second FET that grounds the source, connects the gate to the other output end, and connects the drain to one output end A differential circuit comprising:
Consisting of either
An oscillation circuit comprising at least one inverter circuit pair and one or more differential circuits.   4. The oscillation circuit according to claim 3, wherein N = 4.   5. The oscillation circuit according to claim 4, wherein the first and second delay circuits are configured by the differential circuit, and the third and fourth delay circuits are configured by the inverter circuit pair. . One inverter circuit pair is configured as a NAND circuit and a NOR circuit,
The NAND circuit has two inputs, one input terminal is used as one input terminal of the inverter circuit pair, the other input terminal is connected to the first terminal for oscillation control, and the output terminal is connected to the inverter circuit pair. As one output end,
The NOR circuit has two inputs, one input terminal is used as the other input terminal of the inverter circuit pair, the other input terminal is connected to the second terminal for oscillation control, and the output terminal is connected to the inverter circuit pair. 6. The oscillation circuit according to claim 3, wherein the oscillation circuit is the other output terminal.   The oscillation circuit according to any one of claims 3 to 6, further comprising a variable current source that controls a power supply current in at least one of the N stages of delay circuits.

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