JP2009253366A - Variable delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continuously set fine delay time highly accurately in a wide variable width without being limited to the variable range of a variable load capacity in a simple and small-sized configuration. <P>SOLUTION: A variable delay circuit comprises: a delay part A and a delay part B connected in parallel between an input terminal and an output terminal, for outputting the input signals of the input terminal to the output terminal with delay time Ta and Tb (Ta>Tb) when operated alone respectively; and a current control part for inputting analog control signals X and Y, changing a current amount flowing to the delay part A and the delay part B correspondingly to the difference (X-Y), and setting the delay time continuously changing correspondingly to the difference (X-Y) between the delay time Ta and Tb. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a variable delay circuit capable of delaying an input signal and controlling a delay time.

  In optical transmission / reception systems, a small delay time is increased for input signals and clock signals to compensate for differences in path lengths of optical transmission lines, skew due to wavelength dispersion, etc., and skew due to differences in wiring length in semiconductor integrated circuits. A variable delay circuit that can be set with high accuracy and a wide variable width is required.

FIG. 9 shows a configuration example of a conventional variable delay circuit (Non-Patent Document 1).
In the figure, in the conventional variable delay circuit, a plurality of delay circuits 91 each having a variable load capacitance connected to an inverter are connected in cascade, the outputs of the respective delay circuits 91 are branched and input to a selector 92, one of which is input. By selecting and outputting, the delay time according to the capacitance value of each delay circuit and the number of stages of the delay circuit is set.
P. Chen, et al., "A Portable Digitally Controlled Oscillator Using Novel Varactors", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL.52, NO.5, MAY 2005

  The conventional variable delay circuit can take a wide variable range of the delay time according to the number of stages of the delay circuit, but if the delay time of each delay circuit is fixed, the minimum delay width is set to one delay circuit. The delay time is limited.

  In addition, in the configuration in which the delay time is set using a variable load capacity, the variable range of the load capacity is limited, so that the variable width in one stage is small, and in order to obtain a wide variable width, it is necessary to connect in multiple stages. was there. On the other hand, a large capacity may be used to obtain a wide variable width in one stage, but there is a problem that the waveform deteriorates when a high-speed signal is handled. Furthermore, in order to control the delay time with high accuracy, there is a problem that the circuit configuration becomes complicated and the circuit area increases.

  The present invention provides a variable delay circuit capable of continuously setting a minute delay time with high accuracy and a wide variable width without being limited to a variable range of a variable load capacitance with a simple and small configuration. For the purpose.

  The variable delay circuit of the present invention is connected in parallel between an input terminal and an output terminal, and outputs the input signal of the input terminal to the output terminal with delay times Ta and Tb (Ta> Tb) when operated individually. The delay unit A and the delay unit B and the analog control signals X and Y are input, the amount of current flowing through the delay unit A and the delay unit B is changed according to the difference (X−Y), and the delay times Ta and Tb A current control unit that sets a delay time that continuously changes according to the difference (X−Y).

  The current control unit has a configuration in which the collectors of two transistors that input analog control signals X and Y to the base are connected to the delay unit A and the delay unit B, and the common emitter is connected to the current source.

  A buffer circuit may be connected to the preceding stage of the delay unit A and the delay unit B, and the input terminal, the delay unit A, and the delay unit B may be connected to each other through each buffer circuit.

  A configuration in which a load capacitor is connected to the delay unit A, a peaking capacitor is connected to the delay unit B, or a peaking coil is connected to the delay unit B, and the delay times Ta and Tb are set so that Ta> Tb is satisfied. Good.

  In the variable delay circuit of the present invention, the current flowing through the delay unit A and the delay unit B having their own delay times Ta and Tb (Ta> Tb) is converted into the difference between the analog control signals X and Y using the current control unit. By controlling accordingly, the delay time can be continuously changed within the range of the delay times Ta and Tb. As a result, a minute delay time can be continuously varied with high accuracy and a wide variable width with a simple and small configuration.

(First embodiment)
FIG. 1 shows a first embodiment of the variable delay circuit of the present invention.
In the figure, a delay unit A11 and a delay unit B12 are connected in parallel between an input terminal IN and an output terminal OUT. The delay unit A11 and the delay unit B12 have their own delay times Ta and Tb (Ta> Tb), and when they are operated independently, the input signals at the input terminals are delayed by the delay times Ta and Tb (Ta> Tb). Output to the output terminal. A current control unit 13 is connected to the delay unit A11 and the delay unit B12. The current control unit 13 receives the analog control signals X and Y, changes the amount of current flowing through the delay unit A11 and the delay unit B12 according to the difference (X−Y), and determines the difference between the delay times Ta and Tb ( A delay time that continuously changes in accordance with (XY) is set.

(Second Embodiment)
FIG. 2 shows a second embodiment of the variable delay circuit of the present invention.
A feature of the present embodiment is that buffer circuits 14 and 15 are connected in front of the delay unit A11 and the delay unit B12 in the first embodiment, and the input terminal IN, the delay unit A11, and the delay are connected via the buffer circuits 14 and 15, respectively. Part B12 is connected. Thereby, mutual interference can be avoided regardless of the circuit configurations of the delay unit A11 and the delay unit B12 connected in parallel.

(Configuration example of delay unit)
FIG. 3 shows a first configuration example (basic configuration) of the delay unit A11 and the delay unit B12 shown in FIGS. The basic configuration of the delay unit is a buffer circuit using a differential transistor circuit, in which differential inputs IN and IN are connected to the bases of the differential transistors 21 and 22, and differential outputs having a predetermined delay from each collector. In this configuration, OUT and OUT are taken out.

  The second configuration example of the delay unit shown in FIG. 4 is a configuration in which load capacitors 31 and 32 are connected to the buffer circuit of FIG. The delay time increases by the rise time Tr and fall time Tf corresponding to the charge / discharge time. The third configuration example of the delay unit shown in FIG. 5 is a configuration in which a peaking capacitor 33 is connected to the buffer circuit of FIG. Since the peaking capacitor 33 works to reduce Tr and Tf, the delay time is reduced. The third configuration example of the delay unit shown in FIG. 6 is a configuration in which peaking coils 34 and 35 are connected to the buffer circuit of FIG. Similarly, the peaking coils 34 and 35 work to reduce Tr and Tf, so that the delay time is reduced.

  By combining the configuration using the load capacitors 31 and 32 as the delay unit A11 and the configuration using the peaking capacitor 33 or the peaking coils 34 and 35 as the delay unit B12, the inherent delay times Ta and Tb set for the respective units. Can be set such that Ta> Tb. Furthermore, by increasing the values of the load capacitors 31 and 32, the peaking capacitor 33, and the peaking coils 34 and 35, the delay times Ta and Tb can be increased, respectively, and the variable delay range can be expanded.

(Example configuration)
FIG. 7 shows an embodiment of the variable delay circuit according to the present invention.
In FIG. 7, the delay unit A11, the delay unit B12, the current control unit 13, and the buffer circuits 14 and 15 of the configuration of the present embodiment correspond to the second embodiment shown in FIG. The delay unit A11 has a configuration using the differential transistors 21 and 22 and the load capacitors 31 and 32 shown in FIG. 4, and the delay unit B12 uses the differential transistors 23 and 24 and the peaking capacitor 33 shown in FIG. It was the composition that was. Note that the peaking capacitor 33 of the delay unit B12 may be replaced with the peaking coils 34 and 35 shown in FIG. As a result, the delay times Ta and Tb of the delay unit A11 and the delay unit B12 are set so that Ta> Tb.

  The current control unit 13 has a collector connected to a common emitter of the differential transistors 21 and 22, a transistor 25 connected to the analog control signal X to the base, and a collector connected to a common emitter of the differential transistors 23 and 24. A transistor 26 having an analog control signal Y connected to the base and a current source 41 connected to a common emitter of the transistors 25 and 26 are configured.

When the analog control signals X and Y have a sufficient difference, for example, a difference of about ± 100 mV, the transistors 25 and 26 operate as switches, a current flows only in the delay unit A11 or only in the delay unit B12, and the delay time t is
t = Ta or t = Tb
Set to On the other hand, when the analog control signals X and Y have the same magnitude or the difference between them is small, a current corresponding to the difference (X−Y) flows through the delay unit A11 and the delay unit B12.
Ta>t> Tb
The delay time t is set.

FIG. 8 shows an operation example of the variable delay circuit of the present invention. Here, a pulse of one bit of 10 Gbit / s is shown. When the difference (X−Y) between the analog control signals X and Y is 0, the delay time t is
t = (Ta + Tb) / 2
It becomes. From this state, for example, if Y is fixed and X is increased, the delay time t approaches Ta, and if X exceeds a predetermined value, the delay time t becomes equal to Ta, and conversely if X is decreased, the delay time is increased. t approaches Tb, and eventually the delay time t becomes equal to Tb. That is, when the difference (X−Y) is in the range of approximately 0 to ± 100 mV, the delay time t is
Ta>t> Tb
When the difference is more than ± 100mV, the delay time is
t = Ta or t = Tb
It was confirmed that The variable delay range at this time was about 10 ps.

  Note that a larger variable delay amount can be continuously set by connecting the variable delay circuits in multiple stages.

The figure which shows 1st Embodiment of the variable delay circuit of this invention. The figure which shows 2nd Embodiment of the variable delay circuit of this invention. The figure which shows the 1st structural example (basic structure) of a delay part. The figure which shows the 2nd structural example of a delay part. The figure which shows the 3rd structural example of a delay part. The figure which shows the 4th structural example of a delay part. The figure which shows the Example structure of the variable delay circuit of this invention. The figure which shows the operation example of the variable delay circuit of this invention. The figure which shows the structural example of the conventional variable delay circuit.

Explanation of symbols

11 Delay part A
12 Delay part B
13 Current controller 14, 15 Buffer circuit 21, 22 Differential transistor 23, 24 Differential transistor 25, 26 Transistor 31, 32 Load capacity 33 Peaking capacity 34, 35 Peaking coil 41 Current source

Claims (6)

A delay unit A and a delay unit B that are connected in parallel between the input terminal and the output terminal and output the input signal of the input terminal to the output terminal with delay times Ta and Tb (Ta> Tb) when operated individually. When,
Analog control signals X and Y are input, the amount of current flowing through the delay unit A and the delay unit B is changed according to the difference (X−Y), and the difference (X−Y) between the delay times Ta and Tb. And a current control unit that sets a delay time that continuously changes in response to a variable delay circuit. The variable delay circuit according to claim 1,
The current control unit has a configuration in which collectors of two transistors that input analog control signals X and Y to a base are connected to the delay unit A and the delay unit B, and a common emitter is connected to a current source. A variable delay circuit. The variable delay circuit according to claim 1,
A variable circuit is characterized in that a buffer circuit is connected in front of each of the delay unit A and the delay unit B, and the input terminal and the delay unit A and the delay unit B are connected via the buffer circuits. Delay circuit. The variable delay circuit according to claim 1,
A variable delay circuit, wherein a load capacitor is connected to the delay unit A, and the delay times Ta and Tb are set such that Ta> Tb. The variable delay circuit according to claim 1,
A variable delay circuit, wherein a peaking capacitor is connected to the delay unit B, and the delay times Ta and Tb are set such that Ta> Tb. The variable delay circuit according to claim 1,
A variable delay circuit, wherein a peaking coil is connected to the delay unit B, and the delay times Ta and Tb are set such that Ta> Tb.

Images